AD AD8010 2000 200 ma output current high-speed amplifier Datasheet

a
200 mA Output Current
High-Speed Amplifier
AD8010
FEATURES
200 mA of Output Current
9 Load
SFDR –54 dBc @ 1 MHz
Differential Gain Error 0.04%, f = 4.43 MHz
Differential Phase Error 0.06, f = 4.43 MHz
Maintains Video Specifications Driving Eight Parallel
75 Loads
0.02% Differential Gain
0.03 Differential Phase
0.1 dB Gain Flatness to 60 MHz
THD –72 dBc @ 1 MHz, RL = 18.75 IP3 42 dBm @ 5 MHz, RL = 18.75 1 dB Gain Compression 21 dBm @ 5 MHz, RL = 100 230 MHz –3 dB Bandwidth, G = +1, RL = 18.75 800 V/s Slew Rate, RL = 18.75 25 ns Settling Time to 0.1%
Available in 8-Lead DIP, 16-Lead Wide Body SOIC and
Thermally Enhanced 8-Lead SOIC
CONNECTION DIAGRAMS
8-Lead DIP and SOIC
NC 1
The AD8010 is offered in three package options: an 8-lead DIP,
16-lead wide body SOIC and a low thermal resistance 8-lead
SOIC, and operates over the industrial temperature range of
–40°C to +85°C.
NC
7
+VS
+IN 3
6
OUT
–VS 4
5
NC
16-Lead Wide Body SOIC
NC 1
AD8010
16
NC
NC 2
15
NC
–IN 3
14
+VS
NC 4
13
NC
+IN 5
12
OUT
NC 6
11
NC
–VS 7
10
NC
NC 8
9
NC
NC = NO CONNECT
75
PRODUCT DESCRIPTION
The AD8010 is an ideal component choice for any application
that needs a driver that will maintain signal quality when driving
low impedance loads.
8
–IN 2
NC = NO CONNECT
APPLICATIONS
Video Distribution Amplifier
VDSL, xDSL Line Driver
Communications
ATE
Instrumentation
The AD8010 is a low power, high current amplifier capable of
delivering a minimum load drive of 175 mA. Signal performance
such as 0.02% and 0.03° differential gain and phase error is
maintained while driving eight 75 Ω back terminated video lines.
The current feedback amplifier features gain flatness to 60 MHz
and –3 dB (G = +1) signal bandwidth of 230 MHz and only
requires a typical of 15.5 mA supply current from ± 5 V supplies.
These features make the AD8010 an ideal component for Video
Distribution Amplifiers or as the drive amplifier within high data
rate Digital Subscriber Line (VDSL and xDSL) systems.
AD8010
VOUT1
RF
RG
VOUT2
VOUT3
+5V
VOUT4
RS
VIN
AD8010
VOUT5
RT
–5V
VOUT6
VOUT7
VOUT8
75
Figure 1. Video Distribution Amplifier
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD8010–SPECIFICATIONS
(@ 25C, VS = 5 V, G = +2, RL = 18.75 , RS+ = 150 , RF = RG = 604 (R-16),
RF = RG = 562 (N-8), RF = RG = 499 (R-8). TMIN = –40C, TMAX = +85C unless otherwise noted)
Model
DYNAMIC PERFORMANCE
–3 dB Bandwidth
0.1 dB Bandwidth
Large Signal Bandwidth
Peaking
Slew
Rise and Fall Time
Settling Time
NOISE/HARMONIC PERFORMANCE
Distortion
2nd Harmonic
3rd Harmonic
IMD
IP3
1 dB Gain Compression
Input Noise Voltage
Input Noise Current
Differential Gain
Differential Phase
Conditions
Min
Typ
G = +1, VOUT = 0.2 V p-p
G = +2, VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 4 V p-p
VOUT = 0.2 V p-p, < 5 MHz
VOUT = 2 V p-p
VOUT = 2 V p-p
0.1%, VOUT = 2 V p-p
180
130
30
230
190
60
90
0.02
800
2.0
25
MHz
MHz
MHz
MHz
dB
V/µs
ns
ns
–73
–58
–53
–67
–44
–77
–63
–57
–63
–50
–73
42
21
2
3
20
0.02
0.02
0.02
0.03
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
nV√Hz
pA√Hz
pA√Hz
%
%
Degrees
Degrees
VOUT = 2 V p-p
1 MHz
5 MHz
10 MHz
10 MHz, RL = 39 Ω
20 MHz
1 MHz
5 MHz
10 MHz
10 MHz, RL = 39 Ω
20 MHz
5 MHz ∆f = 10 kHz
5 MHz
5 MHz
f = 10 kHz
f = 10 kHz, +In
f = 20 kHz, –In
f = 4.43 MHz, RL = 150 Ω
f = 4.43 MHz, RL = 18.75 Ω
f = 4.43 MHz, RL = 150 Ω
f = 4.43 MHz, RL =18.75 Ω
DC PERFORMANCE
Input Offset Voltage
5
TMIN–TMAX
Offset Drift
Input Bias Current (–)
10
10
TMIN–TMAX
Input Bias Current (+)
6
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Common-Mode Rejection Ratio
Input Common-Mode Voltage Range
Open Loop Transresistance
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL = 18.75 Ω
RL = 150 Ω
Output Current
Short-Circuit Current
Capacitive Load Drive
+Input
–Input
VCM = ± 2.5 V
50
VOUT = ± 2.5 V
TMIN–TMAX
300
250
RL = 9 Ω
± 2.1
± 2.7
175
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
135
200
12
20
mV
mV
µV/°C
µA
µA
µA
µA
kΩ
Ω
pF
dB
V
kΩ
kΩ
± 2.5
± 3.0
200
240
40
V
V
mA
mA
pF
15.5
60
50
12
15
Unit
125
12.5
2.75
54
± 2.5
500
± 4.5
TMIN to TMAX
+VS = +4 V to +6 V, –VS = +5 V
+VS = +5 V, –VS = –4 V to –6 V
Max
66
56
± 6.0
17
20
V
mA
mA
dB
dB
Specifications subject to change without notice.
–2–
REV. B
AD8010
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation2
Plastic Package (N) . . . . . . Observe Power Derating Curves
Small Outline Package (R) . Observe Power Derating Curves
Wide Body SOIC (R-16) . . . Observe Power Derating Curves
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
The maximum power that can be safely dissipated by the
AD8010 is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature
of the plastic, approximately +150°C. Temporarily exceeding
this limit may cause a shift in parametric performance due to a
change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175°C for an extended period
can result in device failure.
While the AD8010 is internally short circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package: θJA = 90°C/W
8-Lead SOIC Package: θJA = 122°C/W
16-Lead SOIC Package: θJA = 73°C/W
MAXIMUM POWER DISSIPATION – Watts
3.0
TJ = 150C
2.5
8-LEAD MINI-DIP PACKAGE
2.0
16-LEAD SOIC
PACKAGE (WIDEBODY)
1.5
1.0
8-LEAD SOIC PACKAGE
0.5
0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – C
Figure 2. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Options
AD8010AN
AD8010AR
AD8010AR-16
AD8010AR-REEL
AD8010AR-REEL7
AD8010AR-16-REEL
AD8010AR-16-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic DIP
8-Lead Plastic SOIC
16-Lead Wide Body SOIC
REEL SOIC
REEL SOIC
REEL SOIC
REEL SOIC
N-8
SO-8
R-16
13" REEL
7" REEL
13" REEL
7" REEL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8010 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. B
–3–
WARNING!
ESD SENSITIVE DEVICE
60
dG
PERCENTAGE OF UNITS
50
DIFFERENTIAL GAIN – %
SAMPLE SIZE = 300
G = +2
f = 4.43MHz (PAL)
RL = 18.75
40
dG
30
DIFFERENTIAL GAIN dG IN %
DIFFERENTIAL PHASE d IN Degrees
d
d
d
20
dG
d
10
dG
d d
0.05
0.10
0.04
0.08
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
0.02
0.04
0.01
0.02
d d d d d
0
0
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13
dG (%)/d – Degrees
1
2
4
6
8
10
12
NUMBER OF VIDEO LOADS
–45
16
0
45
G = +2
VO = 2V p-p
RL AS SHOWN
–55
40
INTERCEPT POINT – dBm
–50
2ND
–60
RL = 18.75
–65
3RD
–70
–75
–80
3RD
2ND
RL = 100
–85
35
30
G = +2
RL = 18.75
25
20
15
10
–90
–95
1
2
3
4
5 6 7 8 9 10
FREQUENCY – MHz
5
20
1
10
FREQUENCY – MHz
6.5
6.20
6.15
G = +2
RL = 18.75
VO = 0.2V p-p
+85C
4
G = +2
VO = 0.2V p-p
NUMBER OF VIDEO
LOADS AS SHOWN
6.4
6.3
GAIN FLATNESS – dB
+25C
6.10
6.05
6.0
–40C
5.95
100
Figure 7. Two-Tone, 3rd Order IMD Intercept vs.
Frequency; G = +2, RL = 18.75 Ω
Figure 4. Harmonic Distortion vs. Frequency; G = +2
GAIN FLATNESS – dB
14
Figure 6. Differential Gain and Phase vs. Number of Video
Loads Over Temperature (–40 °C to +85 °C); f = 4.43 MHz
Figure 3. Distribution of Differential Gain (dG) and
Differential Phase (dφ); RL = 18.75 Ω
HARMONIC DISTORTION – dBc
0.06
0.03
DIFFERENTIAL PHASE – Degrees
AD8010–Typical Performance Characteristics
5.90
2
6
6.2
8
6.1
6.0
5.9
1
5.8
5.85
5.7
5.80
5.6
10
12
14
5.5
0.1
1
10
FREQUENCY – MHz
100
1
500
10
100
1000
FREQUENCY – MHz
Figure 5. Gain Flatness vs. Frequency Over Temperature
(–40 °C to +85 °C)
Figure 8. Gain Flatness vs. Frequency vs. Number of
Video Loads
–4–
REV. B
AD8010
0
5
4dBm
4dBm
G = +2
RL = 18.75
fO = 5MHz
f = 10kHz
–15
–25
–35
–45
–55
–65
GAIN = 6.6
RF
–20
–69dBm
RG
–30
–40
50
50
150
50
–50
500kHz TONE SPACING FROM
500kHz TO 5.5MHz WITH
4 MISSING TONES
–60
–70
–69dBm
–75
–80
–85
–90
4.965
4.985
5.0
5.015
FREQUENCY – MHz
5.035
0
FREQUENCY = 5MHz
G = +2
RL = AS SHOWN (SEE SCHEMATIC)
HARMONIC DISTORTION – dBc
RL = 18.75
–65
–75
RF
RL = 100
–85
RG
50 P
OUT
150
–105
–10
3
4
5
6
7
FREQUENCY – MHz
8
9
10
P
RL1 = FOR RL = 100 IN
RL1 = 23.1 FOR RL = 18.75
–8
–6
–4
–2
RL1
50
0
2
POUT – dBm
G = +2
VO = 2V p-p
f = 5MHz
–60
–55
–95
2
–55
–35
–45
1
Figure 12. Multitone Distortion; RL = 100 Ω
Figure 9. Intermodulation Distortion
TOTAL HARMONIC DISTORTION – dBc
PMEASURE = 10dBm
(FULL SCALE)
–10
–5
PMEASURE – dBm
INTERMODULATION DISTORTION – dBm
POUT
50
–65
–70
–75
–80
2ND
–85
3RD
–90
4
6
8
10
15
12
Figure 10. Total Harmonic Distortion vs. POUT; G = +2
100
200
300
LOAD – 400
500
Figure 13. Harmonic Distortion vs. Load
2
G = +1
G = +2
7.0
–2
G = +3
–3
–5
4.0
12
3.0
2.0
1.0
0.0
1
10
FREQUENCY – MHz
100
1
1000
Figure 11. Small Signal Closed-Loop Frequency
Response; RL = 18.75 Ω
REV. B
5.0
8
GAIN AS SHOWN
VO = 0.2V p-p
RL = 18.75
–6
–7
0.1
4
1
6.0
–1
GAIN – dB
NORMALIZED GAIN – dB
0
–4
G = +2
VO = 0.2V p-p
NUMBER OF VIDEO LOADS AS SHOWN
8.0
1
10
100
FREQUENCY – MHz
1000
Figure 14. Closed-Loop Frequency Response vs.
Number of Video Loads
–5–
AD8010
0
–10
–10
–20
–20
–30
CMRR – dB
PSRR – dB
–30
–40
–50
–PSRR
–40
–50
–60
–70
–60
+PSRR
–80
–70
–90
–80
0.03
0.1
1
10
100
–100
0.1
500
1
FREQUENCY – MHz
Figure 15. PSRR vs. Frequency
10
FREQUENCY – MHz
100
500
Figure 18. CMRR vs. Frequency
0
316
G = +2
100
31
10
3.1
1
0.31
45
100
PHASE
90
31.6
135
10
TRANSRESISTANCE
3.16
180
1
225
PHASE – Degrees
TRANSRESISTANCE – k
CLOSED-LOOP OUTPUT RESISTANCE – 1000
310
0.1
0.031
0.1
1
10
FREQUENCY – MHz
100
0.316
10k
500
G = +1
1
G = +2
1.0
GAIN AS SHOWN
VO = 2V p-p
RL = 18.75
NORMALIZED GAIN – dB
NORMALIZED GAIN – dB
1G
2.0
0
G = +2
–3
G = +10
–4
–5
0.0
–1.0
–2.0
–3.0
GAIN AS SHOWN
VO = 4V p-p
RL = 18.75
G = +10
–4.0
–5.0
–6
–7
0.1
100M
3.0
2
–2
1M
10M
FREQUENCY – Hz
Figure 19. Transresistance and Phase vs. Frequency;
RL = 18.75 Ω
Figure 16. Closed-Loop Output Resistance vs. Frequency
–1
100k
–6.0
1
10
FREQUENCY – MHz
100
–7.0
0.1
1000
Figure 17. Large Signal Frequency Response; VO = 2 V p-p
0
10
FREQUENCY – MHz
100
1000
Figure 20. Large Signal Frequency Response; VO = 4 V p-p
–6–
REV. B
AD8010
5
G = +1
RL = 18.75
VO = 0.2V p-p
0.2
3
0.1
2
0.05
1
VOLTS
VOLTS
0.15
G = +1
RL = 18.75
VO = 4V p-p
4
0
–0.05
0
–1
–0.1
–2
–0.15
–3
–4
–0.2
50mV
20ns
1V
20ns
–5
Figure 21. Small-Signal Pulse Response; G = +1
G = +2, –1
RL = 18.75
VO = 0.2V p-p
0.2
0.15
3
0.1
2
0.05
1
0
–1
–0.1
–2
–0.15
–3
–4
1V
20ns
50mV
Figure 22. Small-Signal Pulse Response; G = +2, –1
1000
INPUT CURRENT NOISE – pA/ Hz
INPUT VOLTAGE NOISE – nV/ Hz
10
100
1k
10k
100k
1M
100
INVERTING CURRENT
10
NONINVERTING CURRENT
1
10
10M
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 23. Input Voltage Noise vs. Frequency
REV. B
20ns
Figure 25. Large-Signal Pulse Response; G = +2, –1
100
10
0
–0.05
–0.2
1
G = +2, –1
RL = 18.75
VO = 4V p-p
4
VOLTS
VOLTS
Figure 24. Large-Signal Pulse Response; G = +1
Figure 26. Input Current Noise vs. Frequency
–7–
AD8010
Driving Capacitance Loads
G = +6
RF = 604
RL = 18.75
VOLTS
INPUT
The AD8010 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 28. The inset figure shows the
optimum value for RSERIES vs. capacitive load. It is worth noting
that the frequency response of the circuit when driving large
capacitive loads will be dominated by the passive roll-off of
RSERIES and CL.
OUTPUT
0
INPUT (500mV/DIV)
OUTPUT (1V/DIV)
LAYOUT CONSIDERATIONS
100ns
The specified high speed performance of the AD8010 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
Figure 27. Overdrive Recovery; G = +6
OVERDRIVE RECOVERY
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide low impedance
path. The ground plane should be removed from the area near
the input pins to reduce the parasitic capacitance.
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 27, the AD8010 recovers
within 35 ns from negative overdrive and within 75 ns from
positive overdrive.
–VS
+VS
THEORY OF OPERATION
The AD8010 is a current feedback amplifier optimized for high
current output while maintaining excellent performance with
respect to flatness, distortion and differential gain/phase. As a
video distribution amplifier, the AD8010 will drive up to 12
parallel video loads (12.5 Ω) from a single output with 0.04%
differential gain and 0.04° differential phase errors. This means
that, unlike designs with one driver per output, any output is a
true reflection of the signal on all other outputs.
FB
C1
+
150
VIN
RBT
RT
RF
The high output current capability of the AD8010 also make it
useful in xDSL applications. The AD8010 can drive a 12.5 Ω
single-ended or 25 Ω differential load with low harmonic distortion. This makes it useful in designs that utilize a step-up
transformer to drive a twisted-pair transmission line.
The standard noninverting closed-loop configuration with the
recommended power supply bypassing technique is shown in
Figure 29. Ferrite beads (Amidon Associates, Torrance CA,
Part Number 43101) are used to suppress high frequency power
supply energy on the DUT supply lines at the DUT. C1 and C2
each represent the parallel combination of a 47 µF (16 V) tantalum electrolytic capacitor, a 10 µF (10 V) tantalum electrolytic
capacitor and a 0.1 µF ceramic chip capacitor. Connect C1
from the +VS pin to the –VS pin. Connect C2 from the –VS pin
to signal ground.
GAIN AS SHOWN
VO = 0.2V p-p
w/ 30% OVERSHOOT
CAPACITIVE LOAD – pF
RF
RG
RS
150
VIN
10
50
RL
Figure 29. Standard Noninverting Closed-Loop Configuration with Recommended Bypassing Technique
200
G = +5
C2
+
RG
To achieve these levels of performance special precautions with
respect to supply bypassing are recommended (Figure 29). This
configuration minimizes the contribution from high frequency
supply rejection to differential gain and phase errors as well as
reducing distortion due to harmonic energy in the power supplies.
100
ZO
AD8010
VOUT
CL
The feedback resistor should be located close to the inverting
input pin in order to keep the parasitic capacitance at this node
to a minimum. Parasitic capacitances of less than 1 pF at the
inverting input can significantly affect high speed performance.
G = +2
G = +1
1
0
5
10
RS – 15
Stripline design techniques should be used for long traces
(greater than about 3 cm). These should be designed with a
characteristic impedance (ZO) of 50 Ω or 75 Ω and be properly
terminated at each end.
20
Figure 28. Capacitive Load Drive vs. Series Resistor for
Various Gains
–8–
REV. B
AD8010
The bypassing scheme that is used for the AD8010 requires
special attention. It was found that the conventional technique
of bypassing each power pin individually to ground can have an
adverse effect on the differential phase error of the circuit. The
cause of this is attributed to the fact that there is an internal
compensation capacitor in the AD8010 that is referenced to the
negative supply.
APPLICATIONS
Video Distribution Amplifier
The AD8010 is optimized for the specific function of providing
excellent video performance when driving multiple video loads
in parallel. Significant power is saved and heat sinking is greatly
simplified because of the ability of the AD8010 to obtain this
performance when running on a ± 5 V supply. However, due to
the high currents that flow when driving many parallel video
loads, special layout and bypassing techniques are required to
assure optimal performance.
The recommended technique is to connect parallel bypass
capacitors from the positive supply to the negative supply and
then to bypass the negative supply to ground. For high frequency bypassing, 0.1 µF ceramic capacitors are recommended.
These should be placed within a few millimeters of the power
pins and should preferably be chip type capacitors.
When designing a video distribution amplifier with the AD8010, it
is very important to keep in mind where the high (ac) currents
will flow. These paths include the power supply pins of the chip
along with the bypass capacitors and the return path for these
capacitors, the output circuits and the return path of the output
current from the loads.
The high currents that can potentially flow through the power
supply pins require large bypassing capacitors. These should be
low inductance tantalum types and at least 47 µF. The ground
side of the capacitor that bypasses the negative supply should be
brought to a single point ground that is the common for the
returns of the outputs.
In general, any loops that are formed by any of the above paths
should be made as small as possible. Large loops are both generators and receivers of magnetic fields and can cause undesired
coupling of signals that lowers the performance of the amplifier.
Effects that have not been seen before in other op amp circuits
might arise because of the high currents. Most op amp circuits
output, at most, tens of milliamps and do not require extremely
tight video specifications, while a video distribution amplifier
can output hundreds of milliamps and require extremely low
differential gain and phase errors.
Figure 30 shows a circuit for making an N-channel video distribution amplifier. As a practical matter, the AD8010 can readily
drive eight standard 150 Ω video loads. When driving up to 12
video loads, there is minimal degradation in video performance.
Another important consideration when driving multiple cables
is the high frequency isolation between the outputs of the
cables. Due to its low output impedance, the AD8010 achieves
better than 46 dB of output-to-output isolation at 5 MHz driving back terminated 75 Ω cables.
+5V
FB
499
499
75
AD8010
150
VIN
C1
75
RL1
75
RL2
75
RLN
75
75
C2
FB
–5V
75
Figure 30. An N-Channel Video Distribution Amplifier Using An AD8010.
NOTE: Please see Figure 29 for Recommended Bypassing Technique.
REV. B
–9–
AD8010
Differential Line Driver
In the circuit in Figure 31 the A device is configured as a gainof-two follower, while the B device is a gain-of-two inverter.
These will produce a differential output signal whose maximum
value is twice the peak-to-peak value of the maximum output
of one device. For this circuit a 12 V peak-to-peak output can
be obtained.
Twisted pair transmission lines are more often being used for
high frequency analog and digital signals. Over long distances,
however, the attenuation characteristics of these lines can
degrade the performance of the transmission system. To compensate for this, larger signals are transmitted, which after the
attenuation, will still have useful signal strength.
The op amps drive a 1:2 step-up transformer that drives a
100 Ω transmission line. Since the impedance reflected back to
the primary varies as the square of the turns ratio, it will appear
as 25 Ω at the primary. This source terminating resistor is split
as a 12.4 Ω resistor at the output of each device.
The high output current of two AD8010s can be used along
with a transformer to create a high power differential line driver.
The differential configuration effectively doubles the output
swing, while the step-up transformer further increases the output voltage.
The circuit shown is capable of delivering 12 V p-p to the line
and operates with a –3 dB bandwidth of 40 MHz. The peak
current output of either op amp is 100 mA.
499
499
AD8010
12.4
+6
150
VIN
402
806
AD8010
100
12.4
1:2 –6
150
Figure 31. High Output Differential Line Driver Using Two AD8010s.
NOTE: Please see Figure 29 for Recommended Bypassing Technique.
–10–
REV. B
AD8010
Closed-Loop Gain and Bandwidth
Table I. –3 dB Bandwidth and Slew Rate vs. Closed-Loop
Gain and Resistor Values
The AD8010 is a current feedback amplifier optimized for use
in high performance video and data acquisition applications.
Since it uses a current feedback architecture, its closed-loop
–3 dB bandwidth is dependent on the magnitude of the feedback
resistor. The desired closed-loop bandwidth and gain are obtained
by varying the feedback resistor (RF) to set the bandwidth, and
varying the gain resistor (RG) to set the desired gain. The characteristic curves and specifications for this data sheet reflect the
performance of the AD8010 using the values of RF noted at the
top of the specifications table. If a greater –3 dB bandwidth
and/or slew rate is required (at the expense of video performance),
Table I provides the recommended resistor values. Figure 32
shows the test circuit and conditions used to produce Table I.
Package: N-8
Closed-Loop
Gain
RF ()
RG ()
–3 dB BW
(MHz)
Slew Rate
(V/s)
+1
+2
+5
+10
453
374
348
562
374
86.6
61.9
285
255
200
120
900
900
800
550
Closed-Loop
Gain
RF ()
RG ()
–3 dB BW
(MHz)
Slew Rate
(V/s)
+1
+2
+5
+10
412
392
392
604
392
97.6
66.5
245
220
160
95
900
900
800
550
Closed-Loop
Gain
RF ()
RG ()
–3 dB BW
(MHz)
Slew Rate
(V/s)
+1
+2
+5
+10
392
374
348
499
374
86.6
54.9
345
305
220
135
950
1000
1000
650
∞
Package: R-16
Effect of Feedback Resistor Tolerance on Gain Flatness
Because of the relationship between the 3 dB bandwidth and the
feedback resistor, the fine scale gain flatness will, to some extent,
vary with feedback resistor tolerance. It is therefore recommended
that resistors with a 1% tolerance be used if it is desired to maintain flatness over a wide range of production lots. In addition,
resistors of different construction have different associated parasitic capacitance and inductance. Metal-film resistors were used
for the bulk of the characterization for this data sheet. It is possible that values other than those indicated will be optimal for
other resistor types.
Quality of Coaxial Cable
Optimum flatness when driving a coax cable is possible only
when the driven cable is terminated at each end with a resistor
matching its characteristic impedance. If the coax was ideal,
then the resulting flatness would not be affected by the length of
the cable. While outstanding results can be achieved using inexpensive cables, it should be noted that some variation in flatness
due to varying cable lengths may be experienced.
∞
Package: SO-8
∞
1. VO = 0.2 V p-p for –3 dB Bandwidth.
2. VO = 2 V p-p for Slew Rate.
3. Bypassing per Figure 29.
VIN
150
VOUT
50
RF
18.75
RG
Figure 32. Test Circuit for Table I
REV. B
–11–
AD8010
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic Mini-DIP
(N-8)
8
5
1
C01047a–0–12/00 (rev. B)
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
4
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
PIN 1
0.0098 (0.25)
0.0040 (0.10)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
SEATING (1.27)
0.0098 (0.25)
PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
0.0196 (0.50)
45
0.0099 (0.25)
8
0
0.0500 (1.27)
0.0160 (0.41)
16-Lead Wide Body SOIC
(R-16)
9
1
8
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
PRINTED IN U.S.A.
16
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.4133 (10.50)
0.3977 (10.00)
0.0291 (0.74)
45
0.0098 (0.25)
8 0.0500 (1.27)
0.0192 (0.49)
0 0.0157 (0.40)
SEATING 0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
–12–
REV. B