Agere FW801A Low-power phy ieee 1394a-2000 one-cable transceiver/arbiter device Datasheet

Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Distinguishing Features
■
■
■
■
■
■
■
■
■
■
■
Compliant with IEEE Standard 1394a-2000,
IEEE Standard for a High Performance Serial
Bus Amendment 1.
■
■
■
Supports connection debounce.
■
Supports multispeed packet concatenation.
■
Supports PHY pinging and remote PHY access
packets.
Low power consumption during powerdown or
microlow-power sleep mode.
■
Fully supports suspend/resume.
■
Supports PHY-link interface initialization and reset.
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
■
Supports 1394a-2000 register set.
■
While unpowered and connected to the bus, will
not drive TPBIAS on the connected port even if
receiving incoming bias voltage on the port.
■
Does not require external filter capacitors for PLL.
■
Does not require a separate 5 V supply for 5 V link
controller interoperability.
■
Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies.
■
Interoperable with 1394 link-layer controllers using
5 V supplies.
1394a-2000 compliant common mode noise filter
on incoming TPBIAS.
Powerdown features to conserve energy in battery-powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports power down.
— Automatic microlow-power sleep mode during
suspend.
■
Provides one fully compliant cable port at
100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
Supports LPS/link-on as a part of PHY-link interface.
Supports provisions of IEEE 1394-1995 Standard
for a High Performance Serial Bus.
Fully interoperable with FireWire† implementation
of IEEE 1394-1995.
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
Separate cable bias and driver termination voltage
supply for the port.
Meets Intel ‡ Mobile Power Guideline 2000.
Other Features
■
48-pin TQFP package.
■
Single 3.3 V supply operation.
■
■
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Features
■
■
■
■
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
Node power-class information signaling for system
power management.
Multiple separate package signals provided for
analog and digital supplies and grounds.
Fully supports OHCI requirements.
Supports arbitrated short bus reset to improve
utilization of the bus.
Supports ack-accelerated arbitration and fly-by
concatenation.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
† FireWire is a registered trademark of Apple Computer, Inc.
‡ Intel is a registered trademark of Intel Corporation.
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Table of Contents
Contents
Page
Distinguishing Features ............................................................................................................................................ 1
Features ................................................................................................................................................................... 1
Other Features ......................................................................................................................................................... 1
Description ................................................................................................................................................................ 3
Signal Information ..................................................................................................................................................... 6
Application Information ...........................................................................................................................................10
Crystal Selection Considerations ............................................................................................................................11
1394 Application Support Contact Information .......................................................................................................12
Absolute Maximum Ratings ....................................................................................................................................12
Electrical Characteristics ........................................................................................................................................13
Timing Characteristics ............................................................................................................................................16
Timing Waveforms ..................................................................................................................................................17
Internal Register Configuration ...............................................................................................................................18
Outline Diagrams ....................................................................................................................................................23
Ordering Information ...............................................................................................................................................23
List of Figures
Figures
Page
Figure 1. Block Diagram ........................................................................................................................................... 5
Figure 2. Pin Assignments ........................................................................................................................................ 6
Figure 3. Typical External Component Connections ..............................................................................................10
Figure 4. Typical Port Termination Network ...........................................................................................................11
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms .............................................................17
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms .......................................................................17
List of Tables
Tables
Page
Table 1. Signal Descriptions ..................................................................................................................................... 7
Table 2. Absolute Maximum Ratings ......................................................................................................................12
Table 3. Analog Characteristics ..............................................................................................................................13
Table 4. Driver Characteristics ...............................................................................................................................14
Table 5. Device Characteristics ..............................................................................................................................15
Table 6. Switching Characteristics .........................................................................................................................16
Table 7. Clock Characteristics ................................................................................................................................16
Table 8. PHY Register Map for the Cable Environment ........................................................................................18
Table 9. PHY Register Fields for the Cable Environment ......................................................................................18
Table 10. PHY Register Page 0: Port Status Page ................................................................................................20
Table 11. PHY Register Port Status Page Fields ...................................................................................................21
Table 12. PHY Register Page 1: Vendor Identification Page .................................................................................22
Table 13. PHY Register Vendor Identification Page Fields ....................................................................................22
2
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Description
serial data bits. The serial data bits are split into two,
four, or eight parallel streams, resynchronized to the
local system clock, and sent to the associated LLC.
The received data is also transmitted (repeated) out of
the other active (connected) cable ports.
The Agere Systems Inc. FW801A device provides the
analog physical layer functions needed to implement a
one-port node in a cable-based IEEE 1394-1995 and
IEEE 1394a-2000 network.
The cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connection status, for initialization and arbitration, and for
packet reception and transmission. The PHY is
designed to interface with a link-layer controller (LLC).
The PHY requires either an external 24.576 MHz crystal or crystal oscillator. The internal oscillator drives an
internal phase-locked loop (PLL), which generates the
required 400 MHz reference signal. The 400 MHz reference signal is internally divided to provide the
49.152 MHz, 98.304 MHz, and 196.608 MHz clock signals that control transmission of the outbound encoded
strobe and data information. The 49.152 MHz clock
signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The powerdown function,
when enabled by the PD signal high, stops operation of
the PLL and disables all circuitry except the cable-notactive signal circuitry.
Both the TPA and TPB cable interfaces incorporate
differential comparators to monitor the line states
during initialization and arbitration. The outputs of
these comparators are used by the internal logic to
determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage.
The value of this common-mode voltage is used during
arbitration to set the speed of the next packet
transmission. In addition, the TPB channel monitors
the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias
voltage. This monitor is called bias-detect.
The TPBIAS circuit monitors the value of incoming
TPA pair common-mode voltage when local TPBIAS is
inactive. Because this circuit has an internal current
source and the connected node has a current sink, the
monitored value indicates the cable connection status.
This monitor is called connect-detect.
Both the TPB bias-detect monitor and TPBIAS
connect-detect monitor are used in suspend/resume
signaling and cable connection detection.
The PHY supports an isolation barrier between itself
and its LLC. When /ISO is tied high, the link interface
outputs behave normally. When /ISO is tied low,
internal differentiating logic is enabled, and the outputs
become short pulses, which can be coupled through a
capacitor or transformer as described in the
IEEE 1394-1995 Annex J. To operate with bus-keeper
isolation, the /ISO pin of the FW801A must be tied
high.
The PHY provides a 1.86 V nominal bias voltage for
driver load termination. This bias voltage, when seen
through a cable by a remote receiver, indicates the
presence of an active connection. The value of this
bias voltage has been chosen to allow interoperability
between transceiver chips operating from 5 V or 3 V
nominal supplies. This bias voltage source should be
stabilized by using an external filter capacitor of
approximately 0.33 µF.
Data bits to be transmitted through the cable ports are
received from the LLC on two, four, or eight data lines
(D[0:7]), and are latched internally in the PHY in
synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and
transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or
393.216 Mbits/s as the outbound data-strobe
information stream. During transmission, the encoded
data information is transmitted differentially on the TPA
and TPB cable pair(s).
The transmitter circuitry, the receiver circuitry, and the
twisted-pair bias voltage circuity are all disabled with a
powerdown condition. The powerdown condition
occurs when the PD input is high. The port transmitter
circuitry, the receiver circuitry, and the TPBIAS output
are also disabled when the port is disabled,
suspended, or disconnected.
During packet reception, the TPA and TPB
transmitters of the receiving cable port are disabled,
and the receivers for that port are enabled. The
encoded data information is received on the TPA and
TPB cable pair. The received data-strobe information
is decoded to recover the receive clock signal and the
Agere Systems Inc.
The line drivers in the PHY operate in a highimpedance current mode and are designed to work
with external 112 Ω line-termination resistor networks.
One network is provided at each end of each twistedpair cable. Each network is composed of a pair of
series-connected 56 Ω resistors. The midpoint of the
pair of resistors that is directly connected to the
twisted-pair A (TPA) signals is connected to the
3
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Description (continued)
TPBIAS voltage signal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B
(TPB) signals is coupled to ground through a parallel
RC network with recommended resistor and capacitor
values of 5 kΩ and 220 pF, respectively.
The value of the external resistors are specified to
meet the standard specifications when connected in
parallel with the internal receiver circuits.
The driver output current, along with other internal
operating currents, is set by an external resistor. This
resistor is connected between the R0 and R1 signals
and has a value of 2.49 kΩ ± 1%.
The FW801A supports suspend/resume as defined in
the IEEE 1394a-2000 specification. The suspend
mechanism allows the FW801A port to be put into a
suspended state. In this state, the port is unable to
transmit or receive data packets, however, it remains
capable of detecting connection status changes and
detecting incoming TPBias. When the FW801A port is
suspended, all circuits except the bias voltage
reference generator, and bias detection circuits are
powered down, resulting in significant power savings.
The use of suspend/resume is recommended.
The signal, C/LKON, as an input, indicates whether a
node is a contender for bus manager. When the
C/LKON signal is asserted, it means the node is a contender for bus manager. When the signal is not
asserted, it means that the node is not a contender.
The C bit corresponds to bit 20 in the self-ID packet
(see Table 4-29 of the IEEE 1394-1995 standard for
additional details).
The power-class bits of the self-ID packet do not have
a default value. These bits can be initialized and read/
written through the LLC using Figure 6-1 (PHY Register Map) of the IEEE 1394a-2000 standard. See Table
8 for the address space of the Pwr_class register.
A powerdown signal (PD) is provided to allow a powerdown mode where most of the PHY circuits are
powered down to conserve energy in battery-powered
applications. The internal logic in FW801A is reset as
long as the powerdown signal is asserted. A cable status signal, CNA, provides a high output when none of
the twisted-pair cable ports are receiving incoming
bias voltage. This output is not debounced. The CNA
output can be used to determine when to power the
PHY down or up. In the powerdown mode, all circuitry
is disabled except the CNA circuitry. It should be noted
that when the device is powered down, it does not act
in a repeater mode.
4
Data Sheet, Rev. 1
June 2001
When the power supply of the PHY is removed while
the twisted-pair cables are connected, the PHY transmitter and receiver circuitry has been designed to
present a high impedance to the cable in order to not
load the TPBIAS signal voltage on the other end of the
cable.
For reliable operation, the TPBn signals must be terminated using the normal termination network regardless
of whether a cable is connected to a port or not connected to a port. When the port does not have a cable
connected, internal connect-detect circuitry will keep
the port in a disconnected state.
Note: All gap counts on all nodes of a 1394 bus must
be identical. This may be accomplished by using
PHY configuration packets (see Section 4.3.4.3
of IEEE 1394-1995 standard) or by using two
bus resets, which resets the gap counts to the
maximum level (3Fh).
The link power status (LPS) signal works with the
C/LKON signal to manage the LLC power usage of the
node. The LPS signal indicates that the LLC of the
node is powered up or powered down. If LPS is inactive for more than 1.2 µs and less than 25 µs, PHY/link
interface is reset. If LPS is inactive for greater than
25 µs, the PHY will disable the PHY/link interface to
save power. If the PHY then receives a link-on packet,
the C/LKON signal is activated to output a 6.114 MHz
signal, which can be used by the LLC to power itself
up. Once the LLC is powered up, the LPS signal communicates this to the PHY and the PHY/link interface
is enabled. C/LKON signal is turned off when LPS is
active or when a bus reset occurs, provided the interrupt that caused C/LKON is not present.
When the PHY/link interface is in the disabled state,
the FW801A will automatically enter a low-power
mode, if all ports are inactive (disconnected, disabled,
or suspended). In this low-power mode, the FW801A
disables its PLL and also disables parts of reference
circuitry depending on the state of the ports (some reference circuitry must remain active in order to detect
incoming TP bias). The lowest power consumption (the
microlow-power sleep mode) is attained when all ports
are either disconnected or disabled with the ports interrupt enable bit cleared. The FW801A will exit the lowpower mode when the LPS input is asserted high or
when a port event occurs that requires the FW801A to
become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or disconnection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Description (continued)
Two of the signals are used to set up various test conditions used in manufacturing. These signals (SE and
SM) should be connected to VSS for normal operation.
The SYSCLK output will become active (and the PHY/
link interface will be initialized and become operative)
within 3 ms after LPS is asserted high, when the
FW801A is in the low-power mode.
CPS
LPS
RECEIVED
DATA
DECODER/
RETIMER
/ISO
CNA
SYSCLK
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R0
R1
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
LINK
INTERFACE
I/O
TPA0+
TPA0–
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
TPBIAS0
CABLE PORT 0
TPB0+
TPB0–
C/LKON
SE
SM
PD
/RESET
TRANSMIT
DATA
ENCODER
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
XI
XO
5-5459.e (F)r.2
Figure 1. Block Diagram
Agere Systems Inc.
5
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
CTL0
1
CTL1
2
D0
LREQ
VSS
SYSCLK
/RESET
XO
XI
PLLVSS
PLLVDD
VSS
VDD
R1
R0
48
47
46
45
44
43
42
41
40
39
38
37
Signal Information
36
VSSA
35
VSSA
3
34
VDDA
D1
4
33
VDDA
VDD
5
32
TPBIAS0
D2
6
31
TPA0+
30
TPA0–
PIN #1 IDENTIFIER
AGERE FW801A
23
24
SM
VDDA
SE
25
22
12
VDD
VSS
21
VSSA
VSS
26
20
11
CPS
D7
19
VSSA
/ISO
27
18
10
PD
D6
17
TPB0–
C/LKON
28
16
9
VDD
D5
15
TPB0+
VSS
29
14
8
LPS
D4
13
7
CNA
D3
5-7302.a (F) R.03
Note: Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Figure 2. Pin Assignments
6
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Signal Information (continued)
Table 1. Signal Descriptions
Pin
Signal*
Type
Name/Description
17
C/LKON
I/O
Bus Manager Capable Input and Link-On Output. On hardware reset,
this pin is used to set the default value of the contender status indicated
during self-ID. The bit value programming is done by tying the signal
through a 10 kΩ resistor to VDD (high, bus manager capable) or to GND
(low, not bus manager capable). Using either the pull-up or pull-down
resistor allows the link-on output to override the input value when necessary.
After hardware reset, this pin is set as an output. If the LPS is inactive,
C/LKON indicates one of the following events by asserting a 6.114 MHz
signal.
1. FW801A receives a link-on packet addressed to this node.
2. Port_event register bit is 1.
3. Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the
Resume_int register bit is also 1. Once activated, the C/LKON output will
continue active until the LPS becomes active. The PHY also deasserts
the C/LKON output when a bus reset occurs, if the C/LKON is active due
solely to the reception of a link-on packet.
Note: If an interrupt condition exists which would otherwise cause the C/
LKON output to be activated if the LPS were inactive, the C/LKON
output will be activated when the LPS subsequently becomes inactive.
13
CNA
O
Cable-Not-Active Output. CNA is asserted high when none of the PHY
ports are receiving an incoming bias voltage. This circuit remains active
during the powerdown mode.
20
CPS
I
Cable Power Status. CPS is normally connected to the cable power
through a 400 kΩ resistor. This circuit drives an internal comparator that
detects the presence of cable power. This information is maintained in
one internal register and is available to the LLC by way of a register read
(see Table 8, Register 0).
1
CTL0
I/O
2
CTL1
Control I/O. The CTLn signals are bidirectional communications control
signals between the PHY and the LLC. These signals control the passage
of information between the two devices. Bus-keeper circuitry is built into
these terminals.
3, 4, 6, 7,
8, 9, 10,
11
D[0:7]
I/O
Data I/O. The Dn signals are bidirectional and pass data between the
PHY and the LLC. Bus-keeper circuitry is built into these terminals.
19
/ISO
I
Link Interface Isolation Disable Input (Active-Low). /ISO controls the
operation of an internal pulse differentiating function used on the PHYLLC interface signals, CTLn and Dn, when they operate as outputs. When
/ISO is asserted low, the isolation barrier is implemented between PHY
and its LLC (as described in Annex J of IEEE 1394-1995). /ISO is normally tied high to disable isolation differentiation. Bus-keepers are
enabled when
/ISO is high (inactive) on CTL, D, and LREQ. When /
ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note AP98-074CMPR for more information on isolation.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Agere Systems Inc.
7
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Signal Information (continued)
Table 1. Signal Descriptions (continued)
Pin
Signal*
Type
Name/Description
14
LPS
I
Link Power Status. LPS is connected to either the VDD supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for
greater than 25 µs, the PHY will disable the PHY/Link interface to save
power. FW801A continues its repeater function.
48
LREQ
I
Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
18
PD
I
Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW801A logic is
kept in the reset state as long as PD is asserted. PD terminal is provided
for backward compatibility. It is recommended that the FW801A be
allowed to manage its own power consumption using suspend/resume in
conjunction with LPS. C/LKON features are defined in 1394a-2000.
41
PLLVDD
—
Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry
portion of the device.
42
PLLVSS
—
Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground
plane.
37
R0
I
38
R1
45
/RESET
23
SE
24
SM
46
SYSCLK
31
TPA0+
30
TPA0−
29
TPB0+
Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
I
Reset (Active-Low). When /RESET is asserted low (active), the FW801A
is reset. An internal pull-up resistor, which is connected to VDD, is provided,
so only an external delay capacitor is required. This input is a standard
logic buffer and can also be driven by an open-drain logic output buffer.
I
Test Mode Control. SE is used during the manufacturing test and should
be tied to VSS.
I
Test Mode Control. SM is used during the manufacturing test and should
be tied to VSS.
O
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
8
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Signal Information (continued)
Table 1. Signal Descriptions (continued)
Pin
Signal*
Type
Name/Description
28
TPB0−
32
TPBIAS0
5, 16, 22,
39
VDD
—
Digital Power. VDD supplies power to the digital portion of the device.
25, 33, 34
VDDA
—
Analog Circuit Power. VDDA supplies power to the analog portion of the
device.
12, 15, 21,
40, 47
VSS
—
Digital Ground. All VSS signals should be tied to the low-impedance
ground plane.
26, 27, 35,
36
VSSA
—
Analog Circuit Ground. All VSSA signals should be tied together to a lowimpedance ground plane.
43
XI
—
44
XO
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant
fundamental mode crystal. Although, when a 24.576 MHz clock source is
used, it can be connected to XI with XO left unconnected. The optimum
values for the external shunt capacitors are dependent on the specifications of the crystal used. It is suggested that two 12 pF shunt capacitors
be used for a crystal with a specified 7 pF loading capacitance. For more
details, see Crystal Selection Considerations in the Application Information section.
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-pair
cable. Board traces from each pair of positive and negative differential
signal pins should be kept matched and as short as possible to the external
load resistors and to the cable connector.
Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias
voltage needed for proper operation of the twisted-pair cable drivers and
receivers and for sending a valid cable connection signal to the remote
nodes.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
Agere Systems Inc.
9
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Application Information
12 pF
2.49 kΩ
R0
37
R1
38
VDD
39
VSS
40
PLLVDD
41
XO
/RESET
SYSCLK LLC
VSS
PLLVSS
42
43
D0
44
2
45
CTL1
46
1
47
CTL0
36
VSSA
35
VSSA
3
34
VDDA
D1
4
33
VDDA
VDD
5
32
TPBIAS0
D2
6
31
TPA0+
30
TPA0–
PIN #1 IDENTIFIER
AGERE FW801A
10
27
VSSA
D7
11
26
VSSA
VSS
12
25
VDDA
SM
SE
VDD
VSS
CPS
/ISO
CABLE
POWER
400 kΩ
PD
C/LKON
LKON
VDD
VSS
10 kΩ
BUS
MANAGER
LPS
LCC PULSE
OR VDD
CNA
PORT 0*
24
D6
23
TPB0–
22
28
21
9
20
D5
19
TPB0+
18
29
17
8
16
D4
15
7
14
D3
13
LLC
48
LREQ LLC
0.1 µF
XI
24.576 MHz
12 pF
5-6767 (F).a R.04
* See Figure 4 for typical port termination network.
Figure 3. Typical External Component Connections
10
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Application Information (continued)
36
VSSA
35
VSSA
34
VDDA
33
VDDA
32
31
30
29
0.33 µF
TPBIAS0
56 Ω
TPA0+
56 Ω
TPA0–
5
6
TPB0+
IEEE 1394-1995 STANDARD
CONNECTOR
28
TPB0–
56 Ω
56 Ω
27
VSSA
220 pF
VSSA
5 kΩ
26
25
VDDA
3
4
1
2
VP
VG
CABLE
POWER
5-7654 (F)
Figure 4. Typical Port Termination Network
1394 Application Support Contact Information
E-mail: [email protected]
Crystal Selection Considerations
The FW801A is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW801A have less than
±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is
recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used.
The total frequency variation must be kept below ±100 ppm from nominal with some allowance for error introduced
by board and device variations. Trade offs between frequency tolerance and stability may be made as long as the
total frequency variation is less than ±100 ppm.
Agere Systems Inc.
11
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Crystal Selection Considerations (continued)
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also
capacitances from the FW801A board traces and capacitances of the other FW801A connected components.
The values for load capacitors (CA and CB) should be calculated using this formula:
CA = CB = (CL – Cstray) × 2
Where:
CL = load capacitance specified by the crystal manufacturer
Cstray = capacitance of the board and the FW801A, typically 2—3 pF
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW801A PLL. The crystal and two load capacitors should be considered as a unit during
layout. They should be placed as close as possible to one another, while minimizing the loop area created by the
combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO signals.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Supply Voltage Range
Symbol
Min
Max
Unit
VDD
3.0
3.6
V
Input Voltage Range*
VI
−0.5
VDD + 0.5
V
Output Voltage Range at Any Output
VO
−0.5
VDD + 0.5
V
Operating Free Air Temperature
TA
0
70
°C
Storage Temperature Range
Tstg
–65
150
°C
* Except for 5 V tolerant I/O (CTL0, CTL1, D0 —D7, and LREQ) where VI max = 5.5 V.
12
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Electrical Characteristics
Table 3. Analog Characteristics
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Supply Voltage
Differential Input Voltage
Source power node
Cable inputs, 100 Mbits/s operation
Cable inputs, 200 Mbits/s operation
Cable inputs, 400 Mbits/s operation
Cable inputs, during arbitration
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
TPB cable inputs,
speed signaling off
TPB cable inputs,
S100 speed signaling on
TPB cable inputs,
S200 speed signaling on
TPB cable inputs,
S400 speed signaling on
TPA, TPB cable inputs,
100 Mbits/s operation
TPA, TPB cable inputs,
200 Mbits/s operation
TPA, TPB cable inputs,
400 Mbits/s operation
Between TPA and TPB cable inputs,
100 Mbits/s operation
Between TPA and TPB cable inputs,
200 Mbits/s operation
Between TPA and TPB cable inputs,
400 Mbits/s operation
—
VDD—SP
VID—100
VID—200
VID—400
VID—ARB
VCM
3.0
142
132
100
168
1.165
3.3
—
—
—
—
—
3.6
260
260
260
265
2.515
V
mV
mV
mV
mV
V
VCM—SP—100
1.165
—
2.515
V
VCM—SP—200
0.935
—
2.515
V
VCM—SP—400
0.532
—
2.515
V
VCM
1.165
—
2.015
V
VCM—NSP—100
1.165
—
2.015
V
VCM—NSP—200
0.935
—
2.015
V
VCM—NSP—400
0.532
—
2.015
V
—
—
—
1.08
ns
—
—
—
0.5
ns
—
—
—
0.315
ns
—
—
—
0.8
ns
—
—
—
0.55
ns
—
—
—
0.5
ns
VTH+
89
—
168
mV
—
VTH−
–168
—
–89
mV
200 Mbits/s
400 Mbits/s
TPBIAS outputs
At rated I/O current
—
VTH—S200
VTH—S400
IO
VO
ICD
45
266
–5
1.665
—
—
—
—
—
—
139
445
2.5
2.015
76
mV
mV
mA
V
µA
Common-mode Voltage
Source Power Mode
Common-mode Voltage
Nonsource Power Mode*
Receive Input Jitter
Receive Input Skew
Positive Arbitration
Comparator Input
Threshold Voltage
Negative Arbitration
Comparator Input
Threshold Voltage
Speed Signal Input
Threshold Voltage
Output Current
TPBIAS Output Voltage
Current Source for
Connect Detect Circuit
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
Agere Systems Inc.
13
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Electrical Characteristics (continued)
Table 4. Driver Characteristics
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
56 Ω load
VOD
172
—
265
mV
Drivers disabled
VOFF
—
—
20
mV
Driver Differential Current,
TPA+, TPA−, TPB+, TPB−
Driver enabled,
speed signaling off*
IDIFF
−1.05
—
1.05
mA
Common-mode Speed Signaling
Current, TPB+, TPB−
200 Mbits/s speed
signaling enabled†
ISP
−2.53
—
−4.84
mA
400 Mbits/s speed
signaling enabled†
ISP
−8.1
—
−12.4
mA
Differential Output Voltage
Off-state Common-mode Voltage
* Limits are defined as the algebraic sum of TPA+ and TPA − driver currents. Limits also apply to TPB+ and TPB − as the algebraic sum of driver
currents.
† Limits are defined as the absolute limit of each of TPB+ and TPB − driver currents.
14
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Electrical Characteristics (continued)
Table 5. Device Characteristics
Parameter
Supply Current:
One Port Active
No Ports Active, LPS = 0
Microlow-Power Sleep Mode
PD = 1
Test Conditions
Symbol
Min
Typ
Max
Unit
IDD
IDD
IDD
IDD
—
—
—
—
54
85
50
50
—
—
—
—
mA
mA
µA
µA
VDD – 0.4
—
—
V
VDD = 3.3 V
High-level Output Voltage
IOH max, VDD = min
VOH
Low-level Output Voltage
IOL min, VDD = max
VOL
—
—
0.4
V
High-level Input Voltage
CMOS inputs
VIH
0.7VDD
—
—
V
Low-level Input Voltage
CMOS inputs
VIL
—
—
0.2VDD
V
Pull-up Current,
/RESET Input
VI = 0 V
II
11
—
32
µA
Powerup Reset Time,
/RESET Input
VI = 0 V
—
2
—
—
ms
—
VIRST
1.1
—
1.4
V
SYSCLK
IOL/IOH
@ TTL
–16
—
16
mA
Control, data
IOL/IOH
@ CMOS
–12
—
12
mA
Rising Input Threshold Voltage
/RESET Input
Output Current
CNA
IOL/IOH
–16
—
16
mA
C/LKON
IOL/IOH
–2
—
2
mA
Input Current,
LREQ, LPS, PD, SE, SM,
PC[0:2] Inputs
VI = VDD or 0 V
II
—
—
°±1
µA
Off-state Output Current,
CTL[0:1], D[0:7], C/LKON I/Os
VO = VDD or 0 V
IOZ
—
—
°±5
µA
Power Status Input Threshold
Voltage, CPS Input
400 kΩ resistor
VTH
7.5
—
8.5
V
Rising Input Threshold Voltage*,
LREQ, CTLn, Dn
—
VIT+
VDD/2 + 0.3
—
VDD/2 + 0.8
V
Falling Input Threshold Voltage*,
LREQ, CTLn, Dn
—
VIT−
VDD/2 – 0.8
—
VDD/2 – 0.3
V
VI = 1/2(VDD)
—
250
—
550
µA
Rising Input Threshold Voltage
LPS
—
VLIH
—
—
0.24VDD + 1
V
Falling Input Threshold Voltage
LPS
—
VLIL
0.24VDD + 0.2
—
—
V
Bus Holding Current,
LREQ, CTLn, Dn
* Device is capable of both differentiated and undifferentiated operation.
Agere Systems Inc.
15
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Timing Characteristics
Table 6. Switching Characteristics
Symbol
Parameter
Measured
Test Conditions
Min
Typ
Max
Unit
—
Jitter, Transmit
TPA, TPB
—
—
—
0.15
ns
—
Transmit Skew
Between
TPA and TPB
—
—
—
±0.1
ns
tr
Rise Time, Transmit (TPA/TPB)
10% to 90%
RI = 56 Ω,
CI = 10 pF
—
—
1.2
ns
tf
Fall Time, Transmit (TPA/TPB)
90% to 10%
RI = 56 Ω,
CI = 10 pF
—
—
1.2
ns
tsu
Setup Time,
Dn, CTLn, LREQ↑↓ to SYSCLK↑
50% to 50%
See Figure 5
6
—
—
ns
th
Hold Time,
Dn, CTLn, LREQ↑↓ from SYSCLK↑
50% to 50%
See Figure 5
0
—
—
ns
td
Delay Time,
SYSCLK↑ to Dn, CTLn↑↓
50% to 50%
See Figure 6
1
—
6
ns
Table 7. Clock Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
External Clock Source Frequency
f
24.5735
24.5760
24.5785
MHz
16
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Timing Waveforms
SYSCLK
th
tsu
Dn, CTLn, LREQ
5-6017.a (F)
Figure 5. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms
SYSCLK
td
Dn, CTLn
5-6018.a (F)
Figure 6. Dn, CTLn Output Delay Relative to SYSCLK Waveforms
Agere Systems Inc.
17
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Internal Register Configuration
The PHY register map is shown below in Table 8.
Table 8. PHY Register Map for the Cable Environment
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 4
Bit 5
Physical_ID
00002
00012
Bit 3
RHB
IBR
Bit 6
Bit 7
R
PS
Gap_count
00102
Extended (7)
00112
Max_speed
01002
LCtrl
Contender
01012
Resume_int
ISBR
XXXXX
XXXXX
Total_ports
Delay
Jitter
Loop
Pwr_fail
Pwr_class
Timeout
Port_event Enab_accel Enab_multi
01112
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
Page_select
Port_select
XXXXX
10002
Register 0 Page_select
11112
Register 7 Page_select
01102
REQUIRED
XXXXX
RESERVED
The meaning of the register fields within the PHY register map are defined by Table 9 below. Power reset values
not specified are resolved by the operation of the PHY state machines subsequent to a power reset.
Table 9. PHY Register Fields for the Cable Environment
Field
Size Type
Power Reset
Value
Description
The address of this node determined during self-identification. A
value of 63 indicates a malconfigured bus; the link will not transmit
any packets.
Physical_ID
6
r
000000
R
1
r
0
When set to one, indicates that this node is the root.
PS
1
r
—
Cable power active.
RHB
1
rw
0
Root hold-off bit. When set to one, the force_root variable is TRUE,
which instructs the PHY to attempt to become the root during the
next tree identify process.
IBR
1
rw
0
Initiate bus reset. When set to one, instructs the PHY to set ibr
TRUE and reset_time to RESET_TIME. These values in turn
cause the PHY to initiate a bus reset without arbitration; the reset
signal is asserted for 166 µs. This bit is self-clearing.
Gap_count
6
rw
3F16
Used to configure the arbitration timer setting in order to optimize
gap times according to the topology of the bus. See Section 4.3.6
of IEEE Standard 1394-1995 for the encoding of this field.
Extended
3
r
7
18
This field has a constant value of seven, which indicates the
extended PHY register map.
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Internal Register Configuration (continued)
Table 9. PHY Register Fields for the Cable Environment (continued)
Field
Size Type Power Reset Value
Description
Total_ports
4
r
1
Max_speed
3
r
0102
Indicates the speed(s) this PHY supports:
0002 = 98.304 Mbits/s
0012 = 98.304 and 196.608 Mbits/s
0102 = 98.304, 196.608, and 393.216 Mbits/s
0112 = 98.304, 196.608, 393.216, and 786.43 Mbits/s
1002 = 98.304, 196.608, 393.216, 786.432, and
1,572.864 Mbits/s
1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and
3,145.728 Mbits/s
All other values are reserved for future definition.
Delay
4
r
0000
Worst-case repeater delay, expressed as 144 + (delay * 20) ns.
LCtrl
1
rw
1
Link Active. Cleared or set by software to control the value of
the L bit transmitted in the node’s self-ID packet 0, which will be
the logical AND of this bit and LPS active.
Contender
1
rw
See description.
Cleared or set by software to control the value of the C bit transmitted in the self-ID packet. Powerup reset value is set by
C/LKON pin.
Jitter
3
r
000
The difference between the fastest and slowest repeater data
delay, expressed as (jitter + 1) * 20 ns.
Pwr_class
3
rw
000
Power-Class. Controls the value of the pwr field transmitted in
the self-ID packet. See Section 4.3.4.1 of IEEE Standard 13941995 for the encoding of this field.
Resume_int
1
rw
0
Resume Interrupt Enable. When set to one, the PHY will set
Port_event to one if resume operations commence for any port.
ISBR
1
rw
0
Initiate Short (Arbitrated) Bus Reset. A write of one to this bit
instructs the PHY to set ISBR true and reset_time to
SHORT_RESET_TIME. These values in turn cause the PHY to
arbitrate and issue a short bus reset. This bit is self-clearing.
Loop
1
rw
0
Loop Detect. A write of one to this bit clears it to zero.
Pwr_fail
1
rw
1
Cable Power Failure Detect. Set to one when the PS bit
changes from one to zero. A write of one to this bit clears it to
zero.
Timeout
1
rw
0
Arbitration State Machine Timeout. A write of one to this bit
clears it to zero (see MAX_ARB_STATE_TIME).
Port_event
1
rw
0
Port Event Detect. The PHY sets this bit to one if any of connected, bias, disabled, or fault change for a port whose
Int_enable bit is one. The PHY also sets this bit to one if
resume operations commence for any port and Resume_int is
one. A write of one to this bit clears it to zero.
Agere Systems Inc.
The number of ports implemented by this PHY. This count
reflects the number.
19
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Internal Register Configuration (continued)
Table 9. PHY Register Fields for the Cable Environment (continued)
Field
Size Type
Power Reset
Value
Description
Enab_accel
1
rw
0
Enable Arbitration Acceleration. When set to one, the PHY will
use the enhancements specified in clause 8.11 of 1394a-2000
specification. PHY behavior is unspecified if the value of
Enab_accel is changed while a bus request is pending.
Enab_multi
1
rw
0
Enable multispeed packet concatenation. When set to one, the link
will signal the speed of all packets to the PHY.
Page_select
3
rw
000
Selects which of eight possible PHY register pages are accessible
through the window at PHY register addresses 10002 through
11112, inclusive.
Port_select
4
rw
000
If the page selected by Page_select presents per-port information,
this field selects which port’s registers are accessible through the
window at PHY register addresses 10002 through 11112, inclusive.
Ports are numbered monotonically starting at zero, p0.
The port status page is used to access configuration and status information for each of the PHY’s ports. The port is
selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address
01112. The format of the port status page is illustrated by Table 10 below; reserved fields are shown shaded. The
meanings of the register fields with the port status page are defined by Table 11.
Table 10. PHY Register Page 0: Port Status Page
Address
Contents
Bit 0
Bit 1
10002
AStat
10012
Negotiated_speed
10102
10112
11002
11012
11102
11112
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
REQUIRED
20
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Child
Connected
Bias
Disabled
Int_enable
Fault
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
RESERVED
BStat
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
XXXXX
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Internal Register Configuration (continued)
The meaning of the register fields with the port status page are defined by Table 11 below.
Table 11. PHY Register Port Status Page Fields
Field
Size Type
Power Reset
Value
Description
AStat
2
r
—
TPA line state for the port:
002 = invalid
012 = 1
102 = 0
112 = Z
BStat
2
r
—
TPB line state for the port (same encoding as AStat).
Child
1
r
0
If equal to one, the port is a child; otherwise, a parent. The
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1: Child Handshake during the tree identify process (see Section 4.4.2.2 in
IEEE Standard 1394-1995).
Connected
1
r
0
If equal to one, the port is connected.
Bias
1
r
0
If equal to one, incoming TPBIAS is detected.
Disabled
1
rw
0
If equal to one, the port is disabled.
Negotiated_speed
3
r
000
Indicates the maximum speed negotiated between this PHY
port and its immediately connected port; the encoding is the
same as for they PHY register Max_speed field.
Int_enable
1
rw
0
Enable port event interrupts. When set to one, the PHY will
set Port_event to one if any of connected, bias, disabled, or
fault (for this port) change state.
Fault
1
rw
0
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
Agere Systems Inc.
21
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 1
June 2001
Internal Register Configuration (continued)
The vendor identification page is used to identify the PHY’s vendor and compliance level. The page is selected by
writing one to Page_select in the PHY register at address 01112. The format of the vendor identification page is
shown in Table 12; reserved fields are shown shaded.
Table 12. PHY Register Page 1: Vendor Identification Page
Address
Contents
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
10002
Compliance_level
10012
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
10102
10112
Vendor_ID
11002
11012
11102
Product_ID
11112
REQUIRED
XXXXX
RESERVED
The meaning of the register fields within the vendor identification page are defined by Table 13.
Table 13. PHY Register Vendor Identification Page Fields
Field
Size Type
Description
Compliance_level
8
r
Standard to which the PHY implementation complies:
0 = not specified
1 = IEEE 1394a-2000
Agere’s FW801A compliance level is 1.
All other values reserved for future standardization.
Vendor_ID
24
r
The company ID or organizationally unique identifier (OUI) of the manufacturer
of the PHY. Agere’s vendor ID is 00601D16. This number is obtained from the
IEEE registration authority committee (RAC). The most significant byte of
Vendor_ID appears at PHY register location 10102 and the least significant at
11002.
Product_ID
24
r
The meaning of this number is determined by the company or organization that
has been granted Vendor_ID. Agere’s FW801A product ID is 08020116. The
most significant byte of Product_ID appears at PHY register location 11012 and
the least significant at 11112.
The vendor-dependent page provides access to information used in manufacturing test of the FW801A.
22
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY IEEE 1394A-2000
One-Cable Transceiver/Arbiter Device
Outline Diagrams
48-Pin TQFP
Dimensions are in millimeters.
9.00 ± 0.20
1.00 REF
7.00 ± 0.20
PIN #1
IDENTIFIER ZONE
37
48
0.25
GAGE PLANE
1
SEATING PLANE
36
0.45/0.75
7.00
± 0.20
DETAIL A
9.00
± 0.20
25
12
13
0.106/0.200
24
DETAIL A
DETAIL B
0.19/0.27
0.08
1.40 ± 0.05
1.60 MAX
0.50 TYP
0.05/0.15
M
DETAIL B
SEATING PLANE
0.08
5-2363 (F)r.8
Ordering Information
Device Code
Package
Comcode
FW801A-DB
48-Pin TQFP
108698374
Agere Systems Inc.
23
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
[email protected]
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Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:
Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
June 2001
DS01-021CMPR-1