ICST ICS950220 Programmable timing control hubâ ¢ for p4â ¢ Datasheet

ICS950220
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock for Intel® 845 chipset.
Pin Configuration
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
VDDREF
X1
X2
GND
1
*FS0/PCICLK7
1
**FS1/PCICLK8
VDDPCI
GND
1
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_1
3V66_2
3V66_3
#RESET
VDDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS950220
Output Features:
•
3 - Pairs of differential CPU clocks @ 3.3V
•
3 - 3V66 @ 3.3V
•
9 - PCI @ 3.3V
•
2 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V, 48MHz, 24Mhz or 66MHz
•
1 - REF @ 3.3V, 14.318MHz
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
REF/FS2**
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTISEL0*
I REF
GND
48MHz_USB/FS3**
48MHz_DOT/SEL_24_48*
AVDD48
GND
3V66_0/24_48MHZ#/FS4**
VDD3V66
GND
SCLK
SDATA
Vtt_PWRGD/PD#*
GND
48-Pin 300-mil SSOP
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
Frequency Table
PLL2
48MHz_USB
/2
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
3
3V66 (3:1)
3V66_0/24_48MHZ#
PLL1
Spread
Spectrum
REF
CPU
DIVDER
SEL24_48
WDEN
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PD#
0467F—07/28/05
3
3
Control
Logic
PCI
DIVDER
7
CPUCLKT (2:0)
CPUCLKC (2:0)
Reg.
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
I REF
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
100.00
133.33
66.67
200.00
66.67
66.67
66.67
66.67
33.33
33.33
33.34
33.33
For additional frequency selections please refer to Byte 0.
Power Groups
PCICLK (6:0)
Reset#
Config.
FS4 FS3 FS2 FS1 FS0
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
ICS950220
Integrated
Circuit
Systems, Inc.
General Description
The ICS950220 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It
provides all necessary clock signals for such a system.
The ICS950220 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 7, 13, 18,
30, 41, 45
PIN NAME
VDD
TYPE
PWR
DESCRIPTION
3.3V power supply.
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2.
2
X1
IN
3
X2
OUT
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF).
GND
PWR
Ground pins for 3.3V supply.
3V66 (3:1)
OUT
3.3V Fixed 66MHz clock outputs for HUB.
PCICLK7
OUT
4, 8, 14, 19, 25, 29,
32, 36, 42
22, 21, 20
5
FS0
PCICLK8
IN
OUT
3.3V PCI clock output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock output.
6
FS1
9
WDEN
PCICLK0
17, 16, 15, 12, 11, 10 PCICLK (6:1)
IN
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
IN
Hardware enable of watch dog circuit. Enabled when latched high.
OUT
3.3V PCI clock output.
OUT
3.3V PCI clock outputs.
23
RESET#
OUT
Real time system reset signal for frequency value or watchdog timmer timeout.
This signal is active low.
24
VDDA
PWR
Analog power 3.3V.
Vtt_PWRGD
IN
PD#
IN
SCLK
SDATA
IN
I/O
26
28
27
31
33
34
3V66_0/24_48MHZ#
OUT
FS4
AVDD48
48MHz_DOT
IN
PWR
OUT
SEL24_48
IN
35
FS3
48MHz_USB
IN
OUT
37
I REF
OUT
38
MULTSEL0
IN
39, 43, 46
CPUCLKC (2:0)
OUT
40, 44, 47
CPUCLKT (2:0)
OUT
FS2
REF
IN
OUT
48
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active high).
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
Clock pin for I2C circuitr y 5V tolerant.
Data pin for I2C circuitr y 5V tolerant.
3.3V output selectable through I2C to be 66MHz from internal VCO or
48MHz/24MHz.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
This selects the frequency for the SEL24_48 output.
H i g h = 2 4 M H z , L ow = 4 8 M H z .
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementor y" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V, 14.318MHz reference clock output.
0467F—07/28/05
2
ICS950220
Integrated
Circuit
Systems, Inc.
Maximum Allowed Current
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
Output
Current
Voh @ Z
0
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
1.0V @ 50
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
0467F—07/28/05
3
ICS950220
Integrated
Circuit
Systems, Inc.
General SMBus serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0467F—07/28/05
4
Not acknowledge
stoP bit
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Bit
Bit2 Bit7 Bit6 Bit5 Bit4 CPUCLK
MHz
FS4 FS3 FS2 FS1 FS0
Bit
(2,7:4)
B it 3
Bit 1
Bit 0
PWD
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010101-
3V66
MHz
PCICLK
MHz
Spread %
0
0
0
0
100.90
67.27
33.63
+/-0.35% center spread
0
0
0
1
100.00
66.67
33.33
0 to -0.6% down spread
0
0
1
0
103.00
68.67
34.33
+/-0.35% center spread
+/-0.35% center spread
0
0
1
1
105.00
70.00
35.00
0
1
0
0
107.00
71.33
35.67
+/-0.35% center spread
0
1
0
1
109.00
72.67
36.33
+/-0.35% center spread
+/-0.35% center spread
0
1
1
0
111.00
74.00
37.00
0
1
1
1
114.00
76.00
38.00
+/-0.35% center spread
1
0
0
0
117.00
78.00
39.00
+/-0.35% center spread
+/-0.35% center spread
1
0
0
1
120.00
80.00
40.00
1
0
1
0
127.00
84.67
42.33
+/-0.35% center spread
1
0
1
1
130.00
86.67
43.33
+/-0.35% center spread
+/-0.35% center spread
1
1
0
0
133.33
88.89
44.44
1
1
0
1
170.00
56.67
28.33
+/-0.35% center spread
1
1
1
0
180.00
60.00
30.00
+/-0.35% center spread
+/-0.35% center spread
1
1
1
1
190.00
63.33
31.67
0
0
0
0
133.90
66.95
33.48
+/-0.35% center spread
0
0
0
1
133.33
66.67
33.33
0 to -0.6% down spread
+/-0.35% center spread
0
0
1
0
120.00
60.00
30.00
0
0
1
1
125.00
62.50
31.25
+/-0.35% center spread
0
1
0
0
134.90
67.45
33.73
+/-0.35% center spread
+/-0.35% center spread
0
1
0
1
137.00
68.50
34.25
0
1
1
0
139.00
69.50
34.75
+/-0.35% center spread
0
1
1
1
141.00
70.50
35.25
+/-0.35% center spread
+/-0.35% center spread
1
0
0
0
143.00
71.50
35.75
1
0
0
1
145.00
72.50
36.25
+/-0.35% center spread
1
0
1
0
150.00
75.00
37.5
+/-0.35% center spread
1
0
1
1
155.00
77.50
38.75
+/-0.35% center spread
1
1
0
0
160.00
80.00
40.00
+/-0.35% center spread
1
1
0
1
170.00
85.00
42.50
+/-0.35% center spread
1
1
1
0
66.67
66.67
33.34
0 to -0.6% down spread
200.00
66.67
33.33
0 to -0.6% down spread
1
1
1
1
Frequency is selected by hardware select, latched inputs
Frequency is selected by Bit 2,7:4
Normal
Spread spectrum enable
Watch dog safe frequency will be selected by latch inputs
Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0467F—07/28/05
5
Note 1
0
1
0
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
40, 39
44, 43
47, 46
-
PWD
1
1
1
X
X
X
X
X
Description
CPUT/C2
CPUT/C1
CPUT/C0
FS4 Read
FS3 Read
FS2 Read
FS1 Read
FS0 Read
b a ck
b a ck
b a ck
b a ck
b a ck
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
17
16
15
12
11
10
9
PWD
X
1
1
1
1
1
1
1
Description
MULTSEL (Read back)
PCICLK_6
PCICLK_5
PCICLK_4
PCICLK_3
PCICLK_2
PCICLK_1
PCICLK_0
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
34
35
31
6
5
PWD
1
1
1
X
0
X
1
1
Description
48MHZ_DOT
48MHz_USB
Reset gear shift detect 1 = Enable, 0 = Disable
Reserved
3V66_0/24_48MHZ#, (default) 1 = 66.66MHz, 0 = 24_48MHZ#
Reserved
PCICLK8
PCICLK7
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin#
PWD
Bit 7
-
1
Description
Async. 3V66 control bit
0 : 3V66 / PCI = 64/32 MHz asynchronous with CPU
1 : 3V66 / PCI = 66.6/33.3 MHz synchronous with CPU
Reserved
Reserved
3V66_0/24_48MHZ#
Reserved
3V66_3
3V66_2
3V66_1
Bit 6
X
Bit 5
X
Bit 4
31
1
Bit 3
X
Bit 2
22
1
Bit 1
21
1
Bit 0
20
1
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at
high, CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0467F—07/28/05
6
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
X
X
X
X
X
X
X
X
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
0
0
1
Device ID values will be based on individual device
0
"22H" in this case.
0
0
1
0
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
0467F—07/28/05
7
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
0
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
1
8 • 290ms = 2.3 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bi t 7
Program
Enable
0
Bi t 6
WD Enable
1
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
WD Alarm
S F4
S F3
S F2
S F1
S F0
1
0
0
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
0467F—07/28/05
8
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
X
VCO frequency, spreading profile, spreading amount and spread
X
frequency. It is recommended to use ICS software for spread
X
programming. Default power on is latched FS divider.
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
B it 1
Bit 0
Name
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
0
1
0
0
0
1
0
0
Description
CPU 2 clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU (1:0) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Div 3
Div 2
Div 1
Div 0
Div 3
Div 2
Div 1
Div 0
PWD
0
1
0
1
0
1
0
1
Description
3V66_0 clock divider ratio can be configured via these
4 bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
3V66 (3:1) clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
0467F—07/28/05
9
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
3V66_INV
3V66_INV
CPU_INV
CPU_INV
PWD
0
0
0
0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
1
0
0
1
Description
3V66_0 Phase Inversion bit
3V66 (3:1) Phase Inversion bit
CPU 2 Phase Inversion bit
CPU (1:0) Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Div (3:2)
Table 2
00
01
10
11
00
/2
/4
/8
/16
Div (1:0)
Div (3:2)
00
01
10
11
00
/4
/8
/16
/32
Div (1:0)
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/9
/18
/36
/72
Byte 18: Group Skew Control Register
Bit
Name
PWD
Bi t 7
CPU_Skew 1
0
Bi t 6
Bi t 5
Bi t 4
Bi t 3
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
0
0
0
0
Bi t 2
Bi t 1
Bi t 0
CPU_Skew 0
Reserved
Reserved
0
0
0
Description
These 2 bits delay the CPUCLKC/T2 with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T2
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bi t 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
3V66_Skew 1
3V66_Skew 0
Reserved
Reserved
3V66_Skew 1
3V66_Skew 0
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Description
These 2 bits delay the 3V66 (3:1) with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the 3V66_0 with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
0467F—07/28/05
10
ICS950220
Integrated
Circuit
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
PWD
1
0
0
0
1
0
0
0
Description
These 4 bits can change the CPU to PCI (6:0) skew from -0.3ns
1.2ns. Default at power up is 0.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
These 4 bits can change the CPU to PCI (8:7) skew from -0.6ns
1.2ns. Default at power up is 0.4ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
Byte 21: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
Reserved
PCIF Slew 1
PCIF Slew 0
3V66 (3:1)_Slew 1
3V66 (3:1)_Slew 1
3V66_0_Slew 1
3V66_0_Slew 0
PWD
1
0
1
0
1
0
1
0
Description
Reserved
Reser ved
PCIF(1:0) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66 (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
3V66_0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF Slew 1
REF Slew 0
PCI (6:4) Slew 1
PCI (6:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI0 Slew 0
PWD
1
0
1
0
1
0
1
0
Description
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
Reserved
VCH Slew 1
VCH Slew 0
48USB Slew 1
48USB Slew 0
48DOT Slew 1
48DOT Slew 0
PWD
X
X
1
0
1
0
1
0
Description
Reserved
VCH clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
48USB clock slew rate control bits.
01 = strong: 11 = normal; 10 = weakk
48DOT clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
0467F—07/28/05
11
ICS950220
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
CONDITIONS
VIH
VIL
VIN = VDD
IIH
VIN = 0 V; Inputs with no pull-up
IIL1
resistors
IIL2
MIN
2
VSS - 0.3
-5
-200
229
IDD3.3OP
CL = Full load
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
Ttrans
IREF=2.32 mA
VDD = 3.3 V
Logic Inputs
1
Output pin capacitance
Input Capacitance
X1 & X2 pins
1
To 1st crossing of target frequency
Transition time
From 1st crossing to 1% target
1
Ts
Settling time
frequency
From VDD = 3.3 V to 1% target
1
TSTAB
Clk Stabilization
frequency
tPZH,tPZL Output enable delay (all outputs)
1
Delay
tPHZ,tPLZ Output disable delay (all outputs)
S3V66-PCI
3V66 to PCI
3V66 (5:0) leads 33MHz PCI
1
Guaranteed by design, not 100% tested in production.
0467F—07/28/05
12
MAX
VDD + 0.3
0.8
5
-5
VIN = 0 V; Inputs with pull-up resistors
Operating Supply Current
TYP
mA
221
360
mA
21
14.318
25
7
5
6
45
3
mA
MHz
nH
pF
pF
pF
ms
3
ms
3
ms
10
10
3.5
ns
ns
ns
27
1
1
1.5
UNITS
V
V
mA
2.12
ICS950220
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; V DD = 3.3 V +/-5%; CL =2pF
1
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo1
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Duty Cycle
dt3
Skew
tsk3
Jitter, Cycle to cycle
tjcyc-cyc
Measurement on single ended
signal using absolute value.
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, V OH = 0.525V
V OH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
TYP
770
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
5
150
756
-7
350
1150
-300
250
550
mV
1
1
1
12
140
mV
1
300
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
-300
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
45
1
mV
332
344
30
30
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
49
55
%
1
8
100
ps
1
60
150
ps
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
0467F—07/28/05
13
ICS950220
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
Output High Current
IOH
Output Low Current
IOL
RDSP1
1
VOH
1
VOL
1
1
1
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH@MIN = 1.0 V,
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1
Rise Time
tr1
1
Fall Time
tf1
1
Duty Cycle
dt1
1
Skew
tsk1
1
Jitter,cycle to cyc
tjcyc-cyc
1
Guaranteed by design, not 100% tested in production.
MIN
TYP
33.33
0.55
UNITS
MHz
Ω
V
V
-33
-33
mA
30
38
mA
12
2.4
MAX
55
0.5
0.5
45
188
1.79
52
280
200
2
2
55
500
500
ns
ns
%
ps
ps
MIN
TYP
MAX
12
2.4
33
55
0.55
UNITS
MHz
Ω
V
V
-33
-33
mA
30
38
mA
1.55
1.32
51.7
2
2
55
ns
ns
%
16
250
ps
200
250
ps
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
Output High Current
IOH
Output Low Current
IOL
RDSP1
1
VOH
1
VOL
1
1
1
1
Rise Time
Fall Time
Duty Cycle
tr1
1
tf1
1
dt1
Skew
tsk1
1
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
V OH@MIN = 1.0 V,
V OH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
1
tjcyc-cyc
VT = 1.5 V
Jitter
Guaranteed by design, not 100% tested in production.
Note: 3V66@66Mhz- main PLL
1
0467F—07/28/05
14
0.5
0.5
45
ICS950220
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
CONDITIONS
FO1
VO = VDD*(0.5)
1
VO = VDD*(0.5)
RDSP1
1
IOH = -1 mA
VOH
1
IOL = 1 mA
VOL
12
2.4
MAX
0.55
UNITS
MHz
Ω
V
V
-23
mA
55
3.1
0.19
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
-29
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
29
0.5
0.5
1
1
45
0.77
0.84
1.12
1.42
49.9
27
1
1
2
2
55
mA
ns
ns
ns
ns
%
VT = 1.5 V
45
54.9
55
%
131
350
ps
TYP
14.31
MAX
0.4
UNITS
MHz
Ω
V
V
-23
mA
27
2
2
mA
ns
ns
IOH
Output Low Current
48DOT Rise Time
48DOT Fall Time
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48DOTDuty Cycle
IOL
1
tr1
1
tf1
1
tr1
1
tf1
1
dt1
1
dt1
1
tjcyc-cyc
1
TYP
48
1
Output High Current
48 USB Duty Cycle
MIN
VT = 1.5 V
Jitter
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
SYMBOL
FO1
Output High Current
IOH
Output Low Current
Rise Time
Fall Time
IOL
1
tr1
1
tf1
1
dt1
Duty Cycle
RDSP11
1
VOH
1
VOL
CONDITIONS
MIN
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
2.4
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
-29
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
29
1
1
1.7
1.76
VT = 1.5 V
45
53.5
55
%
305
1000
ps
VT = 1.5 V
Jitter
tjcyc-cyc1
1
Guaranteed by design, not 100% tested in production.
0467F—07/28/05
15
60
ICS950220
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0467F—07/28/05
16
ICS950220
Integrated
Circuit
Systems, Inc.
3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges
GROUP
3V66
PCI
SYMBOL
CONDITIONS
3V66
3V66 (5:0) pin to pin skew
PCI
3V66 to PCI
S3V66-PCI
MIN
0
PCI_F (2:0) and PCI (6:0) pin to pin skew
3V66 (5:0) leads 33MHz PCI
TYP
MAX UNITS
500
ps
0
500
ps
1.5
3.5
ns
1
Guaranteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK_F
PCICLK
PCICLK
USB/DOT
48MHz
1
Normal
Normal
66MHz
66MHz_IN
66MHz_IN
66MHz_IN
48MHz
0
iref * Mult
Float
Low
Low
Low
Low
Low
0467F—07/28/05
17
ICS950220
Integrated
Circuit
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
0467F—07/28/05
18
ICS950220
Integrated
Circuit
Systems, Inc.
c
N
SYMBOL
L
E1
INDEX
AREA
E
1 2
a
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
A1
-Ce
SEATING
PLANE
b
.10 (.004) C
N
48
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950220yFLFT
Example:
ICS XXXX y F LF - T
Designation for tape and reel packaging
RoHs Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0467F—07/28/05
19
MAX
.630
ICS950220
Integrated
Circuit
Systems, Inc.
Revision History
Rev.
F
Issue Date Description
7/28/2005 Added LF Ordering Information.
Page #
19
0467F—07/28/05
20