LINER LTC3412 2.5a, 4mhz, monolithic synchronous step-down regulator Datasheet

LTC3412
2.5A, 4MHz, Monolithic
Synchronous Step-Down Regulator
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FEATURES
DESCRIPTIO
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The LTC®3412 is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.625V to 5.5V and provides an
adjustable regulated output voltage from 0.8V to 5V while
delivering up to 2.5A of output current. The internal
synchronous power switch with 85mΩ on-resistance
increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an
external resistor or can be sychronized to an external
clock. 100% duty cycle provides low dropout operation
extending battery life in portable systems. OPTI-LOOP®
compensation allows the transient response to be optimized over a wide range of loads and output capacitors.
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High Efficiency: Up to 95%
2.5A Output Current
Low Quiescent Current: 62μA
Low RDS(ON) Internal Switches: 85mΩ
Programmable Frequency: 300kHz to 4MHz
No Schottky Diode Required
±2% Output Voltage Accuracy
0.8V Reference Allows Low Output Voltage
Selectable Forced Continuous/Burst Mode Operation
with Adjustable Burst Clamp
Synchronizable Switching Frequency
Low Dropout Operation: 100% Duty Cycle
Power Good Output Voltage Monitor
Overtemperature Protection
Available in 16-Lead Thermally Enhanced TSSOP
and QFN Packages
The LTC3412 can be configured for either Burst Mode®
operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
requirements of the application. To further maximize
battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle).
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APPLICATIO S
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Portable Instruments
Battery-Powered Equipment
Notebook Computers
Distributed Power Systems
Cellular Telephones
Digital Cameras
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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TYPICAL APPLICATIO
Efficiency vs Load Current
VIN
2.7V TO 5.5V
100
22μF
PVIN
PGOOD
309k
4.7M
1μH
SW
LTC3412
PGND
RUN/SS
470pF
SGND
15k
1000pF
100μF
100pF
ITH
SYNC/MODE VFB
110k
VOUT
2.5V
2.5A
80
Burst Mode OPERATION
EFFICIENCY (%)
SVIN
RT
60
FORCED CONTINUOUS
40
20
392k
3412 F01
75k
Figure 1. 2.5V, 2.5A Step-Down Regulator
0
0.001
VIN = 3.3V
VOUT = 2.5V
0.01
0.1
1
LOAD CURRENT (A)
10
3412 G01
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LTC3412
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ABSOLUTE
AXI U RATI GS (Note 1)
Input Supply Voltage ...................................– 0.3V to 6V
ITH, RUN, VFB Voltages ............................... – 0.3V to VIN
SYNC/MODE Voltages ................................ – 0.3V to VIN
SW Voltage ................................... – 0.3V to (VIN + 0.3V)
Peak SW Sink and Source Current ......................... 6.5A
Operating Temperature
Range (Note 2) ....................................... – 40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
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PACKAGE/ORDER I FOR ATIO
VFB
4
RT
5
SYNC/MODE
6
RUN/SS
7
10 SW
SGND
8
9
17
16 15 14 13
12 PGOOD
RUN/SS 1
13 PGND
SGND 2
12 PGND
11 SW
11 SVIN
17
PVIN 3
10 PVIN
SW 4
PVIN
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 37.6°C/W, θJC = 10°C/W
ORDER PART NUMBER
LTC3412EFE
LTC3412IFE
ITH
14 SW
VFB
3
9
5
6
7
8
SW
15 SW
ITH
PGND
16 PVIN
2
SW
1
PGND
SVIN
PGOOD
RT
SYNC/MODE
TOP VIEW
TOP VIEW
SW
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
EXPOSED PAD (PIN 17) IS SGND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 34°C/W, θJC = 1°C/W
FE PART MARKING
3412EFE
3412IFE
ORDER PART NUMBER
LTC3412EUF
UF PART MARKING
3412
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
SVIN
VFB
IFB
ΔVFB
VLOADREG
PARAMETER
Signal Input Voltage Range
Regulated Feedback Voltage
Voltage Feedback Leakage Current
Reference Voltage Line Regulation
Output Voltage Load Regulation
ΔVPGOOD
RPGOOD
IQ
Power Good Range
Power Good Pull-Down Resistance
Input DC Bias Current
Active Current
Sleep
Shutdown
CONDITIONS
(Note 3)
●
VIN = 2.7V to 5.5V (Note 3)
Measured in Servo Loop, VITH = 0.36V
Measured in Servo Loop, VITH = 0.84V
●
(Note 4)
VFB = 0.78V, VITH = 1V
VFB = 1V, VITH = 0V
VRUN = 0V, VMODE = 0V
●
●
MIN
2.625
0.784
TYP
0.800
0.1
0.04
0.02
– 0.02
±7.5
120
MAX
5.5
0.816
0.4
0.2
0.2
– 0.2
±9
200
250
62
0.02
330
80
1
UNITS
V
V
μA
%/V
%
%
%
Ω
μA
μA
μA
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LTC3412
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
fOSC
fSYNC
RPFET
RNFET
ILIMIT
VUVLO
ILSW
VRUN
IRUN
PARAMETER
Switching Frequency
Switching Frequency Range
SYNC Capture Range
RDS(ON) of P-Channel FET
RDS(ON) of N-Channel FET
Peak Current Limit
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
RUN/SS Leakage Current
CONDITIONS
ROSC = 309kΩ
(Note 6)
(Note 6)
ISW = 1A (Note 7)
ISW = –1A (Note 7)
MIN
0.88
0.3
0.3
TYP
0.95
4
2.375
VRUN = 0V, VIN = 5.5V
0.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3412E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3412I is guaranteed to meet
specified performance over the – 40°C to 85°C temperature range.
85
65
5.4
2.500
0.1
0.65
MAX
1.1
4
4
110
90
2.625
1
0.8
1
UNITS
MHz
MHz
MHz
mΩ
mΩ
A
V
μA
V
μA
Note 3: The LTC3412 is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation as follows: LTC3412: TJ = TA + PD (37.6°C/W).
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test correlation
in the UF package and by production test in the FE package.
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
100
80
90
90
60
FORCED CONTINUOUS
40
VIN = 3.3V
80
VIN = 5V
70
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
100
80
Burst Mode OPERATION
Efficiency vs Load Current
100
60
50
40
30
20
0
0.001
20
VIN = 3.3V
VOUT = 2.5V
0.01
0.1
1
LOAD CURRENT (A)
10
3412 G01
10
70
VIN = 3.3V
VIN = 5V
60
50
40
30
20
VOUT = 2.5V
1MHz
Burst Mode OPERATION
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
10
10
3412 G02
0
0.001
VOUT = 2.5V
1MHz
FORCED CONTINUOUS
0.01
0.1
1
LOAD CURRENT (A)
10
3412 G03
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LTC3412
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Load Regulation
Efficiency vs Frequency
98
0.02
97
96
LOAD = 2.5A
90
VOUT = 2.5V
1MHz
Burst Mode OPERATION
86
2.55
3.05
3.55 4.05 4.55
INPUT VOLTAGE (V)
–0.04
95
1μH
0.47μH
94
2.2μH
93
92
–0.06
–0.08
–0.10
–0.12
VIN = 3.3V
VOUT = 2.5V
LOAD = 1A
Burst Mode OPERATION
91
300
5.05
%ΔVOUT/VOUT
92
88
–0.02
LOAD = 1A
EFFICIENCY (%)
EFFICIENCY (%)
96
94
VIN = 3.3V
VOUT = 2.5V
0.00
LOAD = 100mA
–0.14
–0.16
–0.18
800 1300 1800 2300 2800 3300 3800
FREQUENCY (kHz)
3412 G04
IL
1A/DIV
Reference Voltage
vs Temperature
0.7960
120
VIN = 3.3V
100
0.7950
ON-RESISTANCE (mΩ)
REFERENCE VOLTAGE (V)
VOUT
1V/DIV
3412 G09
Switch On-Resistance
vs Input Voltage
0.7955
VRUN
1V/DIV
2.5
VOUT
100mV/DIV
VOUT
100mV/DIV
20μs/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD STEP = 50mA TO 2.5A
3412 G08
VIN = 3.3V, VOUT = 2.5V
LOAD STEP = NO LOAD TO 2.5A
IL
1A/DIV
2
Load Step Transient Burst Mode
Operation
IL
1A/DIV
VOUT
20mV/DIV
IL
200mA/DIV
20μs/DIV
3412 G07
0.7945
0.7940
0.7935
0.7930
0.7920
–45 –25 –5
PFET ON-RESISTANCE
80
60
NFET ON-RESISTANCE
40
20
0.7925
3412 G10
1
1.5
LOAD CURRENT (A)
3412 G06
Load Step Transient Forced
Continuous
Start-Up, Burst Mode Operation
1ms/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD = 1Ω
0.5
3412 G05
Burst Mode Operation
4μs/DIV
VIN = 3.3V, VOUT = 2.5V
LOAD = 50mA
0
0
15 35 55 75 95 115 120
TEMPERATURE (°C)
3412 G11
2.5
3
3.5
4
INPUT VOLTAGE (V)
4.5
5
3412 G12
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LTC3412
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TYPICAL PERFOR A CE CHARACTERISTICS
Switch On-Resistance
vs Temperature
VIN = 3.3V
ON-RESISTANCE (mΩ)
2.0
PFET ON-RESISTANCE
90
80
70
60
NFET ON-RESISTANCE
50
3500
1.5
1.0
SYNCHRONOUS SWITCH
30
3000
2500
2000
1500
1000
0.5
40
500
MAIN SWITCH
20
–40 –20
0
0
20 40 60 80
TEMPERATURE (°C)
2.5
100 120
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
0
5.5
50 150 250 350 450 550 650 750 850 950
ROSC (kΩ)
3412 G14
3412 G13
3412 G15
Switching Frequency
vs Temperature
Frequency vs Input Voltage
DC Supply Current
vs Input Voltage
1010
R = 309k
350
VIN = 3.3V
1008
1040
300
1030
1020
1010
DC SUPPLY CURRENT (μA)
1006
FREQUENCY (kHz)
FREQUENCY (kHz)
VIN = 3.3V
4000
100
1050
Frequency vs ROSC
4500
FREQUENCY (kHz)
110
Switch Leakage vs Input Voltage
2.5
LEAKAGE CURRENT (nA)
120
1004
1002
1000
998
996
994
1000
ACTIVE
250
200
150
100
992
990
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
SLEEP
990
–40 –20
5.5
50
0
4000
ACTIVE
SUPPLY CURRENT (μA)
250
200
150
100
SLEEP
50
0
–40 –20
20 40 60 80
TEMPERATURE (°C)
100 120
3412 G19
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
Current Limit vs Input Voltage
6.8
VIN = 3.3V
3500
6.6
3000
2500
2000
1500
1000
6.4
6.2
6.0
5.8
5.6
500
0
0
3
3412 G18
CURRENT LIMIT (A)
MINIMUM PEAK INDUCTOR CURRENT (mA)
VIN = 3.3V
2.5
Minimum Peak Inductor Current
vs Burst Clamp Voltage
DC Supply Current vs Temperature
300
100 120
3412 G17
3412 G16
350
20 40 60 80
TEMPERATURE (°C)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
BURST CLAMP VOLTAGE (V)
1
3412 G20
5.4
2.75
3.25
4.75
4.25
3.75
INPUT VOLTAGE (V)
5.25
3412 G21
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LTC3412
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PI FU CTIO S
(FE/UH Package)
SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor. Normally SVIN is equal to
PVIN. SVIN can be greater than PVIN but keep the voltage
difference between SVIN and PVIN less than 0.5V.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output
voltage is not within ±7.5% of regulation point.
ITH (Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.2V corresponding to the zero-sense
voltage (zero current).
VFB (Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the
output.
RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the switching frequency.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Clock Synchronization Input. To select forced continuous,
tie to SVIN. Connecting this pin to a voltage between 0V and
1V selects Burst Mode operation with the burst clamp set
to the pin voltage.
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412. In
shutdown all functions are disabled drawing < 1μA of
supply current. A capacitor to ground from this pin sets the
ramp time to full output current.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal
components, compensation components and the exposed
pad on the bottom side of the IC should connect to this
ground, which in turn connects to PGND at one point.
PVIN (Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple
this pin to PGND with a capacitor.
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
Connection to the Inductor. This pin connects to the drains
of the internal main and synchronous power MOSFET
switches.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of CIN and COUT.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and thermal
performance.
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LTC3412
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FU CTIO AL BLOCK DIAGRA
U
SVIN
SGND
ITH
1
8
3
PVIN
9
SLOPE
COMPENSATION
RECOVERY
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VOLTAGE
REFERENCE
0.8V
16
PMOS CURRENT
COMPARATOR
+
BCLAMP
+
–
–
VFB 4
ERROR
AMPLIFIER
SYNC/MODE
0.74V
+
–
+
–
+
–
P-CH
BURST
COMPARATOR
10
SLOPE
COMPENSATION
OSCILLATOR
11
SW
14
15
+
RUN/SS 7
RUN
0.86V
N-CH
LOGIC
–
+
PGOOD 2
NMOS
CURRENT
COMPARATOR
–
–
+
REVERSE
CURRENT
COMPARATOR
5
6
RT
SYNC/MODE
12
PGND
13
3412 FBD
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OPERATIO
Main Control Loop
The LTC3412 is a monolithic, constant-frequency, current
mode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –2A for forced continuous mode and 0A for
Burst Mode operation.
The operating frequency is set by an external resistor
connected between the RT pin and ground. The practical
switching frequency can range from 300kHz to 4MHz.
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LTC3412
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OPERATIO
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition
clears or the bottom MOSFET’s current limit is reached.
peak inductor current will be determined by the voltage on
the ITH pin until the ITH voltage drops below 200mV. At this
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation but may be desirable
in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage between 0V
to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the ITH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the ITH pin drops. As the ITH voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top MOSFET is held
off and the ITH pin is disconnected from the output of the
error amplifier. The majority of the internal circuitry is also
turned off to reduce the quiescent current to 62μA while
the load current is solely supplied by the output capacitor.
When the output voltage drops, the ITH pin is reconnected
to the output of the error amplifier and the top power
MOSFET along with all the internal circuitry is switched
back on. This process repeats at a rate that is dependent
on the load demand.
Pulse skipping operation can be implemented by connecting the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
Frequency Synchronization
The internal oscillator of the LTC3412 can be synchronized
to an external clock connected to the SYNC/MODE pin. The
frequency of the external clock can be in the range of
300kHz to 4MHz. For this application, the oscillator timing
resistor should be chosen to correspond to a frequency
that is 25% lower than the synchronization frequency.
During synchronization, the burst clamp is set to 0V and
each switching cycle begins at the falling edge of the
external clock signal.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412 is designed to operate down to an input
supply voltage of 2.625V. One important consideration at
low input supply voltages is that the RDS(ON) of the Pchannel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
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LTC3412
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OPERATIO
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.8A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current falls to a safe level.
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APPLICATIO S I FOR ATIO
The basic LTC3412 application circuit is shown in Figure 1. External component selection is determined by the
maximum load current and begins with the selection of the
inductor value and operating frequency followed by CIN
and COUT.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge and switching losses but
requires larger inductance values and/or capacitance to
maintain low output ripple voltage.
The operating frequency of the LTC3412 is determined by
an external resistor that is connected between the RT pin
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
ROSC =
3.23 • 1011
f(Hz)
(Ω) − 10kΩ
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
⎤
⎡V
⎤⎡ V
ΔIL = ⎢ OUT ⎥ ⎢1 − OUT ⎥
VIN ⎦
⎣ fL ⎦ ⎣
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with
small ripple current. This, however, requires a large
inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
⎛ V
⎞
L = ⎜ OUT ⎟
⎝ fΔIL(MAX) ⎠
⎛
VOUT ⎞
⎜ 1− V
⎟
IN(MAX) ⎠
⎝
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation begins
when the peak inductor current falls below a level set by the
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase.
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Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, mollypermalloy,
or Kool Mμ® cores. Actual core loss is independent of core
size for a fixed inductor value but it is very dependent on
the inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate energy but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent
large ripple voltage, a low ESR input capacitor sized for the
maximum RMS current should be used. RMS current is
given by:
IRMS = IOUT (MAX)
VOUT
VIN
VIN
−1
VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients, as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔVOUT, is determined by:
⎛
1 ⎞
ΔVOUT ≤ ΔIL ⎜ ESR +
⎟
⎝
8fC OUT ⎠
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
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the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
⎛ R2⎞
VOUT = 0.8V ⎜ 1 + ⎟
⎝ R1⎠
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 2.
VOUT
R2
VFB
R1
LTC3412
SGND
3412 F02
Figure 2. Setting the Output Voltage
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the ITH pin will decrease. When the ITH voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
IBURST is determined by the desired amount of output
voltage ripple. As the value of IBURST increases, the sleep
period between pulses and the output voltage ripple increase. The burst clamp voltage, VBURST, can be set by a
resistor divider from the VFB pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by
connecting the SYNC/MODE pin to ground. This sets IBURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skipped while maintaining the output voltage in regulation.
Burst Clamp Programming
Frequency Synchronization
If the voltage on the SYNC/MODE pin is less than VIN by 1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, IBURST, for each switching cycle according to the following equation:
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external frequency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
⎛ 3.75A ⎞
IBURST = (VBURST − 0.2V ) ⎜
⎟
⎝ 0.8V ⎠
VBURST is the voltage on the SYNC/MODE pin. IBURST can
be programmed in the range of 0A to 3.75A. For values of
VBURST greater than 1V, IBURST is set at 3.75A. For values
of VBURST less than 0.2V, IBURST is set at 0A. As the output
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (IQ < 1μA).
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The LTC3412 contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
⎛
VIN ⎞
tSS = RSSC SS ln ⎜
⎟ (Seconds)
⎝ VIN − 1.8V ⎠
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG=f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW and external inductor RL. In continuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3412 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3412 is running at high ambient temperature with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3412 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
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The junction temperature, TJ, is given by:
First, calculate the timing resistor:
TJ = TA + TR
where TA is the ambient temperature.
ROSC =
3.23 • 1011
− 10k = 313k
1• 106
As an example, consider the LTC3412 in dropout at an
input voltage of 3.3V, a load current of 2.5A and an
ambient temperature of 70°C. From the typical performance graph of switch resistance, the RDS(ON) of the Pchannel switch at 70°C is approximately 97mΩ. Therefore, power dissipated by the part is:
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
PD = (ILOAD2)(RDS(ON)) = (2.5A)2(97mΩ) = 0.61W
Using a 1μH inductor, results in a maximum ripple current
of:
For the TSSOP package, the θJA is 37.6°C/W. Thus the
junction temperature of the regulator is:
TJ = 70°C + (0.61W)(37.6°C/W) = 93°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ΔILOAD(ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in Figure 1 will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3412 in an
application with the following specifications: VIN = 2.7V to
4.2V, VOUT = 2.5V, IOUT(MAX) = 2.5A, IOUT(MIN) = 10mA, f
= 1MHz. Because efficiency is important at both high and
low load current, Burst Mode operation will be utilized.
⎛ 2.5V ⎞ ⎛ 2.5V ⎞
L=⎜
⎟ = 1.01μH
⎟ ⎜ 1−
⎝ (1MHz)(1A)⎠ ⎝ 4.2V ⎠
⎛
⎞ ⎛ 2.5V ⎞
2.5V
ΔIL = ⎜
⎟ = 1.01A
⎟ ⎜ 1−
⎝ (1MHz)(1μH)⎠ ⎝ 4.2V ⎠
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. In this application,
two tantalum capacitors will be used to provide the bulk
capacitance and a ceramic capacitor in parallel to lower the
total effective ESR. For this design, two 100μF tantalum
capacitors in parallel with a 10μF ceramic capacitor will be
used. CIN should be sized for a maximum current rating of:
⎛ 2.5V ⎞ 4.2V
− 1 = 1.23ARMS
IRMS = (2.5A ) ⎜
⎟
⎝ 4.2V ⎠ 2.5V
Decoupling the PVIN and SVIN pins with a 22μF ceramic
capacitor and a 220μF tantalum capacitor is adequate for
most applications.
The burst clamp and output voltage can now be programmed by choosing the values of R1, R2 and R3. The
voltage on the MODE pin will be set to 0.32V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.32V will set the minimum inductor current, IBURST, as
follows:
⎛ 3.75V ⎞
IBURST = (0.32V − 0.2V ) ⎜
⎟ = 563mA
⎝ 0.8V ⎠
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If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
R2 + R3 = 185k
R2 0.8V
1+
=
R3 0.32V
The last two equations shown result in the following
values for R2 and R3: R2 = 110k , R3 = 75k. The value of
R1 can now be determined by solving the equation shown
below:
R1
2.5V
=
185k 0.8V
R1 = 393k
1+
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412. The exposed pad should
be connected to SGND.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail
in your system).
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT and
SGND.
Top Side
Bottom Side
Figure 3. LTC3412 Layout Diagram
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APPLICATIO S I FOR ATIO
VIN
2.7V TO 4.2V
CFB 22pF X5R
R1 392k
1
RPG
100k
PGOOD
CITH 680pF X7R RITH
7.15k
2
3
CC
100pF
RSS
4.7M
R2
110k
ROSC
309k
PVIN
PGOOD
SW
ITH
SW
LTC3412
4
R3
75k
SVIN
5
PGND
CSS
470pF X7R 8
CIN1††
220μF
15
14
L1*
1μH
13
VFB
PGND
SW
RUN
SW
SGND
PVIN
COUT2†
10μF
11
+
10
COUT1**
100μF
×2
9
CIN2
22μF
X5R 6.3V
*TOKO D62CB A920CY-1ROM
**SANYO POSCAP 4TPB100M
†TAIYO YUDEN LMK325BJ106MN
††SANYO POSCAP 2R5TPC220M
VOUT
2.5V
2.5A
12
RT
6 SYNC/MODE
7
16
GND
3412 F04
Figure 4. Single Lithium-Ion to 2.5V, 2.5A Regulator at 1MHz, Burst Mode Operation Using POSCAPs
3412fb
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LTC3412
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TYPICAL APPLICATIO S
2.5V, 2.5A Regulator Using All Ceramic Capacitors
VIN
2.7V TO 5.5V
CIN3**
100μF
C1 22pF X5R
R1 392k
1
RPG
100k
PGOOD
CITH 1000pF X7R RITH
15k
2
3
CC
100pF
RSS
4.7M
PVIN
PGOOD
SW
ITH
SW
LTC3412
4
R3
75k
SVIN
R2
110k
5
ROSC
309k
6
7
CSS
470pF X7R 8
PGND
16
CIN1
22μF
X5R 6.3V
15
14
L1*
1μH
13
VFB
PGND
VOUT
2.5V
2.5A
12
RT
SW
11
COUT**
100μF
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF
X5R 6.3V
GND
3412 F05
*TOKO D62CB A920CY-1ROM
**TDK C4532X5R0J107M
1.8V, 2.5A Step-Down Regulator at 1MHz, Burst Mode Operation
VIN
3.3V
C1 22pF X5R
R1 232k
1
RPG
100k
PGOOD
CITH 560pF X7R RITH
10k
2
3
C2
47pF
RSS
4.7M
PVIN
PGOOD
SW
ITH
SW
LTC3412
4
R3
75k
SVIN
R2
110k
5
ROSC
309k
6
7
CSS
470pF X7R 8
PGND
16
CIN1**
22μF
15
14
L1
1μH*
13
VFB
PGND
VOUT
1.8V
2A
12
RT
SW
11
COUT**
22μF
×2
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF**
3412 TA05
GND
*SUMIDA CR431R0
**AVX 12066D226MAT
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TYPICAL APPLICATIO S
2.5V, 2.5A Low Output Noise Regulator at 2MHz
CIN3
0.1μF
X5R
RIN
5Ω
R1 392k
1
RPG
100k
CITH 1000pF X7R RITH
22.1k
2
3
C1
56pF
R2
182k
5
ROSC
137k
6
7
CSS
470pF X7R 8
RSS
4.7M
SVIN
PVIN
PGOOD
SW
ITH
SW
LTC3412
4
PGND
CIN1**
100μF
16
15
14
L1
0.47μH*
13
VFB
PGND
VOUT
2.5V
2.5A
12
RT
SW
11
COUT**
100μF
×2
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
100μF**
3412 TA06
GND
*VISHAY DALE IHLP-2525CZ-01 0.47
**TDK C4532X5R0J107M
Efficiency vs Load Current
2MHz, Low Noise
100
90
80
EFFICIENCY (%)
PGOOD
VIN
3.3V
CFF 22pF X7R
70
60
50
40
30
20
10
0
0.01
0.1
1
LOAD CURRENT (A)
10
3412 TA07
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TYPICAL APPLICATIO S
3.3V, 2.5A Step-Down Regulator at 1MHz, Forced Continuous Mode Operation
VIN
5V
CIN3**
100μF
C1 22pF X5R
R1 634k
1
RPG
100k
PGOOD
2
CITH 1000pF X7R RITH
15k
3
CC
100pF
PVIN
PGOOD
CIN1
22μF
X5R 6.3V
15
SW
ITH
14
SW
LTC3412
4
L1*
1μH
13
PGND
VFB
R2
200k
5
ROSC
309k
6
7
CSS
470pF X7R 8
RSS
4.7M
SVIN
16
VOUT
3.3V
2.5A
12
PGND
RT
11
SW
COUT**
100μF
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF
X5R 6.3V
GND
3412 TA01
*PULSE P1166.162T
**TDK C4532X5R0J107M
Lithium-Ion to 3.3V, Single Inductor Buck-Boost Converter
GND
R1 576k
1
RPG
100k
PGOOD
CITH 1000pF X7R RITH
15k
2
3
C2
100pF
RSS
4.7M
R2
110k
ROSC
309k
SVIN
PVIN
PGOOD
SW
ITH
SW
LTC3412
4
R3
75k
5
6
7
CSS
470pF X7R 8
PGND
16
CIN1
22μF
X5R 6.3V
15
14
L1*
2μH
13
VFB
PGND
VOUT
3.3V
12
M1
SILICONIX
Si2302DS
RT
SW
D1
DIODES, INC.
B320A
11
COUT**
100μF
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF
X5R 6.3V
3412 F04
*TOKO D63CB
**TDK C4532X5R0J107M
VIN
2.7V TO 4.2V
CIN3**
100μF
×2
C1
22pF
GND
VIN
2.7V
3V
3.5V
4.2V
MAXIMUM IOUT
800mA
900mA
1.05A
1.2A
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PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 ±0.10
9
2.74
(.108)
4.50 ±0.10
2.74 6.40
(.108) (.252)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
BOTTOM VIEW—EXPOSED PAD
4.00 ± 0.10
(4 SIDES)
0.72 ±0.05
2.15 ± 0.05
(4 SIDES)
4.35 ± 0.05
2.90 ± 0.05
R = 0.115
TYP
0.75 ± 0.05
16
0.55 ± 0.20
PIN 1
TOP MARK
(NOTE 6)
1
2.15 ± 0.10
(4-SIDES)
PACKAGE
OUTLINE
0.30 ±0.05
0.65 BSC
15
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
2
(UF16) QFN 1004
0.200 REF
0.00 – 0.05
0.30 ± 0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3412fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3412
U
TYPICAL APPLICATIO
2.5V, 2.5A Step-Down Regulator Synchronized to 1.25MHz
CIN3**
100μF
C1 22pF X5R
VIN
2.7V TO 5.5V
R1 392k
1
RPG
100k
PGOOD
CITH 1000pF X7R RITH
15k
2
3
SVIN
PVIN
PGOOD
SW
ITH
SW
LTC3412
CC 100pF
4
PGND
CIN1
22μF
X5R 6.3V
15
14
L1*
1μH
13
VFB
R2 182k
5
16
PGND
VOUT
2.5V
2.5A
12
RT
ROSC 309k
1.25MHz 6 SYNC/MODE
EXT CLOCK 7
RUN
CSS
470pF X7R 8
SGND
RSS
4.7M
SW
SW
PVIN
11
COUT1**
100μF
10
9
CIN2
22μF
X5R 6.3V
*TOKO D62CB A920CY-1ROM
**TDK C4532X5R0J107M
GND
3412 TA02
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PART NUMBER
DESCRIPTION
COMMENTS
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VIN = 2.65V to 10V, 95% Efficiency, MSOP-8
LTC1878
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VIN = 2.65V to 6V, 95% Efficiency, MSOP-8
LTC1879
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VIN = 2.65V to 10V, 95% Efficiency, SSOP-16
LTC3404
600mA (IOUT), 1.4MHz Synchronous Step-Down Converter
VIN = 2.65V to 6V, 95% Efficiency, MSOP-8
LTC3405A
300mA (IOUT), 1.5MHz Synchronous Step-Down Converter
VIN = 2.65V to 6V, 96% Efficiency, ThinSOT Package
LTC3406/LTC3406B
600mA (IOUT), 1.5MHz Synchronous Step-Down Converter
VIN = 2.5V to 5.5V, 95% Efficiency, ThinSOT,
B Version: Burst Mode Defeat
LTC3411
1.25A (IOUT), 4MHz Synchronous Step-Down Converter
VIN = 2.5V to 5.5V, 95% Efficiency, MSOP-10
ThinSOT is a trademark of Linear Technology Corporation.
3412fb
20
Linear Technology Corporation
LT 0707 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002