PD - 97211
IRL1404ZPbF
IRL1404ZSPbF
IRL1404ZLPbF
AUTOMOTIVE MOSFET
Features
l
l
l
l
l
l
l
Logic Level
Advanced Process Technology
Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Lead-Free
HEXFET® Power MOSFET
D
VDSS = 40V
RDS(on) = 3.1mΩ
G
ID = 75A
Description
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low
on-resistance per silicon area. Additional features
of this design are a 175°C junction operating
temperature, fast switching speed and improved
repetitive avalanche rating . These features combine to make this design an extremely efficient and
reliable device for use in Automotive applications
and a wide variety of other applications.
S
S
D
G
TO-220AB
IRL1404ZPbF
G
S
D
S
D
G
D2Pak
IRL1404ZSPbF
TO-262
IRL1404ZLPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
EAS (Thermally limited)
EAS (Tested )
IAR
EAR
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V (Package Limited)
180
130
75
790
200
W
1.3
± 16
W/°C
V
190
490
See Fig.12a, 12b, 15, 16
mJ
c
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
d
c
g
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Junction-to-Ambient (PCB Mount)
i
i
j
h
Units
A
A
mJ
-55 to + 175
°C
300 (1.6mm from case )
10 lbf in (1.1N m)
y
y
Typ.
Max.
Units
–––
0.50
–––
0.75
–––
62
°C/W
–––
40
k
1
05/17/06
IRL1404Z/S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
∆V(BR)DSS/∆TJ
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Min. Typ. Max. Units
Conditions
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
40
–––
–––
–––
–––
1.4
120
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
0.034
2.5
–––
–––
–––
–––
–––
–––
–––
–––
75
28
40
19
180
30
49
4.5
–––
–––
3.1
4.7
5.9
2.7
–––
20
250
200
-200
110
–––
–––
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
5080
970
570
3310
870
1280
–––
–––
–––
–––
–––
–––
S
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 32V
gfs
IDSS
IGSS
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
VGS = 10V, ID = 75A
mΩ VGS = 5.0V, ID = 40A
VGS = 4.5V, ID = 40A
V VDS = VGS, ID = 250µA
S VDS = 10V, ID = 75A
µA VDS = 40V, VGS = 0V
VDS = 40V, VGS = 0V, TJ = 125°C
nA VGS = 16V
VGS = -16V
ID = 75A
nC VDS = 32V
VGS = 5.0V
VDD = 20V
ID = 75A
ns RG = 4.0Ω
VGS = 5.0V
D
Between lead,
e
e
e
e
e
nH
pF
G
f
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
180
ISM
(Body Diode)
Pulsed Source Current
–––
–––
720
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
26
18
1.3
39
27
c
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C,
L = 0.066mH, RG = 25Ω, IAS = 75A, VGS =10V.
Part not recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same
charging time as Coss while VDS is rising from 0 to
80% VDSS .
2
Conditions
MOSFET symbol
A
V
ns
nC
D
showing the
integral reverse
G
S
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V
TJ = 25°C, IF = 75A, VDD = 20V
di/dt = 100A/µs
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical
repetitive avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is only applied to TO-220AB package.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques
refer to application note #AN-994.
TO-220 device will have an Rth value of 0.65°C/W.
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IRL1404Z/S/LPbF
1000
1000
VGS
10V
7.0V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM
100
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
3.0V
60µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
BOTTOM
100
3.0V
10
60µs PULSE WIDTH
Tj = 175°C
1
100
0.1
V DS, Drain-to-Source Voltage (V)
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
200
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current (Α)
VGS
10V
7.0V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
T J = 175°C
100
10
T J = 25°C
VDS = 10V
60µs PULSE WIDTH
1.0
2
3
4
5
6
7
8
9
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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TJ = 25°C
150
100
T J = 175°C
50
V DS = 10V
0
10
0
50
100
150
200
ID,Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
vs. Drain Current
3
IRL1404Z/S/LPbF
100000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 75A
C, Capacitance(pF)
C oss = C ds + C gd
10000
Ciss
Coss
1000
Crss
4.0
3.0
2.0
1.0
0.0
100
1
10
100
0
VDS, Drain-to-Source Voltage (V)
40
60
80
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1000.00
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
20
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
T J = 175°C
100.00
10.00
T J = 25°C
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
1msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
1.00
10msec
1
0.0
0.5
1.0
1.5
2.0
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 32V
VDS= 20V
5.0
2.5
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL1404Z/S/LPbF
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
200
ID, Drain Current (A)
Limited By Package
150
100
50
ID = 75A
VGS = 10V
1.5
1.0
0.5
0
25
50
75
100
125
150
-60 -40 -20 0
175
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
T C , Case Temperature (°C)
Fig 10. Normalized On-Resistance
vs. Temperature
Fig 9. Maximum Drain Current vs.
Case Temperature
1
Thermal Response ( Z thJC )
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
0.01
0.001
τJ
1E-005
τJ
τ1
τ1
R2
R2
τ2
R3
R3
τ3
τ2
Ci= τi/Ri
Ci i/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
R1
R1
τC
τ
τ3
Ri (°C/W) τi (sec)
0.000213
0.212
0.277
0.001234
0.261
0.021750
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL1404Z/S/LPbF
DRIVER
L
VDS
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
800
15V
ID
TOP
15A
24A
BOTTOM 75A
700
600
500
400
300
200
100
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
I AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGS
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
3.0
2.5
2.0
ID = 250µA
1.5
1.0
0.5
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage vs. Temperature
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IRL1404Z/S/LPbF
100
Duty Cycle = Single Pulse
Avalanche Current (A)
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.05
0.10
10
1
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
200
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 75A
150
100
50
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
vs. Temperature
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175
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asT jmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRL1404Z/S/LPbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
V DD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
*
VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
V GS
RG
RD
D.U.T.
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRL1404Z/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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9
IRL1404Z/S/LPbF
D2Pak (TO-263AB) Package Outline
Dimensions are shown in millimeters (inches)
D2Pak (TO-263AB) Part Marking Information
7+,6,6$1,5)6:,7+
/27&2'(
$66(0%/('21::
,17+($66(0%/</,1(/
,17(51$7,21$/
5(&7,),(5
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IRL1404Z/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
(;$03/( 7+,6,6$1,5//
/27&2'(
$66(0%/('21::
,17+($66(0%/</,1(&
,17(51$7,21$/
5(&7,),(5
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11
IRL1404Z/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/06
12
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/