ASAHI KASEI [AK4642EN] AK4642EN Stereo CODEC with MIC/HP/SPK-AMP GENERAL DESCRIPTION The AK4642 features a stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording/playback function. The AK4642 is available in a 32pin QFN, utilizing less board space than competitive offerings. FEATURES 1. Recording Function • Stereo Mic Input (Full-differential or Single-ended) • Stereo Line Input • MIC Amplifier (+32dB/+26dB/+20dB or 0dB) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • ADC Performance: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB) • Wind-noise Reduction Filter • Stereo Separation Emphasis 2. Playback Function • Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz) • Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute) • Digital ALC (Automatic Level Control) (+36dB ∼ −54dB, 0.375dB Step, Mute) • Stereo Separation Emphasis • Stereo Line Output - Performance: S/(N+D): 88dB, S/N: 92dB • Stereo Headphone-Amp - S/(N+D): 70dB, S/N: 90dB - Output Power: 62mW@16Ω (HVDD=3.3V) - Pop Noise Free at Power ON/OFF • Mono Speaker-Amp - S/(N+D): 50dB@240mW, S/N: 90dB - BTL Output - Availbable for both Dynamic and Piezo Speaker - Output Power: 400mW@8Ω (HVDD=3.3V) 3.0Vrms@50Ω (HVDD=5V) • Analog Mixing: Mono Input 3. Power Management 4. Master Clock: (1) PLL Mode • Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode • Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs MS0420-E-00 2005/09 -1- ASAHI KASEI [AK4642EN] 6. Sampling Rate: • PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz • PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz • EXT Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. µP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz High Speed Mode) 8. Master/Slave mode 9. Audio Interface Format: MSB First, 2’s compliment • ADC : 16bit MSB justified, I2S • DAC : 16bit MSB justified, 16bit LSB justified, 16-24bit I2S 10. Ta = −30 ∼ 85°C (SPK-Amp=OFF) −30 ∼ 70°C (SPK-Amp=ON) 11. Power Supply: • AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V) • HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V) 12. Package: 32pin QFN (5mm x 5mm, 0.5mm pitch) 13. Register Upper-Compatible with Mono CODEC (AK4536/4630/4631) Block Diagram AVDD AVSS VCOM DVDD DVSS PMMP MPWR CSN CCLK CDTI PMADL or PMADR RIN1 MIC-Amp LIN2 External MIC Cont rol Register PMADL LIN1 Internal MIC I2C MIC Power Supply A/D Wind-Noise Reduction HPF Stereo Separation PDN ALC PMADR BICK RIN2 LRCK or SDTO Audio I/F SDTI Line In PMLO LOUT Line Out ROUT PMHPL PMDAC HPL D/A Headphone DATT Bass SMUTE Boost Stereo ALC Separation HPF PMHPR HPR MCKO PMPLL MUTET PLL MCKI VCOC PMSPK SPP Speaker SPN PMBP HVDD HVSS MIN Figure 1. Block Diagram MS0420-E-00 2005/09 -2- ASAHI KASEI [AK4642EN] Ordering Guide −30 ∼ +85°C 32pin QFN (0.5mm pitch) Evaluation board for AK4642 AK4642EN AKD4642 HPL HPR HVSS HVDD SPP SPN MCKO MCKI 24 23 22 21 20 19 18 17 Pin Layout 13 LRCK RIN2 / IN2− 29 Top View 12 SDTO LIN2 / IN2+ 30 11 SDTI LIN1 / IN1− 31 10 CDTI / SDA RIN1 / IN1+ 32 9 CCLK / SCL MS0420-E-00 CSN / CAD0 8 AK4642EN 7 28 PDN MIN 6 BICK I2C 14 5 27 VCOC LOUT 4 DVDD AVDD 15 3 26 AVSS ROUT 2 DVSS VCOM 16 1 25 MPWR MUTET 2005/09 -3- ASAHI KASEI [AK4642EN] Comparison with AK4537 Function Mic Input Stereo Mic Input MIC-Power MIC-Amp MIC ALC Wind-noise Reduction Filter Stereo Separation Emphasis Mono Mic Mode ALC for Playback DATT Bass Boost DAC Digital Filter Stopband Attenuation Line Output Level Usage for Piezo Speaker AK4537 Single-ended 1-Input 2-Output, RL=2kΩ (min) +20dB or 0dB +27.5dB to –8dB, 0.5dB step N/A N/A N/A SP only, +18dB to –8dB 0 to –127dB, Mute +5.74dB/+5.94dB/+16.04dB@20Hz AK4642EN Single-ended / Full-differential 2-Input selectable 1-Output, RL=0.5kΩ (min) +32dB/+26dB/+20dB or 0dB +36dB to –54dB, 0.375dB step, Mute Available Available Available Line/HP/SP, +36dB to –54dB +12 to –115dB, Mute +5.76dB/+10.80dB/+16.06dB@20Hz 43dB 59dB 1.98Vpp N/A PLL Input Frequency 11.2896MHz, 12MHz, 12.288MHz µP I/F X’tal MCKI AC Input MCKI Pull-down Analog Loopback Mono Line Output Stereo Beep Input Power Supply (HVDD) Package Register Map 4-wire/I2C(100kHz mode) Available Available Available Available Available Available 2.4 ∼ 3.6V 52pin QFN (7.2mm x 7.2mm) 1.98Vpp/2.50Vpp Available 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz 3-wire/I2C(400kHz mode) N/A N/A N/A N/A N/A N/A 2.6 ∼ 5.25V 32pin QFN (5mm x 5mm) No Compatibility MS0420-E-00 2005/09 -4- ASAHI KASEI [AK4642EN] Comparison with AK4631 Function Mic Input Stereo Mic Input ADC MIC ALC Wind-noise Reduction Filter Stereo Separation Emphasis ALC for Playback Soft Mute Bass Boost De-emphasis DAC HP-Amp Line Output Line Output Level µP I/F MCKI Pull-down Analog Loopback DSP Mode Package Regester Map AK4631 Single-ended N/A Mono +27.5dB to –8dB, 0.5dB step N/A N/A SP only, +18dB to –8dB N/A N/A N/A Mono N/A Mono 1.98Vpp 3-wire Available Available Available 28pin QFN (5.2mm x 5.2mm) MS0420-E-00 AK4642EN Single-ended / Full-differential Available Stereo +36dB to –54dB, 0.375dB step, Mute Available Available Line/HP/SP, +36dB to –54dB Available Available Available Stereo Available Stereo 1.98Vpp/2.50Vpp 3-wire/I2C N/A N/A N/A 32pin QFN (5mm x 5mm) Upper-compatible (Difference: ALC parameter, Analog Loopback & DSP Mode Removed) 2005/09 -5- ASAHI KASEI [AK4642EN] Register Compatibility with AK4631 AK4631 Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Input PGA Control Digital Volume Control ALC2 Mode Control D7 0 0 SPPS 0 PLL3 0 DVTM 0 0 0 DVOL7 0 D6 PMVCM 0 BEEPS AOPSN PLL2 0 ROTM ALC2 REF6 IPGA6 DVOL6 0 D5 PMBP 0 ALC2S MGAIN1 PLL1 FS3 ZTM1 ALC1 REF5 IPGA5 DVOL5 RFS5 D4 PMSPK 0 DACA SPKG1 PLL0 MSBS ZTM0 ZELM REF4 IPGA4 DVOL4 RFS4 D3 PMAO M/S DACM SPKG0 BCKO1 BCKP WTM1 LMAT1 REF3 IPGA3 DVOL3 RFS3 D2 PMDAC MCKPD MPWR BEEPA BCKO0 FS2 WTM0 LMAT0 REF2 IPGA2 DVOL2 RFS2 D1 PMMIC MCKO MICAD ALC1M DIF1 FS1 LTM1 RATT REF1 IPGA1 DVOL1 RFS1 D0 PMADC PMPLL MGAIN0 ALC1A DIF0 FS0 LTM0 LMTH REF0 IPGA0 DVOL0 RFS0 D1 0 MCKO 0 0 DIF1 FS1 0 RGAIN0 REF1 D0 PMADL PMPLL AK4642 Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH to 1FH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 D7 0 0 SPPSN LOVL PLL3 PS1 DVTM 0 REF7 D6 PMVCM HPMTN BEEPS LOPS PLL2 PS0 0 0 REF6 D5 PMBP PMHPL DACS MGAIN1 PLL1 FS3 ZTM1 ALC REF5 D4 PMSPK PMHPR DACL SPKG1 PLL0 0 ZTM0 ZELMN REF4 D3 PMLO M/S 0 SPKG0 BCKO 0 WTM1 LMAT1 REF3 D2 PMDAC 0 PMMP BEEPL 0 FS2 WTM0 LMAT0 REF2 MGAIN0 0 DIF0 FS0 0 LMTH0 REF0 IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 DVL7 RGAIN1 DVL6 LMTH1 DVL5 0 DVL4 0 DVL3 0 DVL2 0 DVL1 0 DVL0 0 Additional Function for AK4642 only Bits which are not needed for AK4642 MS0420-E-00 2005/09 -6- ASAHI KASEI [AK4642EN] PIN/FUNCTION No. 1 Pin Name MPWR I/O O Function MIC Power Supply Pin Common Voltage Output Pin, 0.45 x AVDD 2 VCOM O Bias voltage of ADC inputs and DAC outputs. 3 AVSS Analog Ground Pin 4 AVDD Analog Power Supply Pin Output Pin for Loop Filter of PLL Circuit 5 VCOC O This pin should be connected to AVSS with one resistor and capacitor in series. Control Mode Select Pin 6 I2C I “H”: I2C Bus, “L”: 3-wire Serial Power-Down Mode Pin 7 PDN I “H”: Power-up, “L”: Power-down, reset and initializes the control register. CSN I Chip Select Pin (I2C pin = “L”) 8 CAD0 I Chip Address 1 Select Pin (I2C pin = “H”) CCLK I Control Data Clock Pin (I2C pin = “L”) 9 SCL I Control Data Clock Pin (I2C pin = “H”) CDTI I Control Data Input Pin (I2C pin = “L”) 10 SDA I/O Control Data Input Pin (I2C pin = “H”) 11 SDTI I Audio Serial Data Input Pin 12 SDTO O Audio Serial Data Output Pin 13 LRCK I/O Input / Output Channel Clock Pin 14 BICK I/O Audio Serial Data Clock Pin 15 DVDD Digital Power Supply Pin 16 DVSS Digital Ground Pin 17 MCKI I External Master Clock Input Pin 18 MCKO O Master Clock Output Pin 19 SPN O Speaker Amp Negative Output Pin 20 SPP O Speaker Amp Positive Output Pin 21 HVDD Headphone & Speaker Amp Power Supply Pin 22 HVSS Headphone & Speaker Amp Ground Pin 23 HPR O Rch Headphone-Amp Output Pin 24 HPL O Lch Headphone-Amp Output Pin Mute Time Constant Control Pin 25 MUTET O Connected to HVSS pin with a capacitor for mute time constant. 26 ROUT O Rch Stereo Line Output Pin 27 LOUT O Lch Stereo Line Output Pin 28 MIN I Mono Signal Input Pin RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”) 29 I Microphone Negative Input 2 Pin (MDIF2 bit = “1”) IN2− LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”) 30 IN2+ I Microphone Positive Input 2 Pin (MDIF2 bit = “1”) LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”) 31 I Microphone Negative Input 1 Pin (MDIF1 bit = “1”) IN1− RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”) 32 IN1+ I Microphone Positive Input 1 Pin (MDIF1 bit = “1”) Note 1. All input pins except analog input pins (MIN, LIN1, RIN1, LIN2, RIN2) should not be left floating. Note 2. AVDD or AVSS voltage should be input to I2C pin. MS0420-E-00 2005/09 -7- ASAHI KASEI [AK4642EN] Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MPWR, VCOC, SPN, SPP, HPR, HPL, MUTET, ROUT, LOUT, MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ MCKO MCKI MS0420-E-00 Setting These pins should be open. This pin should be open. This pin should be connected to DVSS. 2005/09 -8- ASAHI KASEI [AK4642EN] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min Power Supplies: Analog AVDD −0.3 Digital DVDD −0.3 Headphone-Amp / Speaker-Amp HVDD −0.3 |AVSS – DVSS| (Note 4) ∆GND1 |AVSS – HVSS| (Note 4) ∆GND2 Input Current, Any Pin Except Supplies IIN Analog Input Voltage (Note 5) VINA −0.3 Digital Input Voltage (Note 6) VIND −0.3 Ambient Temperature (powered applied) Ta −30 Storage Temperature Tstg −65 Maximum Power Dissipation Pd1 Ta=85°C (Note 8) (Note 7) Pd2 Ta=70°C (Note 9) max 6.0 6.0 6.0 0.3 0.3 ±10 AVDD+0.3 DVDD+0.3 85 150 400 550 Units V V V V V mA V V °C °C mW mW Note 3. All voltages with respect to ground. Note 4. AVSS, DVSS and HVSS must be connected to the same analog ground plane. Note 5. I2C, MIN, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins Pull-up resistors at SDA and SCL pins should be connected to DVDD or less voltage. Note 7. In case that PCB wiring density is 100%. This power is the AK4642 internal dissipation that does not include power of externally connected speaker and headphone. Note 8. Speaker-Amp is not available. Note 9. Speaker-Amp is available. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, HVSS=0V; Note 3) Parameter Symbol min typ Power Supplies Analog AVDD 2.6 3.3 (Note 10) Digital DVDD 2.6 3.3 HP / SPK-Amp (Note 11) HVDD 2.6 3.3 / 5.0 Difference 0 AVDD−DVDD −0.3 Max 3.6 3.6 5.25 +0.3 Units V V V V Note 3. All voltages with respect to ground. Note 10. The power-up sequence between AVDD, DVDD and HVDD is not critical. When the power supplies are partially powered OFF, the AK4642 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. Note 11. HVDD = 2.6 ∼ 3.6V when 8Ω dynamic speaker is connected to the AK4642. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0420-E-00 2005/09 -9- ASAHI KASEI [AK4642EN] ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, HVDD=3.3V; AVSS=DVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) min typ max Parameter MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins; MDIF1 = MDIF2 bits = “0” (Single-ended inputs) Input MGAIN1-0 bits = “00” 40 60 80 Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 MGAIN1-0 bits = “00” 0 MGAIN1-0 bits = “01” +20 Gain MGAIN1-0 bits = “10” +26 MGAIN1-0 bits = “11” +32 MIC Amplifier: IN1+, IN1−, IN2+, IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Maximum Input Voltage (Note 12) MGAIN1-0 bits = “01” 0.228 MGAIN1-0 bits = “10” 0.114 MGAIN1-0 bits = “11” 0.057 MIC Power Supply: MPWR pin Output Voltage (Note 13) 2.22 2.47 2.72 Load Resistance 0.5 Load Capacitance 30 ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution 16 (Note 15) 0.168 0.198 0.228 Input Voltage (Note 14) (Note 16) 1.68 1.98 2.28 (Note 15) 71 83 S/(N+D) (−1dBFS) (Note 16) 88 (Note 15) 76 86 D-Range (−60dBFS, A-weighted) (Note 16) 95 (Note 15) 76 86 S/N (A-weighted) (Note 16) 95 (Note 15) 75 90 Interchannel Isolation (Note 16) 100 (Note 15) 0.1 0.8 Interchannel Gain Mismatch (Note 16) 0.1 0.8 Units kΩ kΩ dB dB dB dB Vpp Vpp Vpp V kΩ pF Bits Vpp Vpp dBFS dBFS dB dB dB dB dB dB dB dB Note 12. The voltage difference between IN1/2+ and IN1/2− pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential mic input is not available at MGAIN1-0 bits = “00”. Maximum input voltage of IN1+, IN1−, IN2+ and IN2− pins is proportional to AVDD voltage, respectively. Vin = 0.069 x AVDD (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. When the signal larger than above value is input to IN1+, IN1−, IN2+ or IN2− pin, ADC does not operate normally. Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ) Note 14. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 15. MGAIN1-0 bits = “01” (+20dB) Note 16. MGAIN1-0 bits = “00” (0dB) MS0420-E-00 2005/09 - 10 - ASAHI KASEI [AK4642EN] min typ max Units Parameter DAC Characteristics: Resolution 16 Bits Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, RL=10kΩ Output Voltage (Note 17) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp S/(N+D) (−3dBFS) 78 88 dBFS S/N (A-weighted) 82 92 dB Interchannel Isolation 80 100 dB Interchannel Gain Mismatch 0.1 0.5 dB Load Resistance 10 kΩ Load Capacitance 30 pF Headphone-Amp Characteristics: DAC → HPL/HPR pins, ALC=OFF, IVOL=0dB, DVOL=0dB Output Voltage (Note 18) 1.58 1.98 2.38 Vpp HPG bit = “0”, 0dBFS, HVDD=3.3V, RL=22.8Ω 2.40 3.00 3.60 Vpp HPG bit = “1”, 0dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 1.00 Vrms S/(N+D) 60 70 dBFS HPG bit = “0”, −3dBFS, HVDD=3.3V, RL=22.8Ω 80 dBFS HPG bit = “1”, −3dBFS, HVDD=5V, RL=100Ω HPG bit = “1”, 0dBFS, HVDD=3.3V, RL=16Ω (Po=62mW) 20 dBFS (Note 19) 80 90 dB S/N (A-weighted) (Note 20) 90 dB (Note 19) 65 75 dB Interchannel Isolation (Note 20) 80 dB (Note 19) 0.1 0.8 dB Interchannel Gain Mismatch (Note 20) 0.1 0.8 dB Load Resistance 16 Ω C1 in Figure 2 30 pF Load Capacitance C2 in Figure 2 300 pF Note 17. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ)@LOVL bit = “0”. Note 18. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD(typ)@HPG bit = “0”, 0.91 x AVDD(typ)@HPG bit = “1”. Note 19. HPG bit = “0”, HVDD=3.3V, RL=22.8Ω. Note 20. HPG bit = “1”, HVDD=5V, RL=100Ω. HP-Amp HPL/HPR pin Measurement Point 47µF C1 0.22µF 6.8Ω C2 16Ω 10Ω Figure 2. Headphone-Amp output circuit MS0420-E-00 2005/09 - 11 - ASAHI KASEI [AK4642EN] min typ max Units Parameter Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, RL=8Ω, BTL, HVDD=3.3V Output Voltage (Note 21) 3.11 Vpp SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) 3.13 3.92 4.71 Vpp SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW) 1.79 Vrms SPKG1-0 bits = “10”, −2.5dBFS (Po=400mW) S/(N+D) 60 dB SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) 20 50 dB SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW) 20 dB SPKG1-0 bits = “10”, −2.5dBFS (Po=400mW) S/N (A-weighted) 80 90 dB Load Resistance 8 Ω Load Capacitance 30 pF Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=0dB, DVOL=0dB, CL=3µF, Rserial=10Ω x 2, RL=50Ω, BTL, HVDD=5.0V Output Voltage SPKG1-0 bits = “10”, 0dBFS 6.75 Vpp (Note 21) SPKG1-0 bits = “11”, 0dBFS 6.80 8.50 10.20 Vpp S/(N+D) SPKG1-0 bits = “10”, 0dBFS 60 dB (Note 22) SPKG1-0 bits = “11”, 0dBFS 40 50 dB S/N (A-weighted) 80 90 dB Load Resistance (Note 23) 50 Ω Load Capacitance (Note 23) 3 µF Mono Input: MIN pin (External Input Resistance=20kΩ) Maximum Input Voltage (Note 24) 1.98 Vpp Gain (Note 25) MIN Æ LOUT/ROUT LOVL bit = “0” 0 +4.5 dB −4.5 LOVL bit = “1” +2 dB MIN Æ HPL/HPR HPG bit = “0” dB −24.5 −20 −15.5 HPG bit = “1” dB −16.4 MIN Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” +4.43 +8.93 dB −0.57 ALC bit = “0”, SPKG1-0 bits = “01” +6.43 dB ALC bit = “0”, SPKG1-0 bits = “10” +10.65 dB ALC bit = “0”, SPKG1-0 bits = “11” +12.65 dB ALC bit = “1”, SPKG1-0 bits = “00” +6.43 dB ALC bit = “1”, SPKG1-0 bits = “01” +8.43 dB ALC bit = “1”, SPKG1-0 bits = “10” +12.65 dB ALC bit = “1”, SPKG1-0 bits = “11” +14.65 dB Note 21. Output voltage is proportional to AVDD voltage. Vout = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0 bits = “11” at Full-differential output. Note 22. In case of measuring at SPP and SPN pins. Note 23. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 33. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be connected at both SPP and SPN pins, respectively. Note 24. Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 25. The gain is in inverse proportion to external input resistance. MS0420-E-00 2005/09 - 12 - ASAHI KASEI Parameter Power Supplies: Power-Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD (Note 26) HVDD: HP-Amp Normal Operation No Output (Note 27) HVDD: SPK-Amp Normal Operation No Output (Note 28) Power-Down (PDN pin = “L”) (Note 29) AVDD+DVDD+HVDD [AK4642EN] min typ max Units - 15 23 mA - 5 8 mA - 8 24 mA - 10 100 µA Note 26. PLL Master Mode (MCKI=12.288MHz) and PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S bits = “1”. MPWR pin outputs 0mA. AVDD=11mA(typ), DVDD=4mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=10mA(typ), DVDD=3mA(typ). Note 27. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMBP bits = “1” and PMSPK bit = “0”. Note 28. PMADL = PMADR = PMDAC = PMLO = PMSPK = PMVCM = PMPLL = PMBP bits = “1” and PMHPL = PMHPR bits = “0”. Note 29. All digital input pins are fixed to DVDD or DVSS. MS0420-E-00 2005/09 - 13 - ASAHI KASEI [AK4642EN] FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; fs=44.1kHz; DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 30) PB 0 17.3 kHz ±0.16dB 19.4 kHz −0.66dB 19.9 kHz −1.1dB 22.1 kHz −6.9dB Stopband SB 26.1 kHz Passband Ripple PR dB ±0.1 Stopband Attenuation SA 73 dB Group Delay (Note 31) GD 19 1/fs Group Delay Distortion 0 ∆GD µs ADC Digital Filter (HPF): (Note 32) Frequency Response (Note 30) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB DAC Digital Filter (LPF): Passband (Note 30) PB 0 19.6 kHz ±0.1dB 20.0 kHz −0.7dB 22.05 kHz −6.0dB Stopband SB 25.2 kHz Passband Ripple PR dB ±0.01 Stopband Attenuation SA 59 dB Group Delay (Note 31) GD 22 1/fs DAC Digital Filter (LPF) + SCF: FR dB Frequency Response: 0 ∼ 20.0kHz ±1.0 DAC Digital Filter (HPF): (Note 32) Frequency Response (Note 30) −3.0dB FR 0.9 Hz 2.7 Hz −0.5dB 6.0 Hz −0.1dB BOOST Filter: (Note 33) Frequency Response MIN FR 20Hz dB 5.76 100Hz dB 2.92 1kHz dB 0.02 MID FR 20Hz dB 10.80 100Hz dB 6.84 1kHz dB 0.13 MAX 20Hz FR dB 16.06 100Hz dB 10.54 1kHz dB 0.37 Note 30. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.454*fs (@-1.0dB). Each response refers to that of 1kHz. Note 31. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. Note 32. When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. Note 33. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale. MS0420-E-00 2005/09 - 14 - ASAHI KASEI [AK4642EN] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage VOH (Iout=−200µA) DVDD−0.2 Low-Level Output Voltage VOL (Except SDA pin: Iout=200µA) (SDA pin: Iout=3mA) VOL Input Leakage Current Iin - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; CL=20pF) Parameter Symbol min PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 256fs at fs=32kHz, 29.4kHz dMCK LRCK Output Timing Frequency fs 7.35 Duty Cycle Duty BICK Output Timing Period BCKO bit = “0” tBCK BCKO bit = “1” tBCK Duty Cycle dBCK PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 256fs at fs=32kHz, 29.4kHz dMCK LRCK Input Timing Frequency fs 7.35 Duty Duty 45 BICK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK MS0420-E-00 typ - Max 30%DVDD - Units V V V - 0.2 0.4 ±10 V V µA typ max Units - 27 - MHz ns ns - 12.288 MHz 50 33 60 - % % 50 48 - kHz % 1/(32fs) 1/(64fs) 50 - ns ns % - 27 - MHz ns ns - 12.288 MHz 50 33 60 - % % - 48 55 kHz % - 1/(32fs) - ns ns ns 2005/09 - 15 - ASAHI KASEI [AK4642EN] Parameter Symbol min PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs 7.35 Duty Duty 45 BICK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 240 Pulse Width High tBCKH 240 PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 Duty Duty 45 BICK Input Timing Period PLL3-0 bits = “0010” tBCK PLL3-0 bits = “0011” tBCK Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK External Slave Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 512fs fCLK 3.7632 1024fs fCLK 7.5264 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK LRCK Input Timing Frequency 256fs fs 7.35 512fs fs 7.35 1024fs fs 7.35 Duty Duty 45 BICK Input Timing Period tBCK 312.5 Pulse Width Low tBCKL 130 Pulse Width High tBCKH 130 Audio Interface Timing Master Mode tMBLR BICK “↓” to LRCK Edge (Note 34) −40 LRCK Edge to SDTO (MSB) tLRD −70 (Except I2S mode) tBSD BICK “↓” to SDTO −70 SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Slave Mode tLRB 50 LRCK Edge to BICK “↑” (Note 34) tBLR 50 BICK “↑” to LRCK Edge (Note 34) LRCK Edge to SDTO (MSB) tLRD (Except I2S mode) tBSD BICK “↓” to SDTO SDTI Hold Time tSDH 50 SDTI Setup Time tSDS 50 Note 34. BICK rising edge must not occur at the same time as LRCK edge. MS0420-E-00 typ max Units - 48 55 kHz % - 1/(32fs) - ns ns ns - 48 55 kHz % 1/(32fs) 1/(64fs) - - ns ns ns ns - 12.288 13.312 13.312 - MHz MHz MHz ns ns - 48 26 13 55 kHz kHz kHz % - - ns ns ns - 40 70 ns ns - 70 - ns ns ns - 80 ns ns ns - 80 - ns ns ns 2005/09 - 16 - ASAHI KASEI Parameter Control Interface Timing (3-wire Serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 35) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 36) PMADL or PMADR “↑” to SDTO valid (Note 37) [AK4642EN] Symbol min typ max Units tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 80 80 40 40 150 50 50 - - ns ns ns ns ns ns ns ns fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 1.3 0.6 1.3 0.6 0.6 0 0.1 0.6 0 - 400 0.3 0.3 50 kHz µs µs µs µs µs µs µs µs µs µs ns tPD tPDV 150 - 1059 - ns 1/fs Note 35. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 36. The AK4642 can be reset by the PDN pin = “L”. Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. MS0420-E-00 2005/09 - 17 - ASAHI KASEI [AK4642EN] Timing Diagram 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs 50%DVDD LRCK tLRCKH tLRCKL 1/fMCK Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 50%DVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 3. Clock Timing (PLL Master mode) 50%DVDD LRCK tBLR tBCKL BICK 50%DVDD tDLR tBSD SDTO 50%DVDD tSDS tSDH VIH SDTI VIL Figure 4. Audio Interface Timing (PLL Master mode) MS0420-E-00 2005/09 - 18 - ASAHI KASEI [AK4642EN] 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL tBCK Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH BICK VIL tBCKH tBCKL fMCK 50%DVDD MCKO tMCKL dMCK = tMCKL x fMCK x 100 Figure 5. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin) 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tLRCKH tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tBCK VIH BICK VIL tBCKH tBCKL Figure 6. Clock Timing (EXT Slave mode) MS0420-E-00 2005/09 - 19 - ASAHI KASEI [AK4642EN] VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD tLRD SDTO MSB 50%DVDD tSDH tSDS VIH SDTI VIL Figure 7. Audio Interface Timing (PLL/EXT Slave mode) MS0420-E-00 2005/09 - 20 - ASAHI KASEI [AK4642EN] VIH CSN VIL tCCKL tCSS tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 8. WRITE Command Input Timing tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 9. WRITE Data Input Timing VIH SDA VIL tBUF tLOW tHIGH tR tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA Start tSU:STO Stop Figure 10. I2C Bus Mode Timing MS0420-E-00 2005/09 - 21 - ASAHI KASEI [AK4642EN] PMADL bit or PMADR bit tPDV SDTO 50%DVDD Figure 11. Power Down & Reset Timing 1 tPD PDN VIL Figure 12. Power Down & Reset Timing 2 MS0420-E-00 2005/09 - 22 - ASAHI KASEI [AK4642EN] OPERATION OVERVIEW System Clock There are the following four clock modes to interface with external devices (see Table 1 and Table 2). Mode PMPLL bit M/S bit PLL3-0 bits PLL Master Mode 1 1 See Table 4 PLL Slave Mode 1 1 0 See Table 4 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode 0 0 x Don’t Care (Note 38) 0 1 x Note 38. If this mode is selected, the invalid clocks are output from MCKO pin when MCKO bit is “1”. Table 1. Clock Mode Setting (x: Don’t care) Mode MCKO bit 0 PLL Master Mode 1 0 PLL Slave Mode (PLL Reference Clock: MCKI pin) 1 PLL Slave Mode (PLL Reference Clock: LRCK or BICK pin) EXT Slave Mode MCKO pin “L” Selected by PS1-0 bits “L” Selected by PS1-0 bits 0 “L” MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits GND Selected by FS3-0 bits Table 2. Clock pins state in Clock Mode 0 “L” BICK pin Output (Selected by BCKO bit) Input (Selectet by BCKO bit) Input (Selected by BCKO bit) Input (≥ 32fs) Figure Figure 13 Figure 14 Figure 15 Figure 16 - LRCK pin Output (1fs) Input (1fs) Input (1fs) Input (1fs) Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4642 is power-down mode (PDN pin = “L”) and exits reset state, the AK4642 is slave mode. After exiting reset state, the AK4642 goes to master mode by changing M/S bit = “1”. When the AK4642 is used by master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and BICK pins of the AK4642 should be pulled-down or pulled-up by the resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode 1 Master Mode Table 3. Select Master/Slave Mode MS0420-E-00 Default 2005/09 - 23 - ASAHI KASEI [AK4642EN] PLL Mode When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4642 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. 1) Setting of PLL Mode Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit 0 1 2 0 0 0 0 0 0 0 0 1 0 1 0 PLL Reference Clock Input Pin LRCK pin N/A BICK pin 3 0 0 1 1 BICK pin 4 5 6 7 12 13 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 Others Others Input Frequency 1fs 32fs 64fs R and C of VCOC pin R[Ω] C[F] 6.8k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 220n 4.7n 10n 4.7n 10n 4.7n 4.7n 4.7n 4.7n 10n 10n MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 13.5MHz MCKI pin 27MHz N/A Table 4. Setting of PLL Mode (*fs: Sampling Frequency) PLL Lock Time (max) 160ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms Default 2) Setting of sampling frequency in PLL Mode When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz Default 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 4 0 1 0 0 7.35kHz 5 0 1 0 1 11.025kHz 6 0 1 1 0 14.7kHz 7 0 1 1 1 22.05kHz 10 1 0 1 0 32kHz 11 1 0 1 1 48kHz 14 1 1 1 0 29.4kHz 15 1 1 1 1 44.1kHz Others Others N/A Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and FS1-0 bits. (See Table 6). FS2 bit is “don’t care”. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 Don’t care 0 0 0 Default 7.35kHz ≤ fs ≤ 8kHz 0 Don’t care 1 1 0 8kHz < fs ≤ 12kHz 0 Don’t care 0 2 1 12kHz < fs ≤ 16kHz 0 Don’t care 1 3 1 16kHz < fs ≤ 24kHz 1 Don’t care 0 6 1 24kHz < fs ≤ 32kHz 1 Don’t care 1 7 1 32kHz < fs ≤ 48kHz Others Others N/A Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” MS0420-E-00 2005/09 - 24 - ASAHI KASEI [AK4642EN] PLL Unlock State 1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) In this mode, LRCK and BICK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is “1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see Table 7). After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state after a period of 1/fs. When sampling frequency is changed, BICK and LRCK pins do not output irregular frequency clocks but go to “L” by setting PMPLL bit to “0”. MCKO pin BICK pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid “L” Output PLL Unlock (except above case) “L” Output Invalid Invalid PLL Lock “L” Output See Table 9 See Table 10 Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) PLL State LRCK pin “L” Output Invalid 1fs Output 2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC and DAC output invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and DACS bits. MCKO pin MCKO bit = “0” MCKO bit = “1” After that PMPLL bit “0” Æ “1” “L” Output Invalid PLL Unlock “L” Output Invalid PLL Lock “L” Output Output Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”) PLL State MS0420-E-00 2005/09 - 25 - ASAHI KASEI [AK4642EN] PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (see Table 10). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz DSP or µP AK4642 MCKI 256fs/128fs/64fs/32fs MCKO 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 13. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) BICK Output Frequency 0 32fs Default 1 64fs Table 10. BICK Output Frequency at Master Mode BCKO bit MS0420-E-00 2005/09 - 26 - ASAHI KASEI [AK4642EN] PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4642 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5). 11.2896MHz, 12MHz, 12.288MHz 13.5MHz, 24MHz, 27MHz AK4642 DSP or µP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs ≥ 32fs 1fs MCLK BCLK LRCK SDTO SDTI SDTI SDTO Figure 14. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) b) PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6). AK4642 DSP or µP MCKO MCKI BICK LRCK 32fs, 64fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 15. PLL Slave Mode 2 (PLL Reference Clock: LRCK or BICK pin) The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4642 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). MS0420-E-00 2005/09 - 27 - ASAHI KASEI [AK4642EN] EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4642 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 11). Mode 0 1 2 3 Others MCKI Input Sampling Frequency Frequency Range Don’t care 0 0 256fs 7.35kHz ∼ 48kHz Don’t care 0 1 1024fs 7.35kHz ∼ 13kHz Don’t care 1 0 256fs 7.35kHz ∼ 48kHz Don’t care 1 1 512fs 7.35kHz ∼ 26kHz Others N/A N/A Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) FS3-2 bits FS1 bit FS0 bit Default The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output through LOUT/ROUT pins at fs=8kHz is shown in Table 12. S/N (fs=8kHz, 20kHzLPF + A-weighted) 256fs 83dB 512fs 93dB 1024fs 93dB Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins MCKI The external clocks (MCKI, BICK and LRCK) should always be present whenever the ADC or DAC is in operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4642 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC should be in the power-down mode (PMADL=PMADR=PMDAC bits = “0”). AK4642 DSP or µP MCKO 256fs, 512fs or 1024fs MCKI BICK LRCK MCLK ≥ 32fs 1fs BCLK LRCK SDTO SDTI SDTI SDTO Figure 16. EXT Slave Mode MS0420-E-00 2005/09 - 28 - ASAHI KASEI [AK4642EN] System Reset Upon power-up, the AK4642 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1” at PMDAC bits is “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is complete. When PMDAC bit is “1”, the ADC does not require an initialization cycle. The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an initialization cycle. Audio Interface Format Three types of data formats are available and are selected by setting the DIF1-0 bits (seeTable 13). In all modes, the serial data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK and BICK are output from the AK4642 in master mode, but must be input to the AK4642 in slave mode. The SDTO is clocked out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO (ADC) SDTI (DAC) N/A N/A MSB justified LSB justified MSB justified MSB justified I2S compatible I2S compatible Table 13. Audio Interface Format BICK N/A ≥ 32fs ≥ 32fs ≥ 32fs Figure Figure 17 Figure 18 Figure 19 Default If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at 8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) SDTI(i) 1 0 15 14 13 Don't Care 15 14 13 15 14 1 0 1 0 Don't Care 15 15 14 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 17. Mode 1 Timing MS0420-E-00 2005/09 - 29 - ASAHI KASEI [AK4642EN] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 7 6 5 4 3 2 1 0 15 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 13 1 0 SDTI(i) 15 14 13 1 0 Don't Care 15 14 13 1 0 15 14 13 1 0 15 Don't Care 15 15:MSB, 0:LSB Lch Data Rch Data Figure 18. Mode 2 Timing LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTO(o) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 SDTI(i) 0 15 14 8 7 6 5 4 3 2 1 0 15 14 8 7 6 5 4 3 2 1 0 0 1 2 3 15 16 17 18 31 0 1 2 3 15 16 17 18 31 0 1 BICK(64fs) SDTO(o) 15 14 2 1 0 SDTI(i) 15 14 2 1 0 Don't Care 15 14 2 1 0 15 14 2 1 0 Don't Care 15:MSB, 0:LSB Lch Data Rch Data Figure 19. Mode 3 Timing Mono/Stereo Mode PMADL and PMADR bits set mono/stereo ADC operation. PMADL bit 0 0 1 1 PMADR bit ADC Lch data 0 All “0” 1 Rch Input Signal 0 Lch Input Signal 1 Lch Input Signal Table 14. Mono/Stereo ADC operation MS0420-E-00 ADC Rch data All “0” Rch Input Signal Lch Input Signal Rch Input Signal Default 2005/09 - 30 - ASAHI KASEI [AK4642EN] Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 0.9Hz (@fs=44.1kHz) and scales with sampling rate (fs). When PMADL bit = “1” or PMADR bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADL=PMADR bits = “0”, PMDAC bit = “1”, the HPF of DAC is enabled but the HPF of ADC is disabled. MIC/LINE Input Selector The AK4642 has input selector. When MDIF1 and MDIF2 bits are “0”, INL and INR bits select LIN1/LIN2 and RIN1/RIN2, respectively. When MDIF1 and MDIF2 bits are “1”, LIN1, RIN1, LIN2 and RIN2 pins become IN1−, IN1+, IN2+ and IN2− pins respectively. In this case, full-differential input is available (Figure 21). MDIF1 bit MDIF2 bit INL bit 0 0 1 1 0 1 INR bit Lch 0 LIN1 0 1 LIN1 0 LIN2 1 1 LIN2 0 x LIN1 1 x N/A 0 N/A x 1 IN1+/− x x IN1+/− Table 15. MIC/Line In Path Select Rch RIN1 RIN2 RIN1 RIN2 IN2+/− N/A N/A RIN2 IN2+/− Default AK4642 INL bit LIN1/IN1− pin ADC Lch RIN1/IN1+ pin MDIF1 bit INR bit RIN2/IN2− pin ADC Rch LIN2/IN2+ pin MDIF2 bit Figure 20. Mic/Line Input Selector MS0420-E-00 2005/09 - 31 - ASAHI KASEI [AK4642EN] AK4642 MPWR pin 1k MIC-Amp IN1− pin IN1+ pin 1k Figure 21. Connection Example for Full-differential Mic Input (MDIF1/2 bits = “1”) MIC Gain Amplifier The AK4642 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 16). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01”, “10” or “11”. MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +20dB 0 +26dB 1 +32dB Table 16. Mic Input Gain Default MIC Power When PMMP bit = “1”, the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 0.5kΩ. In case of using two sets of stereo mic, the load resistance is minimum 2kΩ for each channel. No capacitor must not be connected directly to MPWR pin (see Figure 22). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 17. MIC Power Default MIC Power ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ ≥ 2kΩ MPWR pin Microphone LIN1 pin Microphone RIN1 pin Microphone LIN2 pin Microphone RIN2 pin Figure 22. MIC Block Circuit MS0420-E-00 2005/09 - 32 - ASAHI KASEI [AK4642EN] Digital EQ/HPF/LPF The AK4642 performs wind-noise reduction filter, stereo separation emphasis, gain compensation and ALC (Automatic Level Control) by digital domain for A/D converted data (Figure 23). FIL1, FIL3 and EQ blocks are IIR filters of 1st order. The filter coefficient of FIL3, EQ and FIL1 blocks can be set to any value. Refer to the section of “ALC operation” about ALC. When only DAC is powered-up, digital EQ/HPF/LPF circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. Therefore, FIL3, EQ, FIL1 and GN1-0 bits should be set to “0” if digital EQ/HPF/LPF is not used for playback path. PMADL bit, PMADR bit PMDAC bit 0 1 0 LOOP bit Status Digital EQ/HPF/LPF x Power-down Power-down “00” x Playback Playback path x Recording Recording path “01”, “10” or “11” 0 Recording & Playback Recording path 1 1 Recording Monitor Playback Recording path Note 39. Stereo separation emphasis circuit is effective only at stereo operation. Table 18. Digital EQ/HPF/LPF Cirtcuit Setting (x: Don’t care) Default FIL3 coefficient also sets the attenuation of the stereo separation emphasis. The combination of GN1-0 bit (Table 19) and EQ coefficient set the compensation gain. FIL1 and FIL3 blocks become HPF when F1AS and F3AS bits are “0” and become LPF when F1AS and F3AS bits are “1”, respectively. When EQ and FIL1 bits are “0”, EQ and FIL1 blocks become “through” (0dB). When FIL3 bit is “0”, FIL3 block become “MUTE”. When each filter coefficient is changed, each filter should be set to “through” (“MUTE” in case of FIL3). Wind-noise reduction FIL1 An y coefficient F1A13-0 F1B13-0 F1AS Stereo separation emphasis FIL3 Gain compensation EQ An y coefficient 0dB ∼ -10dB F3A13-0 MUTE F3B13-0 (set by F3AS FIL3 coefficient) Gain ALC An y coefficient GN1-0 EQA15-0 +24/+12/0dB EQB13-0 EQC15-0 +12dB ∼ 0dB Figure 23. Digital EQ/HPF/LPF GN1 GN0 Gain 0 0 0dB Default 0 1 +12dB 1 x +24dB Table 19. Gain select of gain block (x: Don’t care) MS0420-E-00 2005/09 - 33 - ASAHI KASEI [AK4642EN] [Filter Coefficient Setting] 1) When FIL1 and FIL3 are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of should be set to 0dB.) Register setting FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 / tan (πfc/fs) A = 10K/20 x , B= 1 + 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function 1−z H(z) = A Amplitude −1 2 − 2cos (2πf/fs) M(f) = A 1 + Bz −1 Phase θ(f) = tan −1 1 + B2 + 2Bcos (2πf/fs) (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1 and FIL3 are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1 should be set to 0dB.) Register setting FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) 1 − 1 / tan (πfc/fs) 1 A = 10K/20 x , 1 + 1 / tan (πfc/fs) Transfer function 1+z H(z) = A 1 + 1 / tan (πfc/fs) Amplitude −1 1 + Bz −1 B= 2 + 2cos (2πf/fs) M(f) = A 1 + B2 + 2Bcos (2πf/fs) MS0420-E-00 Phase θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs) 2005/09 - 34 - ASAHI KASEI [AK4642EN] 3) EQ fs: Sampling frequency fc1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc2/fs) , B= 1 + 1 / tan (πfc1/fs) A + Cz Amplitude −1 1 + Bz −1 C =10K/20 x 1 + 1 / tan (πfc1/fs) Transfer function H(z) = , 2 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Phase 2 A + C + 2ACcos (2πf/fs) M(f) = 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1 block Example: HPF, fs=44.1kHz, fc=100Hz F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ block Example: fs=44.1kHz, fc1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111 MS0420-E-00 2005/09 - 35 - ASAHI KASEI [AK4642EN] ALC Operation The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit operates at recording path. PMADL bit, PMADR bit “00” PMDAC bit 0 1 0 “01”, “10” or “11” 1. 1 LOOP bit Status x Power-down x Playback x Recording 0 Recording & Playback 1 Recording Monitor Playback Table 20. ALC Setting (x: Don’t care) ALC Power-down Playback path Recording path Recording path Recording path Default ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 21), the IVL and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 22). The IVL and IVR are then set to the same value for both channels. When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 23). When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits. The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 21) or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level 0 ALC Output ≥ −2.5dBFS −2.5dBFS > ALC Output ≥ −4.1dBFS 1 ALC Output ≥ −4.1dBFS −4.1dBFS > ALC Output ≥ −6.0dBFS 0 ALC Output ≥ −6.0dBFS −6.0dBFS > ALC Output ≥ −8.5dBFS 1 ALC Output ≥ −8.5dBFS −8.5dBFS > ALC Output ≥ −12dBFS Table 21. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 ZTM1 ZTM0 0 0 1 1 0 1 0 1 LMAT1 LMAT0 ALC Limiter ATT Step 0 0 1 step 0.375dB 0 1 2 step 0.750dB 1 0 4 step 1.500dB 1 1 8 step 3.000dB x x 1step 0.375dB Table 22. ALC Limiter ATT Step (x: Don’t care) Default Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 23. ALC Zero Crossing Timeout Period MS0420-E-00 Default Default 2005/09 - 36 - ASAHI KASEI 2. [AK4642EN] ALC Recovery Operation The ALC recovery operation waits for the WTM1-0 bits (Table 24) to be set after completing the ALC limiter operation. If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 21) during the wait time, the ALC recovery operation is done. The IVL and IVR values are automatically incremented by RGAIN1-0 bits (Table 25) up to the set reference level (Table 26) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 23). Then the IVL and IVR are set to the same value for both channels. The ALC recovery operation is done at a period set by WTM1-0 bits. When zero cross is detected at both channels during the wait period set by WTM1-0 bits, the ALC recovery operation waits until WTM1-0 period and the next recovery operation is done. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to “01”, IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When “ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)” during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When “ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”, the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. WTM1 WTM0 0 0 1 1 0 1 0 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 24. ALC Recovery Operation Waiting Period RGAIN1 0 0 1 1 RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 25. ALC Recovery GAIN Step Default Default REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H −53.25 02H −53.625 01H −54.0 00H MUTE Table 26. Reference Level at ALC Recovery operation MS0420-E-00 2005/09 - 37 - ASAHI KASEI 3. [AK4642EN] Example of ALC Operation Table 27 shows the examples of the ALC setting for mic recording. Register Name Comment LMTH ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data as ZTM1-0 bits Maximum gain at recovery operation WTM1-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Gain of IVOL Limiter ATT step Recovery GAIN step ALC enable Data 01 0 01 fs=8kHz Operation −4.1dBFS Enable 32ms Data 01 0 11 fs=44.1kHz Operation −4.1dBFS Enable 23.2ms 01 32ms 11 23.2ms E1H +30dB E1H +30dB E1H +30dB E1H +30dB 00 00 1 1 step 1 step Enable 00 1 step 00 1 step 1 Enable Table 27. Example of the ALC setting The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”. • LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS Manual Mode ALC bit = “1” WR (ZTM1-0, WTM1-0) (1) Addr=06H, Data=14H WR (REF7-0) (2) Addr=08H, Data=E1H WR (IVL/R7-0) * The value of IVOL should be (3) Addr=09H&0CH, Data=E1H the same or smaller than REF’s WR (RGAIN1, LMTH1) (4) Addr=0BH, Data=00H WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”) (5) Addr=07H, Data=01H ALC Operation Note : WR : Write Figure 24. Registers set-up sequence at ALC operation MS0420-E-00 2005/09 - 38 - ASAHI KASEI [AK4642EN] Input Digital Volume (Manual Mode) The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume. IVL7-0 and IVR7-0 bits set the gain of the volume control (Table 28). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 or IVR7-0 bits are written during PMADL=PMADR bits = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADL or PMADR bit is changed to “1”. Even if the path is switched from recording to playback, the register setting of IVOL remains. Therefore, IVL7-0 and IVR7-0 bits should be set to “91H” (0dB). IVL7-0 IVR7-0 F1H F0H EFH : E2H E1H E0H : 03H 02H 01H 00H GAIN (dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54 MUTE Table 28. Input Digital Volume Setting MS0420-E-00 Default 2005/09 - 39 - ASAHI KASEI [AK4642EN] When writing to the IVL7-0 and IVR7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL and IVR are not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL and IVR, this write operation is ignored and zero crossing counter is not reset. Therefore, IVL and IVR can be written by an interval less than zero crossing timeout. ALC bit ALC Status Disable Enable IVL7-0 bits E1H(+30dB) IVR7-0 bits C6H(+20dB) Internal IVL E1H(+30dB) Internal IVR C6H(+20dB) E1(+30dB) --> F1(+36dB) (1) Disable E1(+30dB) (2) E1(+30dB) --> F1(+36dB) C6H(+20dB) Figure 25. IVOL value during ALC operation (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. The wait time from ALC bit = “1” to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL and IVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to “1” by an interval more than zero crossing timeout period after ALC bit = “0”. MS0420-E-00 2005/09 - 40 - ASAHI KASEI [AK4642EN] De-emphasis Filter The AK4642 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 29). DEM1 0 0 1 1 DEM0 Mode 0 44.1kHz 1 OFF Default 0 48kHz 1 32kHz Table 29. De-emphasis Control Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal (Table 30). If the BST1-0 bits are set to “01” (MIN Level), use a 47µF capacitor for AC-coupling. If the boosted signal exceeds full scale, the analog output clips to the full scale. Figure 26 shows the boost frequency response at –20dB signal input. Boost Filter (fs=44.1kHz) 20 MAX Level [dB] 15 MID 10 MIN 5 0 -5 10 100 1000 10000 Frequency [Hz] Figure 26. Bass Boost Frequency Response (fs=44.1kHz) BST1 0 0 1 1 BST0 Mode 0 OFF 1 MIN 0 MID 1 MAX Table 30. Bass Boost Control MS0420-E-00 Default 2005/09 - 41 - ASAHI KASEI [AK4642EN] Digital Output Volume The AK4642 has a digital output volume (256 levels, 0.5dB step, Mute). The volume can be set by the DVL7-0 and DVR7-0 bits. The volume is included in front of a DAC block. The input data of DAC is changed from +12 to –115dB or MUTE. When the DVOLC bit = “1”, the DVL7-0 bits control both Lch and Rch attenuation levels. When the DVOLC bit = “0”, the DVL7-0 bits control Lch level and DVR7-0 bits control Rch level. This volume has a soft transition function. The DVTM bit sets the transition time between set values of DVL/R7-0 bits as either 1061/fs or 256/fs (Table 32). When DVTM bit = “0”, a soft transition between the set values occurs (1062 levels). It takes 1061/fs (=24ms@fs=44.1kHz) from 00H (+12dB) to FFH (MUTE). DVL/R7-0 Gain 00H +12.0dB 01H +11.5dB 02H +11.0dB : : 18H 0dB Default : : FDH −114.5dB FEH −115.0dB FFH MUTE (−∞) Table 31. Digital Volume Code Table DVTM bit 0 1 Transition time between DVL/R7-0 bits = 00H and FFH Setting fs=8kHz fs=44.1kHz 1061/fs 133ms 24ms 256/fs 32ms 6ms Table 32. Transition Time Setting of Digital Output Volume MS0420-E-00 Default 2005/09 - 42 - ASAHI KASEI [AK4642EN] Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by −∞ (“0”) during the cycle set by the DVTM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the value set by the DVL/R7-0 bits during the cycle set of the DVTM bit. If the soft mute is cancelled within the cycle set by the DVTM bit after starting the operation, the attenuation is discontinued and returned to the value set by the DVL/R7-0 bits. The soft mute is effective for changing the signal source without stopping the signal transmission (Figure 27). SM U T E bit D VTM bit D V L/R 7-0 bits D V TM bit (1) (3) Attenuation -∞ GD (2) GD Analog O utput Figure 27. Soft Mute Function (1) The output signal is attenuated until −∞ (“0”) by the cycle set by the DVTM bit. (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within the cycle set by the DVTM bit, the attenuation is discounted and returned to the value set by the DVL/R7-0 bits. MS0420-E-00 2005/09 - 43 - ASAHI KASEI [AK4642EN] Analog Mixing: Mono Input When the PMBP bit is set to “1”, the mono input is powered-up. When the BEEPS bit is set to “1”, the input signal from the MIN pin is output to Speaker-Amp. When the BEEPH bit is set to “1”, the input signal from the MIN pin is output to Headphone-Amp. When the BEEPL bit is set to “1”, the input signal from the MIN pin is output to the stereo line output amplifier. The external resister Ri adjusts the signal level of MIN input. Table 33, Table 34 and Table 35 show the typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Ri BEEPL MIN LOUT/ROUT pin BEEPH HPL/HPR pin BEEPS SPP/SPN pin Figure 7. Block Diagram of MIN pin LOVL bit MIN Æ LOUT/ROUT 0 0dB Default 1 +2dB Table 33. MIN Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ HPG bit MIN Æ HPL/HPR 0 Default −20dB 1 −16.4dB Table 34. MIN Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ MIN Æ SPP/SPN ALC bit = “0” ALC bit = “1” 00 +4.43dB +6.43dB Default 01 +6.43dB +8.43dB 10 +10.65dB +12.65dB 11 +12.65dB +14.65dB Table 35. MIN Input Æ Speaker-Amp Output Gain (typ) at Ri = 20kΩ SPKG1-0 bits MS0420-E-00 2005/09 - 44 - ASAHI KASEI [AK4642EN] Stereo Line Output (LOUT/ROUT pins) When DACL bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When DACL bit is “0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the PMLO bit = LOPS bit = “0”, the stereo line output enters power-down mode and the output is pulled-down to AVSS by 100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to AVSS by 20kΩ after AC coupled as Figure 29. Rise/Fall time is 300ms(max) at C=1µF. When PMLO bit = LOPS bit = “1”, stereo line output is in normal operation. LOVL bit set the gain of stereo line output. “DACL” “LOVL” LOUT pin DAC ROUT pin Figure 28. Stereo Line Output LOPS 0 1 PMLO Mode LOUT/ROUT pin 0 Power-down Pull-down to AVSS 1 Normal Operation Normal Operation 0 Power-save Fall down to AVSS 1 Power-save Rise up to VCOM Table 36. Stereo Line Output Mode Select (x: Don’t care) Default LOVL Gain Output Voltage (typ) 0 0dB 0.6 x AVDD Default 1 +2dB 0.757 x AVDD Table 37. Stereo Line Output Volume Setting LOUT ROUT 1µF 220Ω 20kΩ Figure 29. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit) MS0420-E-00 2005/09 - 45 - ASAHI KASEI [AK4642EN] [Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit)] (2 ) (5 ) P M L O b it (1 ) (3 ) (4 ) (6 ) L O P S b it L O U T , R O U T p in s N o r m a l O u tp u t ≥ 300 m s ≥ 300 m s Figure 30. Stereo Line Output Control Sequence (in case of using Pop Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF. (3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “1”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to AVSS. Fall time is 200ms (max 300ms) at C=1µF. (6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode. MS0420-E-00 2005/09 - 46 - ASAHI KASEI [AK4642EN] Headphone Output Power supply voltage for the Headphone-Amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The load resistance is 16Ω (min). HPG bit selects the output voltage (see Table 38). HPG bit 0 1 Output Voltage [Vpp] 0.6 x AVDD 0.91 x AVDD Table 38. Headphone-Amp Output Voltage When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL and HPR pins) go to “L” (HVSS). When the HPMTN bit is “1”, the common voltage rises to HVDD/2. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant is in proportional to HVDD voltage and the capacitor at MUTET pin. [Example]: A capacitor between the MUTET pin and ground = 1.0µF, HVDD=3.3V: Rise/fall time constant: τ = 100ms(typ), 250ms(max) Time until the common goes to HVSS when HPMTN bit = “1” Æ “0”: 500ms(max) When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go to “L” (HVSS). PMHPL bit, PMHPR bit HPMTN bit HPL pin, HPR pin (1) (2) (3) (4) Figure 31. Power-up/Power-down Timing for Headphone-Amp (1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still HVSS. (2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising. (3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling. (4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are HVSS. If the power supply is switched off or Headphone-Amp is powered-down before the common voltage goes to HVSS, some POP noise occurs. MS0420-E-00 2005/09 - 47 - ASAHI KASEI [AK4642EN] When BOOST=OFF, the cut-off frequency (fc) of Headphone-Amp depends on the external resistor and capacitor. This fc can be shifted to lower frequency by using bass boost function. Table 39 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at HVDD = 2.7, 3.0 and 3.3V. The output voltage of headphone is 0.6 x AVDD (Vpp). When an external resistor R is smaller than 12Ω, put an oscillation prevention circuit (0.22µF±20% capacitor and 10Ω±20% resistor) because it has the possibility that Headphone-Amp oscillates. HP-AMP AK4642 R 0.22µ C Headphone 16Ω 10Ω Figure 32. External Circuit Example of Headphone HPG bit R [Ω] 6.8 0 16 0 1 100 C [µF] 100 47 100 47 220 100 22 10 fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN @fs=44.1kHz 70 28 149 78 50 19 106 47 45 17 100 43 62 25 137 69 Table 39. External Circuit Example MS0420-E-00 Output Power [mW]@0dBFS 2.7V 3.0V 3.3V 10.1 12.5 15.1 5.1 6.3 7.7 33 41 50 0.9 1.1 1.3 2005/09 - 48 - ASAHI KASEI [AK4642EN] Speaker Output Power supply for Speaker-Amp (HVDD) is 2.6V to 5.25V. In case of dynamic (electromagnetic) speaker (load resistance < 50Ω), HVDD is 2.6V to 3.6V. Speaker Type Dynamic Speaker Piezo (Ceramic) Speaker HVDD 2.6 ∼ 3.6V 2.6 ∼ 5.25V Load Resistance (min) 8Ω 50Ω (Note 23) Load Capacitance (max) 30pF 3µF (Note 23) Note 23. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 33. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be connected at both SPP and SPN pins, respectively. Table 40. Speaker Type and Power Supply Range The DAC output signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits. SPKG1-0 bits 00 01 10 11 Gain ALC bit = “0” ALC bit = “1” +4.43dB +6.43dB +6.43dB +8.43dB +10.65dB +12.65dB +12.65dB +14.65dB Table 41. SPK-Amp Gain Default SPK-Amp Output (DAC Input = 0dBFS) ALC bit = “0” ALC bit = “1” (LMTH1-0 bits = “00”) 00 3.30Vpp 3.11Vpp 01 4.15Vpp (Note 40) 3.92Vpp 3.3V 10 6.75Vpp (Note 40) 6.37Vpp (Note 40) 11 8.50Vpp (Note 40) 8.02Vpp (Note 40) 3.3V 00 3.30Vpp 3.11Vpp 01 4.15Vpp 3.92Vpp 5.0V 10 6.75Vpp 6.37Vpp 11 8.50Vpp 8.02Vpp Note 40. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped. Table 42. SPK-Amp Output Level AVDD HVDD SPKG1-0 bits MS0420-E-00 2005/09 - 49 - ASAHI KASEI [AK4642EN] <ALC Operation Example of Speaker Playback> fs=44.1kHz Operation −2.5dBFS Enable 11.6ms Register Name Comment LMTH ZELMN ZTM1-0 Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data as ZTM1-0 bits Maximum gain at recovery operation 11 23.2ms C1H +18dB Gain of IVOL 91H 0dB WTM1-0 REF7-0 IVL7-0, IVR7-0 LMAT1-0 RGAIN1-0 ALC Data 00 0 10 Limiter ATT step 00 Recovery GAIN step 00 ALC enable 1 Table 43. ALC Operation Example of Speaker Playback 1 step 1 step Enable <Caution for using Piezo Speaker> When a piezo speaker (load capacitance > 30pF) is used, resistances more than 10Ω should be inserted between SPP/SPN pins and speaker in series, respectively, as shown in Figure 33. Zener diodes should be inserted between speaker and GND as shown in Figure 33, in order to protect SPK-Amp of AK4642 from the power that the piezo speaker outputs when the speaker is pressured. Zener diodes of the following zener voltage should be used. 0.92 x HVDD ≤ Zener voltage of zener diodo (ZD in Figure 33) ≤ HVDD+0.3V Ex) In case of HVDD = 5.0V: 4.6V ≤ ZD ≤ 5.3V For example, zener diode which zener voltage is 5.1V(Min: 4.97V, Max: 5.24V) can be used. ZD SPK-Amp SPP ≥10Ω SPN ≥10Ω ZD Figure 33. Speaker Output Circuit (Load Capacitance > 30pF) MS0420-E-00 2005/09 - 50 - ASAHI KASEI [AK4642EN] <Speaker-Amp Control Sequence> Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pin are in Hi-Z state. When PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-Amp enters power-save mode. In this mode, SPP pin is placed in Hi-Z state and SPN pin goes to HVDD/2 voltage. Power-save mode can reduce the pop noise at power-up and power-down. PMSPK 0 1 SPPSN Mode SPP SPN x Power-down Hi-Z Hi-Z 0 Power-save Hi-Z HVDD/2 1 Normal Operation Normal Operation Normal Operation Table 44. Speaker-Amp Mode Setting (x: Don’t care) Default PMSPK bit SPPSN bit SPP pin SPN pin Hi-Z Hi-Z Hi-Z HVDD/2 HVDD/2 Hi-Z Figure 34. Power-up/Power-down Timing for Speaker-Amp MS0420-E-00 2005/09 - 51 - ASAHI KASEI [AK4642EN] Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge(“↓”). Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by PDN pin = “L”. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A2 A0 D7 D6 D5 D4 D3 D2 D1 D0 “1” “0” “1” C1-C0: R/W: A4-A0: D7-D0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address Control data Figure 35. Serial Control I/F Timing MS0420-E-00 2005/09 - 52 - ASAHI KASEI [AK4642EN] (2) I2C-bus Control Mode (I2C pin = “H”) The AK4642 supports the fast-mode I2C-bus (max: 400kHz). (2)-1. WRITE Operations Figure 36 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits (Figure 37). If the slave address matches that of the AK4642, the AK4642 generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 43). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4642. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 39). The AK4642 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 42). The AK4642 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4642 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K P A C K A C K Figure 36. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 1 CAD0 R/W (Those CAD1/0 should match with CAD1/0 pins) Figure 37. The First Byte 0 0 0 A4 A3 A2 A1 A0 D2 D1 D0 Figure 38. The Second Byte D7 D6 D5 D4 D3 Figure 39. Byte Structure after the second byte MS0420-E-00 2005/09 - 53 - ASAHI KASEI [AK4642EN] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4642. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 1FH prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4642 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4642 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4642 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4642 ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) Data(n+2) A C K A C K Data(n+x) A C K P A C K A C K Figure 40. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4642 then generates an acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition, the AK4642 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 41. RANDOM ADDRESS READ MS0420-E-00 2005/09 - 54 - ASAHI KASEI [AK4642EN] SDA SCL S P start condition stop condition Figure 42. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 43. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 44. Bit Transfer on the I2C-Bus MS0420-E-00 2005/09 - 55 - ASAHI KASEI [AK4642EN] Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name Power Management 1 Power Management 2 Signal Select 1 Signal Select 2 Mode Control 1 Mode Control 2 Timer Select ALC Mode Control 1 ALC Mode Control 2 Lch Input Volume Control Lch Digital Volume Control ALC Mode Control 3 Rch Input Volume Control Rch Digital Volume Control Mode Control 3 Mode Control 4 Power Management 3 Digital Filter Select FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 D7 0 0 SPPSN LOVL PLL3 PS1 DVTM 0 REF7 D6 PMVCM HPMTN BEEPS LOPS PLL2 PS0 0 0 REF6 D5 PMBP PMHPL DACS MGAIN1 PLL1 FS3 ZTM1 ALC REF5 D4 PMSPK PMHPR DACL SPKG1 PLL0 0 ZTM0 ZELMN REF4 D3 PMLO M/S 0 SPKG0 BCKO 0 WTM1 LMAT1 REF3 D2 PMDAC 0 PMMP BEEPL 0 FS2 WTM0 LMAT0 REF2 D1 0 MCKO 0 0 DIF1 FS1 0 RGAIN0 REF1 D0 PMADL PMPLL MGAIN0 0 DIF0 FS0 0 LMTH0 REF0 IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 DVL7 RGAIN1 IVR7 DVR7 0 0 0 GN1 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 DVL6 LMTH1 IVR6 DVR6 LOOP 0 0 GN0 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 DVL5 0 IVR5 DVR5 SMUTE 0 HPG 0 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 DVL4 0 IVR4 DVR4 DVOLC 0 MDIF2 FIL1 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 DVL3 0 IVR3 DVR3 BST1 IVOLC MDIF1 EQ F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 DVL2 0 IVR2 DVR2 BST0 HPM INR FIL3 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 DVL1 0 IVR1 DVR1 DEM1 BEEPH INL 0 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 DVL0 0 IVR0 DVR0 DEM0 DACH PMADR 0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 Note 41. PDN pin = “L” resets the registers to their default values. Note 42. Unused bits must contain a “0” value. MS0420-E-00 2005/09 - 56 - ASAHI KASEI [AK4642EN] Register Definitions Addr 00H Register Name Power Management 1 Default D7 0 0 D6 PMVCM 0 D5 PMBP 0 D4 PMSPK 0 D3 PMLO 0 D2 PMDAC 0 D1 0 0 D0 PMADL 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (Default) 1: Power-up When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (Default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (Default) 1: Power-up PMSPK: Speaker-Amp Power Management 0: Power-down (Default) 1: Power-up PMBP: MIN Input Power Management 0: Power-down (Default) 1: Power-up Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL, BEEPH or BEEPS bit is used to control each path when MIN input is used. PMVCM: VCOM Power Management 0: Power-down (Default) 1: Power-up When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H, PMPLL and MCKO bits are “0”. Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H, 01H, 02H and 10H addresses and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present. MS0420-E-00 2005/09 - 57 - ASAHI KASEI Addr 01H Register Name Power Management 2 Default [AK4642EN] D7 0 0 D6 HPMTN 0 D5 PMHPL 0 D4 PMHPR 0 D3 M/S 0 D2 0 0 D1 MCKO 0 D0 PMPLL 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (Default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode Select 0: Slave Mode (Default) 1: Master Mode PMHPR: Headphone-Amp Rch Power Management 0: Power-down (Default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (Default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (Default) 1: Normal operation MS0420-E-00 2005/09 - 58 - ASAHI KASEI Addr 02H Register Name Signal Select 1 Default [AK4642EN] D7 SPPSN 0 D6 BEEPS 0 D5 DACS 0 D4 DACL 0 D3 0 0 D2 PMMP 0 D1 0 0 D0 MGAIN0 1 MGAIN1-0: MIC-Amp Gain Control (See Table 16) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (Default) 1: Power-up DACL: Switch Control from DAC to Stereo Line Output 0: OFF (Default) 1: ON When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. DACS: Switch Control from DAC to Speaker-Amp 0: OFF (Default) 1: ON When DACS bit is “1”, DAC output signal is input to Speaker-Amp. BEEPS: Switch Control from MIN pin to Speaker-Amp 0: OFF (Default) 1: ON When BEEPS bit is “1”, mono signal is input to Speaker-Amp. SPPSN: Speaker-Amp Power-Save Mode 0: Power-Save Mode (Default) 1: Normal Operation When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, SPP pin goes to Hi-Z and SPN pin is outputs HVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “H”, Speaker-Amp is in power-down mode since PMSPK bit is “0”. MS0420-E-00 2005/09 - 59 - ASAHI KASEI Addr 03H Register Name Signal Select 2 Default [AK4642EN] D7 LOVL 0 D6 LOPS 0 D5 MGAIN1 0 D4 SPKG1 0 D3 SPKG0 0 D2 BEEPL 0 D1 0 0 D0 0 0 BEEPL: Switch Control from MIN pin to Stereo Line Output 0: OFF (Default) 1: ON When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS. SPKG1-0: Speaker-Amp Output Gain Select (See Table 41) MGAIN1: MIC-Amp Gain Control (See Table 16) LOPS: Stereo Line Output Power-Save Mode 0: Normal Operation (Default) 1: Power-Save Mode LOVL: Stereo Line Output Gain Select (Table 37) 0: 0dB (Default) 1: +2dB Addr 04H Register Name Mode Control 1 Default D7 PLL3 0 D6 PLL2 0 D5 PLL1 0 D4 PLL0 0 D3 BCKO 0 D2 0 0 D1 DIF1 1 D0 DIF0 0 D3 0 0 D2 FS2 0 D1 FS1 0 D0 FS0 0 DIF1-0: Audio Interface Format (See Table 13) Default: “10” (Left jutified) BCKO: BICK Output Frequency Select at Master Mode (See Table 10) PLL3-0: PLL Reference Clock Select (See Table 4) Default: “0000”(LRCK pin) Addr 05H Register Name Mode Control 2 Default D7 PS1 0 D6 PS0 0 D5 FS3 0 D4 0 0 FS3-0: Sampling Frequency Select (See Table 5 and Table 6.) and MCKI Frequency Select (See Table 11.) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. PS1-0: MCKO Output Frequency Select (Table 9) Default: “00”(256fs) MS0420-E-00 2005/09 - 60 - ASAHI KASEI Addr 06H Register Name Timer Select Default [AK4642EN] D7 DVTM 0 D6 0 0 D5 ZTM1 0 D4 ZTM0 0 D3 WTM1 0 D2 WTM0 0 D1 0 0 D0 0 0 D1 0 D0 LMTH0 0 D1 REF1 0 D0 REF0 1 WTM1-0: ALC Recovery Waiting Period (see Table 24.) Default: “00” (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 23.) Default: “00” (128/fs) DVTM: Digital Volume Transition Time Setting (see Table 32.) 0: 1061/fs (Default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. Addr 07H Register Name ALC Mode Control 1 Default D7 0 0 D6 0 0 D5 ALC 0 D4 ZELMN 0 D3 LMAT1 0 D2 LMAT0 0 RGAIN0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 21.) Default: “00” LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (see Table 25.) Default: “00” RGAIN1 bit is D7 bit of 03H. LMAT1-0: ALC Limiter ATT Step (see Table 22.) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (Default) 1: Disable ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable Addr 08H Register Name ALC Mode Control 2 Default D7 REF7 1 D6 REF6 1 D5 REF5 1 D4 REF4 0 D3 REF3 0 D2 REF2 0 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (see Table 26.) Default: “E1H” (+30.0dB) MS0420-E-00 2005/09 - 61 - ASAHI KASEI Addr 09H 0CH Register Name Lch Input Volume Control Rch Input Volume Control Default [AK4642EN] D7 IVL7 IVR7 1 D6 IVL6 IVR6 1 D5 IVL5 IVR5 1 D4 IVL4 IVR4 0 D3 IVL3 IVR3 0 D2 IVL2 IVR2 0 D1 IVL1 IVR1 0 D0 IVL0 IVR0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (see Table 28.) Default: “E1H” (+30.0dB) Addr 0AH 0DH Register Name Lch Digital Volume Control Rch Digital Volume Control Default D7 DVL7 DVR7 0 D6 DVL6 DVR6 0 D5 DVL5 DVR5 0 D4 DVL4 DVR4 1 D3 DVL3 DVR3 1 D2 DVL2 DVR2 0 D1 DVL1 DVR1 0 D0 DVL0 DVR0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 0 0 D2 BST0 0 D1 DEM1 0 D0 DEM0 1 DVL7-0, DVR7-0: Output Digital Volume (see Table 31.) Default: “18H” (0dB) Addr 0BH Register Name ALC Mode Control 3 Default D7 RGAIN1 0 D6 LMTH1 0 D5 0 0 LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 21.) RGAIN1: ALC Recovery GAIN Step (see Table 25.) Addr 0EH Register Name Mode Control 3 Default D7 0 0 D6 LOOP 0 D5 SMUTE 0 D4 DVOLC 1 D3 BST1 0 DEM1-0: De-emphasis Frequency Select (Table 29) Default: “01” (OFF) BST1-0: Bass Boost Function Select (Table 30) Default: “00” (OFF) DVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOLC bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: Digital Loopback Mode 0: SDTI → DAC (Default) 1: SDTO → DAC MS0420-E-00 2005/09 - 62 - ASAHI KASEI Addr 0FH Register Name Mode Control 4 Default [AK4642EN] D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 IVOLC 1 D2 HPM 0 D1 BEEPH 0 D0 DACH 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (Default) 1: ON BEEPH: Switch Control from MIN pin to Headphone-Amp 0: OFF (Default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (Default) 1: Mono When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-Amp. Both PMHPL and PMHPR bits should be “1” when HPM bit is “1”. IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (Default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. MS0420-E-00 2005/09 - 63 - ASAHI KASEI Addr 10H Register Name Power Management 3 Default [AK4642EN] D7 0 0 D6 0 0 D5 HPG 0 D4 MDIF2 0 D3 MDIF1 0 D2 INR 0 D1 INL 0 D0 PMADR 0 PMADR: MIC-Amp Lch and ADC Rch Power Management 0: Power-down (Default) 1: Power-up INL: ADC Lch Input Source Select 0: LIN1 pin (Default) 1: LIN2 pin INR: ADC Rch Input Source Select 0: RIN1 pin (Default) 1: RIN2 pin MDIF1: ADC Lch Input Type Select 0: Single-ended input (LIN1/LIN2 pin: Default) 1: Full-differential input (IN1+/IN1− pin) MDIF2: ADC Rch Input Type Select 0: Single-ended input (RIN1/RIN2 pin: Default) 1: Full-differential input (IN2+/IN2− pin) HPG: Headphone-Amp Gain Select (see Table 38.) 0: 0dB (Default) 1: +3.6dB MS0420-E-00 2005/09 - 64 - ASAHI KASEI Addr 11H Register Name Digital Filter Select Default [AK4642EN] D7 GN1 0 D6 GN0 0 D5 0 0 D4 FIL1 0 D3 EQ 0 D2 FIL3 0 D1 0 0 D0 0 0 GN1-0: Gain Select at GAIN block (see Table 19.) Default: “00” FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block is OFF (MUTE). EQ: EQ (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When EQ bit is “1”, the settings of EQA15-0, EQB13-0 and EQC15-0 bits are enabled. When EQ bit is “0”, EQ block is through (0dB). FIL1: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (Default) 1: Enable When FIL1 bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When FIL1 bit is “0”, FIL1 block is through (0dB). MS0420-E-00 2005/09 - 65 - ASAHI KASEI Addr 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Register Name FIL3 Co-efficient 0 FIL3 Co-efficient 1 FIL3 Co-efficient 2 FIL3 Co-efficient 3 EQ Co-efficient 0 EQ Co-efficient 1 EQ Co-efficient 2 EQ Co-efficient 3 EQ Co-efficient 4 EQ Co-efficient 5 FIL1 Co-efficient 0 FIL1 Co-efficient 1 FIL1 Co-efficient 2 FIL1 Co-efficient 3 Default [AK4642EN] D7 F3A7 F3AS F3B7 0 EQA7 EQA15 EQB7 0 EQC7 EQC15 F1A7 F1AS F1B7 0 0 D6 F3A6 0 F3B6 0 EQA6 EQA14 EQB6 0 EQC6 EQC14 F1A6 0 F1B6 0 0 D5 F3A5 F3A13 F3B5 F3B13 EQA5 EQA13 EQB5 EQB13 EQC5 EQC13 F1A5 F1A13 F1B5 F1B13 0 D4 F3A4 F3A12 F3B4 F3B12 EQA4 EQA12 EQB4 EQB12 EQC4 EQC12 F1A4 F1A12 F1B4 F1B12 0 D3 F3A3 F3A11 F3B3 F3B11 EQA3 EQA11 EQB3 EQB11 EQC3 EQC11 F1A3 F1A11 F1B3 F1B11 0 D2 F3A2 F3A10 F3B2 F3B10 EQA2 EQA10 EQB2 EQB10 EQC2 EQC10 F1A2 F1A10 F1B2 F1B10 0 D1 F3A1 F3A9 F3B1 F3B9 EQA1 EQA9 EQB1 EQB9 EQC1 EQC9 F1A1 F1A9 F1B1 F1B9 0 D0 F3A0 F3A8 F3B0 F3B8 EQA0 EQA8 EQB0 EQB8 EQC0 EQC8 F1A0 F1A8 F1B0 F1B8 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (Default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: EQ (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1AS: FIL1 (Wind-noise Reduction Filter) Select 0: HPF (Default) 1: LPF MS0420-E-00 2005/09 - 66 - ASAHI KASEI [AK4642EN] SYSTEM DESIGN Figure 45 and Figure 46 shows the system connection diagram for the AK4642. An evaluation board [AKD4642] is available which demonstrates the optimum layout, power supply arrangements and measurement results. Headphone Line Out 1u 200 1u Mono In External MIC 21 20 19 18 17 HVDD SPP SPN MCKO MCKI R1 22 HVSS 10 R2 47u 6.8 1u 200 23 0.22u HPR 10 ZD1 24 0.22u Dynamic SPK R1, R2: Short ZD1, ZD2: Open Piezo SPK R1, R2: ≥10Ω ZD1, ZD2: Required HPL 10 ZD2 0.1u 47u 6.8 10u 20k 20k Power Supply 2.6 ∼ 3.6V Speaker 25 MUTET DVSS 16 26 ROUT DVDD 15 27 LOUT BICK 14 13 0.1u DSP 28 MIN AK4642EN LRCK 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 I2C PDN CSN 6 7 8 µP Rp AVDD VCOC 4 5 AVSS 3 0.1u VCOM 2.2u 0.1u 2 MPWR 1 2.2k 2.2k 2.2k 2.2k Internal MIC Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4642 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4642 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4642 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. - When piezo speaker is used, 2.6 ∼ 5.25V power should be supplied to HVDD and 10Ω or more series resistors should be connected to both SPP and SPN pins, respectively. - When the AK4642 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4642. Figure 45. Typical Connection Diagram (MIC Input) MS0420-E-00 2005/09 - 67 - ASAHI KASEI [AK4642EN] Headphone Line Out Mono In 200 1u 200 1u 21 20 19 18 17 HVDD SPP SPN MCKO MCKI R1 22 HVSS 10 R2 47u 6.8 1u 23 0.22u HPR 10 ZD1 24 0.22u Dynamic SPK R1, R2: Short ZD1, ZD2: Open Piezo SPK R1, R2: ≥10Ω ZD1, ZD2: Required HPL 10 ZD2 0.1u 47u 6.8 10u 20k 20k Power Supply 2.6 ∼ 3.6V Speaker 25 MUTET DVSS 16 26 ROUT DVDD 15 27 LOUT BICK 14 0.1u DSP 28 MIN AK4642EN LRCK 13 29 RIN2 Top View SDTO 12 30 LIN2 SDTI 11 31 LIN1 CDTI 10 32 RIN1 CCLK 9 I2C PDN CSN 6 7 8 µP Rp AVDD VCOC 4 5 AVSS 3 0.1u VCOM 2 2.2u 0.1u 1 MPWR Line In Cp Analog Ground Digital Ground Notes: - AVSS, DVSS and HVSS of the AK4642 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK4642 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK4642 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. - When piezo speaker is used, 2.6 ∼ 5.25V power should be supplied to HVDD and 10Ω or more series resistors should be connected to both SPP and SPN pins, respectively. - When the AK4642 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, 100kΩ around pull-up resistor should be connected to LRCK and BICK pins of the AK4642. Figure 46. Typical Connection Diagram (Line Input) MS0420-E-00 2005/09 - 68 - ASAHI KASEI [AK4642EN] 1. Grounding and Power Supply Decoupling The AK4642 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and HVDD are supplied separately, the power-up sequence is not critical. AVSS, DVSS and HVSS of the AK4642 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4642 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4642. 3. Analog Inputs The Mic, Line and MIN inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp (typ) for the Mic input and 0.6 x AVDD Vpp (typ) for the MIN input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4642 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Stereo Line Output is centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2. MS0420-E-00 2005/09 - 69 - ASAHI KASEI [AK4642EN] CONTROL SEQUENCE Clock Set up When ADC or DAC is powered-up, the clocks must be supplied. 1. PLL Master Mode. Example: Power Supply Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 8kHz (1) PDN pin (2) (3) PMVCM bit (Addr:00H, D6) (4) (1) Power Supply & PDN pin = “L” Æ “H” MCKO bit (Addr:01H, D1) PMPLL bit (2)Addr:01H, Data:08H Addr:04H, Data:4AH Addr:05H, Data:00H (Addr:01H, D0) (5) MCKI pin Input M/S bit (3)Addr:00H, Data:40H (Addr:01H, D3) 40msec(max) (6) BICK pin LRCK pin Output (4)Addr:01H, Data:0BH Output MCKO, BICK and LRCK output 40msec(max) (8) MCKO pin (7) Figure 47. Clock Set Up Sequence (1) <Example> (1) After Power Up, PDN pin = “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4642. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. (3) Power UpVCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered-up before the other block operates. (4) In case of using MCKO output: MCKO bit = “1” In case of not using MCKO output: MCKO bit = “0” (5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. (6) The AK4642 starts to output the LRCK and BICK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = “1”. (8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = “1”. MS0420-E-00 2005/09 - 70 - ASAHI KASEI [AK4642EN] 2. PLL Slave Mode (LRCK or BICK pin) Example: Power Supply Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PDN pin (2) 4fs (1)ofPower Supply & PDN pin = “L” Æ “H” (3) PMVCM bit (Addr:00H, D6) PMPLL bit (2) Addr:04H, Data:32H Addr:05H, Data:00H (Addr:01H, D0) LRCK pin BICK pin Input (3) Addr:00H, Data:40H (4) Internal Clock (5) (4) Addr:01H, Data:01H Figure 48. Clock Set Up Sequence (2) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4642. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK is a PLL reference clock. (5) Normal operation stats after that the PLL is locked. MS0420-E-00 2005/09 - 71 - ASAHI KASEI [AK4642EN] 3. PLL Slave Mode (MCKI pin) Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 8kHz Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (3) (2)Addr:04H, Data:4AH Addr:05H, Data:00H PMVCM bit (Addr:00H, D6) (4) MCKO bit (Addr:01H, D1) (3)Addr:00H, Data:40H PMPLL bit (Addr:01H, D0) (5) MCKI pin (4)Addr:01H, Data:03H Input 40msec(max) (6) MCKO pin MCKO output start Output (7) (8) BICK pin LRCK pin Input BICK and LRCK input start Figure 49. Clock Set Up Sequence (3) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4642. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Enable MCKO output: MCKO bit = “1” (5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max). (6) The normal clock is output from MCKO after PLL is locked. (7) The invalid frequency is output from MCKO during this period. (8) BICK and LRCK clocks should be synchronized with MCKO clock. MS0420-E-00 2005/09 - 72 - ASAHI KASEI [AK4642EN] 4. EXT Slave Mode Example: Audio I/F Format: MSB justified (ADC and DAC) Input MCKI frequency: 1024fs Sampling Frequency: 8kHz MCKO: Disable Power Supply (1) Power Supply & PDN pin = “L” Æ “H” (1) PDN pin (2) (2) Addr:04H, Data:02H Addr:05H, Data:01H (3) PMVCM bit (Addr:00H, D6) (4) MCKI pin Input (3) Addr:00H, Data:40H (4) LRCK pin BICK pin Input MCKI, BICK and LRCK input Figure 50. Clock Set Up Sequence (4) <Example> (1) After Power Up: PDN pin “L” Æ “H” “L” time of 150ns or more is needed to reset the AK4642. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” Æ “1” VCOM should first be powered up before the other block operates. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied. MS0420-E-00 2005/09 - 73 - ASAHI KASEI [AK4642EN] MIC Input Recording (Stereo) Example: FS3-0 bits X,XXX PLL Master Mode Audio I/F Format:MSB justified (ADC & DAC) Sampling Frequency:44.1kHz Pre MIC AMP:+20dB MIC Power On ALC setting:Refer to Figrure 23 ALC bit=“1” 1,111 (Addr:05H, D5&D2-0) (1) MIC Control (Addr:02H, D2-0) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) (1) Addr:05H, Data:27H 001 101 (2) Addr:02H, Data:05H (2) XXH 3CH (3) Addr:06H, Data:3CH E1H (4) Addr:08H, Data:E1H (3) XXH (4) (5) Addr:0BH, Data:00H ALC Control 3 (Addr:0BH) XXH 00H (6) Addr:07H, Data:21H (5) ALC Control 4 (Addr:07H) XXH 21H 01H (6) ALC State (9) ALC Disable ALC Enable ALC Disable (7) Addr:00H, Data:41H Addr:10H, Data:01H Recording PMADL/R bit (Addr:00H&10H, D0) 1059 / fs (8) (7) ADC Internal State Power Down (8) Addr:00H, Data:40H Addr:10H, Data:00H Initialize Normal State Power Down (9) Addr:07H, Data:01H Figure 51. MIC Input Recording Sequence <Example> This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to “Figure 24. Registers set-up sequence at ALC operation” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK4642 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 02H) (3) Set up Timer Select for ALC (Addr: 06H) (4) Set up REF value for ALC (Addr: 08H) (5) Set up LMTH1 and RGAIN1 bits (Addr: 0BH) (6) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H) (7) Power Up MIC and ADC: PMADL = PMADR bits = “0” → “1” The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz. After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL default value (+30dB). The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be shorter by using the following sequence: At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling capacitor at analog input pin and the internal input resistance 60k(typ). (8) Power Down MIC and ADC: PMADL = PMADR bits = “1” → “0” When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling frequency is changed, it should be done after the AK4642 goes to the manual mode (ALC bit = “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADC or PMADR bit is changed to “1”. (9) ALC Disable: ALC bit = “1” → “0” MS0420-E-00 2005/09 - 74 - ASAHI KASEI [AK4642EN] Speaker-amp Output FS3-0 bits (Addr:05H, D5&D2-0) X,XXX 1,111 Example: (1) PLL Master Mode Audio I/F Format: MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: 0dB ALC: Enable (13) DACS bit (Addr:02H, D3) (2) SPKG1-0 bits (Addr:03H, D4-3) ALC Control 1 (Addr:06H) ALC Control 2 (Addr:08H) ALC Control 3 (Addr:0BH) (1) Addr:05H, Data:27H 00 01 (2) Addr:02H, Data:20H (3) XXH 3CH (3) Addr:03H, Data:08H (4) XXH C1H (4) Addr:06H, Data:3CH (5) XXH 00H (5) Addr:08H, Data:E1H X (6) Addr:0BH, Data:00H (6) ALC bit (Addr:07H, D5) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 0 (7) E1H (7) Addr:07H, Data:20H 91H (8) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (8) Addr:09H & 0CH, Data:91H 18H XXH (9) (14) PMDAC bit (9) Addr:0AH & 0DH, Data:28H (Addr:00H, D2) (10) Addr:00H, Data:74H PMBP bit (Addr:00H, D5) (11) Addr:02H, Data:A0H (10) PMSPK bit (Addr:00H, D4) Playback (11) SPPSN bit (Addr:02H, D7) (12) Addr:02H, Data:20H (12) SPP pin Hi-Z Normal Output Hi-Z (13) Addr:02H, Data:00H SPN pin Hi-Z HVDD/2 Normal Output HVDD/2 Hi-Z (14) Addr:00H, Data:40H Figure 52. Speaker-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Speaker-Amp should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up the path of “DAC Æ SPK-Amp”: DACS bit = “0” Æ “1” (3) SPK-Amp gain setting: SPKG1-0 bits = “00” Æ “01” (4) Set up Timer Select for ALC (Addr: 06H) (5) Set up REF value for ALC (Addr: 08H) (6) Set up LMTH1 and RGAIN1 bits (Addr: 0BH) (7) Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H) When PMADL or PMADR bit is “1”, ALC for DAC path is disabled. (8) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (9) Set up the output digital volume (Addr: 0AH and 0DH). When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (10) Power Up of DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. (11) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1” (12) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0” (13) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” Æ “0” (14) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMBP = PMSPK bits = “1” → “0” MS0420-E-00 2005/09 - 75 - ASAHI KASEI [AK4642EN] Mono signal output from Speaker-Amp Example: Clocks can be stopped. CLOCK (1) Addr:00H, Data:70H PMBP bit (Addr:00H, D5) (1) (5) (2) Addr:02H, Data:60H PMSPK bit (Addr:00H, D4) DACS bit (Addr:02H, D5) (3) Addr:02H, Data:E0H X 0 (2) (6) BEEPS bit Mono Signal Output (Addr:02H, D6) (3) SPPSN bit (4) Addr:02H, Data:60H (Addr:02H, D7) (4) SPP pin SPN pin Hi-Z Hi-Z Normal Output HVDD/2 Normal Output Hi-Z HVDD/2 (5) Addr:00H, Data:40H Hi-Z (6) Addr:02H, Data:00H Figure 53. “BEPP-Amp Æ Speaker-Amp” Output Sequence <Example> The clocks can be stopped when only MIN-Amp and Speaker-Amp are operating. (1) Power Up MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “0” → “1” (2) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “0” Enable the path of “MIN Æ SPK-Amp”: BEEPS bit = “0” → “1” (3) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1” (4) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0” (5) Power Down MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “1” → “0” (6) Disable the path of “MIN Æ SPK-Amp”: BEEPS bit = “1” → “0” MS0420-E-00 2005/09 - 76 - ASAHI KASEI [AK4642EN] Headphone-amp Output E x a m p le : FS3-0 bits (Addr:05H, D5&D2-0) X,XXX P L L M a s te r M o d e S a m p lin g F r e q u e n c y : 4 4 . 1 k H z D V O L C b it = “ 1 ” ( d e fa u lt ) D ig ita l V o lu m e L e v e l: 0 d B B a s s B o o s t L e v e l: M id d le D e -e m p h a s e s re s p o n s e : O F F S o ft M u te T im e : 2 5 6 /fs 1,111 (1) ( 1 ) A d d r : 0 5 H , D a t a :2 7 H DACH bit (2) (Addr:0FH, D0) (13) ( 2 ) A d d r : 0 F H , D a ta 0 9 H BST1-0 bits (Addr:0EH, D3-2) IVL/R7-0 bits (Addr:09H&0CH, D7-0) 00 XX 00 (3) E1H (4 ) A d d r:0 9 H & 0 C H , D a ta 9 1 H 91H (4) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (3 ) A d d r:0 E H , D a ta 1 4 H (12) ( 5 ) A d d r : 0 A H & 0 D H , D a ta 2 8 H 18H XXH (6 ) A d d r:0 0 H , D a ta 6 4 H (5) PMDAC bit (7 ) A d d r:0 1 H , D a ta 3 9 H (Addr:00H, D2) (6) (11) PMBP bit (8 ) A d d r:0 1 H , D a ta 7 9 H P la y b a c k (Addr:00H, D5) (9 ) A d d r:0 1 H , D a ta 3 9 H PMHPL/R bits (7) (10) (Addr:01H, D5-4) HPMTN bit ( 1 0 ) A d d r :0 1 H , D a t a 0 9 H (8) (9) (Addr:01H, D6) ( 1 1 ) A d d r :0 0 H , D a t a 4 0 H ( 1 2 ) A d d r :0 E H , D a ta 0 0 H HPL/R pins Normal Output ( 1 3 ) A d d r :0 F H , D a ta 0 8 H Figure 54. Headphone-Amp Output Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bits). (2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1” (3) Set up the low frequency boost level (BST1-0 bits) (4) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (5) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (6) Power up DAC and MIN-Amp: PMDAC = PMBP bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. (7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1” Output voltage of headphone-amp is still HVSS. (8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1” The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0µF, the time constant is τr = 100ms(typ), 250ms(max). (9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0” The fall time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V and the capacitor value is 1.0µF, the time constant is τ f = 100ms(typ), 250ms(max). If the power supply is powered-off or headphone-Amp is powered-down before the common voltage goes to GND, the pop noise occurs. It takes twice of τf that the common voltage goes to GND. (10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0” (11) Power down DAC and MIN-Amp: PMDAC = PMBP bits = “1” → “0” (12) Off the bass boost: BST1-0 bits = “00” (13) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0” MS0420-E-00 2005/09 - 77 - ASAHI KASEI [AK4642EN] Stereo Line Output Example: FS3-0 bits (Addr:05H, D5&D2-0) X,XXX PLL, Master Mode Audio I/F Format :MSB justified (ADC & DAC) Sampling Frequency: 44.1kHz Digital Volume: 0dB MGAIN1=SPKG1=SPKG0=BEEPL bits = “0” 1,111 (1) (1) Addr:05H, Data:27H (10) DACL bit (2) (2) Addr:02H, Data:10H (Addr:02H, D4) IVL/R7-0 bits (Addr:09H&0CH, D7-0) E1H (3) Addr:09H&0CH, Data:91H 91H (3) DVL/R7-0 bits (Addr:0AH&0DH, D7-0) (4) Addr:0AH&0DH, Data:28H 18H XXH (5) Addr:03H, Data:40H (4) LOPS bit (6) Addr:00H, Data:6CH (Addr:03H, D6) (7) (5) (8) (11) PMDAC bit (Addr:00H, D2) Playback PMBP bit (8) Addr:03H, Data:40H (Addr:00H, D5) (6) (9) (9) Addr:00H, Data:40H PMLO bit (Addr:00H, D3) LOUT pin ROUT pin (7) Addr:03H, Data:00H >300 ms (10) Addr:02H, Data:00H >300 ms Normal Output (11) Addr:03H, Data:00H Figure 55. Stereo Lineout Sequence <Example> At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up the sampling frequency (FS3-0 bits). When the AK4642 is PLL mode, DAC and Stereo Line-Amp should be powered-up in consideration of PLL lock time after the sampling frequency is changed. (2) Set up the path of “DAC Æ Stereo Line Amp”: DACL bit = “0” Æ “1” (3) Set up the input digital volume (Addr: 09H and 0CH) When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB). (4) Set up the output digital volume (Addr: 0AH and 0DH) When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by the soft transition. (5) Enter power-save mode of Stereo Line Amp: LOPS bit = “0” Æ “1” (6) Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0” → “1” The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization cycle, the DAC input digital data of both channels are internally forced to a 2's compliment, “0”. The DAC output reflects the digital input data after the initialization cycle is complete. When PMADC or PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by IVL/R7-0 bits) during an intialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits. LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time is 300ms(max) at C=1µF. (7) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation by setting LOPS bit to “0”. (8) Enter power-save mode of Stereo Line-Amp: LOPS bit: “0” Æ “1” (9) Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1” → “0” LOUT and ROUT pins fall down to AVSS. Fall time is 300ms(max) at C=1µF. (10) Disable the path of “DAC Æ Stereo Line-Amp”: DACL bit = “1” Æ “0” (11) Exit power-save mode of Stereo Line-Amp: LOPS bit = “1” Æ “0” LOPS bit should be set to “0” after LOUT and ROUT pins fall down. MS0420-E-00 2005/09 - 78 - ASAHI KASEI [AK4642EN] Stop of Clock Master clock can be stopped when ADC and DAC are not used. 1. PLL Master Mode Example: Audio I/F Format: MSB justified (ADC & DAC) BICK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) MCKO bit "H" or "L" (1) (2) Addr:01H, Data:08H (Addr:01H, D1) (3) External MCKI Input (3) Stop an external MCKI Figure 56. Clock Stopping Sequence (1) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop MCKO clock: MCKO bit = “1” → “0” (3) Stop an external master clock. 2. PLL Slave Mode (LRCK or BICK pin) Example Audio I/F Format : MSB justified (ADC & DAC) PLL Reference clock: BICK BICK frequency: 64fs Sampling Frequency: 8kHz (1) PMPLL bit (Addr:01H, D0) (2) External BICK Input (1) Addr:01H, Data:00H (2) External LRCK Input (2) Stop the external clocks Figure 57. Clock Stopping Sequence (2) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” (2) Stop the external BICK and LRCK clocks MS0420-E-00 2005/09 - 79 - ASAHI KASEI [AK4642EN] 3. PLL Slave (MCKI pin) Example (1) Audio I/F Format: MSB justified (ADC & DAC) PLL Reference clock: MCKI BICK frequency: 64fs Sampling Frequency: 8kHz PMPLL bit (Addr:01H, D0) (1) MCKO bit (1) Addr:01H, Data:00H (Addr:01H, D1) (2) External MCKI Input (2) Stop the external clocks Figure 58. Clock Stopping Sequence (3) <Example> (1) Power down PLL: PMPLL bit = “1” → “0” Stop MCKO output: MCKO bit = “1” → “0” (2) Stop the external master clock. 4. EXT Slave Mode (1) External MCKI Input Example (1) External BICK Input External LRCK Input Audio I/F Format :MSB justified(ADC & DAC) Input MCKI frequency:1024fs Sampling Frequency:8kHz (1) (1) Stop the external clocks Figure 59. Clock Stopping Sequence (4) <Example> (1) Stop the external MCKI, BICK and LRCK clocks. Power down Power supply current can be shut down (typ. 10µA) by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be also shut down (typ. 10µA) by stopping clocks and setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0420-E-00 2005/09 - 80 - ASAHI KASEI [AK4642EN] PACKAGE 32pin QFN (Unit: mm) 5.00 ± 0.10 0.40 ± 0.10 4.75 ± 0.10 24 17 16 4.75 ± 0.10 B 3.5 5.00 ± 0.10 25 32 1 1 3.5 0.50 +0.07 -0.05 32 C0.42 8 A 0.23 Exposed Pad 9 0.85 ± 0.05 0.10 M AB 0.08 C 0.04 0.01+- 0.01 0.20 C Note) The exposed pad on the bottom surface of the package must be open or connected to the grournd. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate MS0420-E-00 2005/09 - 81 - ASAHI KASEI [AK4642EN] MARKING AKM AK4642 XXXXX 1 XXXXX : Date code identifier (5 digits) Revision History Date (YY/MM/DD) 05/09/15 Revision 00 Reason First Edition Page MS0420-E-00 Contents 2005/09 - 82 - ASAHI KASEI [AK4642EN] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0420-E-00 2005/09 - 83 -