LG GM71S4400CLJ-60 1,048,576 words x 4bit cmos dynamic ram Datasheet

GM71C(S)4400C/CL
LG Semicon Co.,Ltd.
1,048,576 WORDS x 4BIT
CMOS DYNAMIC RAM
Description
Features
The GM71C(S)4400C/CL is the new generation
dynamic RAM organized 1,048,576 words x 4 bit.
GM71C(S)4400C/CL has realized higher density,
higher performance and various functions by
utilizing advanced CMOS process technology. The
GM71C(S)4400C/CL offers Fast Page Mode as a
high speed access Mode. Multiplexed address
inputs permit the GM71C(S)4400C/CL to be
packaged in a standard 300mil 20(26) pin plastic
SOJ and standard 300mil 20(26) pin plastic
TSOP II. The package size provides high system
bit densities and is compatible with widely
available automated testing and insertion
equipment. System oriented features include single
power supply of 5V+/-10% tolerance, direct
interfacing capability with high performance logic
families such as Schottky TTL.
* 1,048,576 Words x 4 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
Pin Configuration
20 (26) SOJ
(Unit: ns)
tRAC
tCAC
tRC
tPC
GM71C(S)4400C/CL-60
60
15
110
40
GM71C(S)4400C/CL-70
70
20
130
45
GM71C(S)4400C/CL-80
80
20
150
50
* Low Power
Active : 605/550/495mW (MAX)
Standby : 5.5mW (CMOS level : MAX)
1.1mW (L-version)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Battery Back Up Operation (L-version)
20 (26) TSOP II
I/O1
VSS
I/O1
1
20
VSS
VSS
20
1
I/O2
I/O4
I/O2
2
19
I/O4
I/O4
19
2
I/O2
WE
I/O3
WE
3
18
I/O3
I/O3
18
3
WE
RAS
CAS
A9
I/O1
RAS
4
17
CAS
CAS
17
4
RAS
OE
A9
5
16
OE
OE
16
5
A9
A0
6
15
A8
A0
6
15
A8
A8
15
6
A0
A1
7
14
A7
A1
7
14
A7
A7
14
7
A1
A2
8
13
A6
A2
8
13
A6
A6
13
8
A2
A3
9
12
A5
A3
9
12
A5
A5
12
9
A3
VCC
10
11
A4
VCC
10
11
A4
A4
11
10
VCC
NORMAL TYPE
(Top View)
REVERSE TYPE
(Top View)
1
GM71C(S)4400C/CL
LG Semicon
Pin Description
Pin
Function
Pin
Function
A0-A9
Address Inputs
WE
Read/Write Enable
A0-A9
Refresh Address Inputs
OE
Output Enable
Data Input / Data Output
VCC
Power (+5V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
I/O1-I/O4
Ordering Information
Type No.
Access Time
Package
GM71C(S)4400CJ/CLJ-60
GM71C(S)4400CJ/CLJ-70
GM71C(S)4400CJ/CLJ-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic SOJ
GM71C(S)4400CT/CLT-60
GM71C(S)4400CT/CLT-70
GM71C(S)4400CT/CLT-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic TSOP II
(Normal Type)
GM71C(S)4400CR/CLR-60
GM71C(S)4400CR/CLR-70
GM71C(S)4400CR/CLR-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic TSOP II
(Reverse Type)
Absolute Maximum Ratings*
Symbol
Parameter
Rating
Unit
0 ~ 70
C
TA
Ambient Temperature under Bias
TSTG
Storage Temperature (Plastic)
-55 ~ 125
C
VIN/VOUT
Voltage on any Pin Relative to VSS
-1.0 ~ 7.0
V
VCC
Voltage on VCC Relative to VSS
-1.0 ~ 7.0
V
IOUT
Short Circuit Output Current
50
mA
PD
Power Dissipation
1.0
W
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
2
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.4
-
6.5
V
VIL
Input Low Voltage (I/O Pin)
-1.0
-
0.8
V
VIL
Input Low Voltage (Others)
-2.0
-
0.8
V
GM71C(S)4400C/CL
LG Semicon
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol
Min Max Unit Note
Parameter
VOH
Output Level
Output “H” Level Voltage (IOUT = -5mA)
2.4
VCC
V
VOL
Output Level
Output “L” Level Voltage (IOUT = 4.2mA)
0
0.4
V
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
60ns
-
110
70ns
-
100
80ns
-
90
-
2
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
ICC8
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
RAS-Only Refresh Current
Average Power Supply Current
RAS-Only Refresh Mode
(RAS Cycling, CAS = VIH, tRC = tRC min)
Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V , DOUT=High-Z)
60ns
-
110
70ns
-
100
80ns
-
90
60ns
-
110
70ns
-
100
80ns
-
90
-
CAS-before-RAS Refresh Current
(tRC = tRC min)
mA
1, 2
mA
mA
2
mA
1, 3
1
mA
5
-
200
uA
4, 5
60ns
-
110
70ns
-
100
80ns
-
90
Battery Back Up Current (Standby with CBR Refresh)
(tRC=125us, tRAS<=1us, WE=VIH, CAS=VIL,
OE, Address and DIN=VIH or VIL, DOUT=High-Z)
-
300
uA
4, 5
Standby Current RAS = VIH
CAS = VIL
DOUT = Enable
-
5
mA
1
mA
II(L)
Input Leakage Current
Any Input (0V<=VIN<=7V)
-10
10
uA
IO(L)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=7V)
-10
10
uA
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. L-version.
5. VCC-0.2V<=VIH<=6.5V, 0V<=VIL<=0.2V.
3
GM71C(S)4400C/CL
LG Semicon
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol
Parameter
Min
Max
Unit
Note
CI1
Input Capacitance (Address)
-
5
§Ü
1
CI2
Input Capacitance (Clocks)
-
7
§Ü
1
CI/O
Data Input, Output Capacitance (Data-In, Out)
-
10
§Ü
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 16)
Test Conditions
Input rise and fall times: 5ns
Output load : 2 TTL gate + CL (100§Ü)
Input, output timing reference levels: 0.8V, 2.4V
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Symbol
4
Parameter
tRC
Random Read or Write Cycle Time
tRP
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
110
-
130
-
150
-
ns
RAS Precharge Time
40
-
50
-
60
-
ns
tRAS
RAS Pulse Width
60
10,000
70
10,000
80
10,000
ns
tCAS
CAS Pulse Width
15
10,000
20
10,000
20
10,000
ns
tASR
Row Address Set-up Time
tRAH
Row Address Hold Time
tASC
Column Address Set-up Time
tCAH
0
-
0
-
0
-
ns
10
-
10
-
10
-
ns
0
-
0
-
0
-
ns
Column Address Hold Time
15
-
15
-
15
-
ns
tRCD
RAS to CAS Delay Time
20
45
20
50
20
60
ns
8
tRAD
RAS to Column Address Delay Time
15
30
15
35
15
40
ns
9
tRSH
RAS Hold Time
15
-
20
-
20
-
ns
tCSH
CAS Hold Time
60
-
70
-
80
-
ns
tCRP
CAS to RAS Precharge Time
10
-
10
-
10
-
ns
tODD
OE to DIN Delay Time
15
-
20
-
20
-
ns
tDZO
OE Delay Time from DIN
0
-
0
-
0
-
ns
tDZC
CAS Set-up Time from DIN
0
-
0
-
0
-
ns
tT
Transition Time
(Rise and Fall)
3
50
3
50
3
50
ns
tREF
Refresh Period
-
16
-
16
-
16
ms
Refresh Period (L-version)
-
128
-
128
-
128
ms
7
GM71C(S)4400C/CL
LG Semicon
Read Cycle
Symbol
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
tRAC
Access Time from RAS
-
60
-
70
-
80
ns
2,3,17
tCAC
Access Time from CAS
-
15
-
20
-
20
ns
3, 4,
13, 17
tAA
Access Time from Address
-
30
-
35
-
40
ns
3, 5,
13, 17
tOAC
Access Time from OE
-
15
-
20
-
20
ns
3,17
tRCS
Read Command Setup Time
0
-
0
-
0
-
ns
tRCH
Read Command Hold Time to CAS
0
-
0
-
0
-
ns
18
tRRH
Read Command Hold Time to RAS
0
-
0
-
0
-
ns
18
tRAL
Column Address to RAS Lead Time
30
-
35
-
40
-
ns
tOFF1
Output Buffer Turn-off Time
0
15
0
15
0
15
ns
6
tOFF2
Output Buffer Turn-off Time from OE
0
15
0
15
0
15
ns
6
tCDD
CAS to DIN Delay Time
15
-
20
-
20
-
ns
tOEP
OE Pulse width
15
-
20
-
20
-
ns
Write Cycle
Symbol
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Min Max Min Max Min Max
Unit
Note
10
tWCS
Write Command Setup Time
0
-
0
-
0
-
ns
tWCH
Write Command Hold Time
15
-
15
-
15
-
ns
tWP
Write Command Pulse Width
10
-
10
-
10
-
ns
tRWL
Write Command to RAS Lead Time
15
-
20
-
20
-
ns
tCWL
Write Command to CAS Lead Time
15
-
20
-
20
-
ns
tDS
Data-in Setup Time
0
-
0
-
0
-
ns
11
tDH
Data-in Hold Time
15
-
15
-
15
-
ns
11
5
GM71C(S)4400C/CL
LG Semicon
Read- Modify-Write Cycle
Symbol
Parameter
tRWC
Read-Modify-Write Cycle Time
tRWD
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
150
-
180
-
200
-
ns
RAS to WE Delay Time
80
-
95
-
105
-
ns
10
tCWD
CAS to WE Delay Time
35
-
45
-
45
-
ns
10
tAWD
Column Address to WE Delay Time
50
-
60
-
65
-
ns
10
tOEH
OE Hold Time from WE
15
-
20
-
20
-
ns
Refresh Cycle
Symbol
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Min Max Min Max Min Max
Unit
tCSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
10
-
10
-
10
-
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
10
-
10
-
10
-
ns
tRPC
RAS Precharge to CAS Hold Time
10
-
10
-
10
-
ns
tCPN
CAS Precharge Time in Normal Mode
10
-
10
-
10
-
ns
Note
Fast Page Mode Cycle
Symbol
6
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
tPC
Fast Page Mode Cycle Time
40
-
45
-
50
-
ns
tCP
Fast Page Mode CAS Precharge Time
10
-
10
-
10
-
ns
tRASP
Fast Page Mode RAS Pulse Width
-
100,000
-
100,000
-
100,000
ns
12
tACP
Access Time from CAS Precharge
-
35
-
40
-
45
ns
3,13,17
tRHCP
RAS Hold Time from CAS Precharge
35
-
40
-
45
-
ns
tCPW
Fast Page Mode Read-Modify-Write Cycle
CAS Precharge to WE Delay Time
55
-
65
-
70
-
ns
tPRWC
Fast Page Mode Read-Modify-Write Cycle
Time
80
-
95
-
100
-
ns
10
GM71C(S)4400C/CL
LG Semicon
Test Mode Cycle
Symbol
Parameter
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
tWS
Test Mode WE Setup Time
0
-
0
-
0
-
ns
tWH
Test Mode WE Hold Time
10
-
10
-
10
-
ns
Counter Test Cycle
Symbol
tCPT
Parameter
CAS Precharge Time in Counter Test
Cycle
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400
C/CL-60
C/CL-70
C/CL-80
Unit
Note
Min Max Min Max Min Max
40
-
40
-
40
-
ns
Notes:
1. AC Measurements assume tT = 5ns.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2TTL loads and 100§Ü.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
5. Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
6. tOFF(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
7
LG Semicon
GM71C(S)4400C/CL
10. tWCS, tRWD, tCWD tCPW and tAWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or a read modify write cycle.
12. tRASP defines RAS pulse width in fast page mode cycles.
13. Access time is determined by the longer of tAA or tCAC or tACP.
14. An initial pause of 100us is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.
15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
16. Test mode operation specified in this data sheet is 2-bit test function controlled by control
address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is low level. In order to end this test mode operation, perform a RAS
only refresh cycle or a CAS-before-RAS refresh cycle.
17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for
the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
8
GM71C(S)4400C/CL
LG Semicon
Package Dimension
Unit: Inches (mm)
20 (26) SOJ
0.275(6.99) MAX
0.260(6.60) MIN
0.330(8.38) MIN
0.340(8.64) MAX
0.295(7.49) MIN
0.305(7.75) MAX
0.025(0.63) MIN
0.039(1.00) MAX
0.008(0.20)
0.085(2.16) MIN
0.103(2.61) MAX
0.661(16.80) MIN
0.669(17.00) MAX
0.128(3.25) MIN
0.148(3.76) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.036(0.91) MAX
0.015(0.38) MIN
0.021(0. 53) MAX
20 (26) TSOP II
0.012(0.30) MIN
0.028(0.70) MAX
0.355(9.02) MIN
o
0.371(9.42) MAX
0.292(7.42) MIN
0.308(7.82) MAX
0~8
0.009(0.22) MAX
0.667(16.94) MIN
0.690(17.54) MAX
0.041(1.03) MIN
0.048(1.23) MAX
0.012(0.30) MIN
0.020(0.50) MAX
0.050(1.27)
TYP
0.001(0.03) MIN
0.009(0.23) MAX
23
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