HANBit HDD16M72D9W DDR SDRAM Module 128Mbyte (16Mx72bit), based on 16Mx8, 4Banks 4K Ref., 184Pin-DIMM with Unbuffered ECC Part No. HDD16M72D9W GENERAL DESCRIPTION The HDD16M72D9W is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of nine CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD16M72D9W is a DIMM(Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible. FEATURES • Part Identification HDD16M72D9W – 10A : 100MHz (CL=2) HDD16M72D9W – 13A : 133MHz (CL=2) HDD16M72D9W – 13B : 133MHz (CL=2.5) • Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 15.6us refresh interval (4K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1200 mil, double sided component URL : www.hbe.co.kr REV 1.0 (November.2002) 1 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W PIN ASSIGNMENT PIN Front PIN Back PIN Frontl 1 VREF 2 DQ0 3 VSS 4 DQ1 5 6 32 A5 62 VDDQ 33 DQ24 63 /WE 34 VSS 64 DQ41 35 DQ25 65 /CAS DQS0 36 DQS3 66 DQ2 37 A4 67 7 VDD 38 VDD 68 DQ42 99 DQ7 8 DQ3 39 DQ26 69 DQ43 100 VSS 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 NC 41 A2 71 * /CS2 102 NC 133 DQ31 163 * /CS3 11 VSS 42 VSS 72 DQ48 103 NC 134 CB4 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52 13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 CB1 75 * CK2 106 DQ13 137 CK0 167 *A13 15 VDDQ 46 VDD 76 * /CK2 107 DM1 138 /CK0 168 VDD 16 * CK1 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DM6 17 * /CK1 48 A0 78 DQS6 109 DQ14 140 DM8 170 DQ54 18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6 172 VDDQ 20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 * BA2 144 CB7 174 DQ60 22 VDDQ 23 DQ16 53 KEY 24 DQ17 25 DQS2 26 27 PIN Back PIN Front 93 VSS 124 VSS 154 /RAS 94 DQ4 125 A6 155 DQ45 95 DQ5 126 DQ28 156 VDDQ 96 VDDQ 127 DQ29 157 /CS0 VSS 97 DM0 128 VDDQ 158 * /CS1 DQS5 98 129 DM3 159 DM5 130 A3 160 VSS 131 DQ30 161 DQ46 DQ6 KEY PIN Back 83 DQ56 114 DQ20 175 DQ61 DQ32 84 DQ57 115 *A12 145 VSS 176 VSS 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 A9 57 DQ34 88 DQ59 119 DM2 149 DM4 180 VDDQ 28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0 29 A7 59 BA0 90 NC 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD *These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN PIN DESCRIPTION A0~A11 Address input VDD Power supply(2.5V) BA0~BA1 Bank Select Address VDDQ Power supply for DQs(2.5V) DQ0~DQ63 Data input/output VREF Power supply for reference Serial EEPROM Power supply(3.3) CB0~CB7 Check bit(Data input/output) VSPD DQS0~DQS7 Data Strobe input/output VSS Ground DM0~DM7 Data-in Mask SA0~SA2 Address in EEPROM CK0~CK2,/CK0~/CK2 Clock input SDA Serial data I/O CKE0 Clock enable input SCL Serial clock /CS0 Chip Select input WP Write protection /RAS Row Address strobe VDDIN VDD identification flag /CAS Column Address strobe NC No connection URL : www.hbe.co.kr REV 1.0 (November.2002) 2 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W FUNCTIONAL BLOCK DIAGRAM URL : www.hbe.co.kr REV 1.0 (November.2002) 3 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W PIN FUNCTION DESCRIPTION Pin CK, /CK Name Clock Input Function CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE CKE Clock Enable POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. /CS enables(registered LOW) and disables(registered HIGH) the command decoder. /CS Chip Select All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. A0 ~ A11 Address BA0 ~ BA1 Bank select address /RAS Row address strobe /CAS Columnaddress strobe /WE Write enable DQS0 ~ 7 Data Strobe Addresses are multiplexed on the same pins. Address : A0 ~ A11 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled DM0~7 Input Data Mask on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc. WP Write Protection When WP is “high”, EEPROM Programming will be inhibited and the entire memory will be write-protected. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply DQ Ground. VREF Supply SSTL_2 reference voltage. URL : www.hbe.co.kr REV 1.0 (November.2002) 4 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNTE VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C PD 13.5 W Voltage on any pin relative to Vss Power dissipation Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. mA Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER Supply Voltage I/O Supply Voltage SYMBOL MIN MAX UNIT VDD 2.3 2.7 V VDDQ 2.3 2.7 V NOTE I/O Reference Voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V Input leakage current I LI -2 2 uA Output leakage current I OZ -5 5 uA Output High current (VOUT = 1.95V) I OH -16.8 mA Output Low current (VOUT = 0.35V) I OL 16.8 mA Output High Current(Half strengh driver) IOH -9 mA Output High Current(Half strengh driver) IOL 9 mA 3 Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC le vel of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. URL : www.hbe.co.kr REV 1.0 (November.2002) 5 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W INPUT/OUTPUT Capacitance (VDD = 2.5V, VDDQ = 2.5V, TA = 25° C, F = 1MHZ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) CIN1 49 57 pF Input Capacitance(CKE0) CIN2 42 50 pF Input Capacitance( CS0) CIN3 42 50 pF Input Capacitance( CLK0, CLK1,CLK2 ) CIN4 22 25 pF COUT1 6 8 pF CIN5 6 8 pF Data & DQS input/output Capacitance(DQ0~DQ63) Input Capacitance(DM0~DM8) AC Operating Conditions PARAMETER/ Condition STMBOL MIN VREF + 0.31 MAX UNIT NOTE VREF - 0.31 V 3 Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) 3 Input Differential Voltage, CK and CK inputs VID (AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX (AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and m ust track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a V REF envelope that has been bandwidth limited 20MHz. AC Operating TEST Conditions PARAMETER VALUE UNIT Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 0.5 V/ns Input Levels(VIH/VIL) VREF+0.31/VREF-0.31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit V URL : www.hbe.co.kr REV 1.0 (November.2002) 6 NOTE HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component) PARAMETER DDR200 DDR266A DDR266B -10A -13A -13B SYMBOL MIN MAX MIN MAX MIN UNIT NOTE MAX Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 ns 1,2 120K 45 120K 45 120K /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 15 15 15 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD Clock cycle time CL=2.0 CL=2.5 tCK 1 1 10 1 tCK 12 7.5 12 10 12 ns 12 7.5 12 7.5 12 ns Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Data out high impedence time from CK-/CK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK DQS-in falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS-in falling edge to CK rising hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns 7.5 ns 0.35 1.1 0.9 0.35 1.1 0.9 tCK Power down exit time tPDEX 10 7.5 tXSW 116 95 Exit self refresh to bank active command tXSA 80 75 Exit self refresh to read command tXSR 200 Refresh interval time tREF 15.6 Output DQS valid window tQH - - - - - - tCK DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 7 3 tCK 1.1 Exit self refresh to write command URL : www.hbe.co.kr REV 1.0 (November.2002) 2 ns 75 ns 200 200 Cycle 15.6 15.6 us 1 4 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W Notes : - 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a pre vious write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter ( tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating (V/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate Δ tIS Δ tIH (V/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 I/O Setup/Hold Plateau Derating I/O Input Level Δ tDS Δ tDH (mV) (ps) (ps) ± 280 +50 +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below V REF ± 310mV for a duration of up to 2ns. 9. - Δ tIH 0.3 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. - Δ tIS 0.3 +100 +100 This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. - Input Setup/Hold Slew Rate I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate Δ tDS Δ tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =0/5ns/V. Input S/H slew rate based on larger of AC -AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. t CK is actual to the system clock cycle time. URL : www.hbe.co.kr REV 1.0 (November.2002) 8 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W COMMAND TRUTH TABLE (V=Valid, X=Don’t Care, H=Logic High, L=Logic Low) COMMAND CK E n-1 CKE n /CS /RAS /CAS /WE DM X L L L L X OP code 1,2 X L L L L X OP code 1,2 L L L H X X L H H H X X Register Extended MRS H Register Mode register set H Auto refresh Refresh Entry Self refresh H H L BA 0,1 Exit L H H X X X Bank active & Row Addr. H X L L H H X V H X L H L H X V Read & column address Write & column address A10/ AP Auto precharge L disable Auto precharge H H X L H L Bank selection Precharge All banks Clock suspend or active power down Precharge power down mode H X L H H L X H X L L H L X H X X X L V V V X X X X Entry H L Exit L H Entry H L Exit L H DM H No operation command H H X X X L H H H H X X X L V V V X X H X X X L H H H 3 3 3 Column 4 H (A0 ~ A9) 4 L Column 4 H (A0 ~ A9) Address V L enable Burst Stop X 3 Address eable Auto precharge NOTE Row address Auto precharge disable A11 A9~A0 X V L X H X 4,6 7 X 5 X X X X X V X X X 8 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is select ed. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data -in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. URL : www.hbe.co.kr REV 1.0 (November.2002) 9 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W PACKAGE DIMENSIONS Unit : mm < Front –Side > 133.35 ± 0.20 < Rear –Side > URL : www.hbe.co.kr REV 1.0 (November.2002) 10 HANBit Electronics Co.,Ltd. HANBit HDD16M72D9W ORDERING INFORMATION Part Number Density Org. HDD16M72D9W-10A 128MByte 16M x 72 HDD16M72D9W-13A 128MByte 16M x 72 Package 184PIN DIMM 184PIN Ref. Vcc MODE MAX.frq 4K 2.5V DDR 100MHz/CL2 4K 2.5V DDR 133MHz/CL2 4K 2.5V DDR 133MHz/CL2.5 DIMM HDD16M72D9W-13B 128MByte 16M x 72 184PIN DIMM URL : www.hbe.co.kr REV 1.0 (November.2002) 11 HANBit Electronics Co.,Ltd.