AD AD8092AR-REEL7 Low-cost, high-speed rail-to-rail amplifier Datasheet

a
FEATURES
Low-Cost Single (AD8091), Dual (AD8092)
Voltage Feedback Architecture
Fully Specified at +3 V, +5 V, and ⴞ5 V Supplies
Single-Supply Operation
Output Swings to within 25 mV of Either Rail
Input Voltage Range
–0.2 V to +4 V; VS = +5 V
High-Speed and Fast Settling on +5 V
110 MHz –3 dB Bandwidth (G = +1)
145 V/␮s Slew Rate
50 ns Settling Time to 0.1%
Good Video Specifications (G = +2)
Gain Flatness of 0.1 dB to 20 MHz; RL = 150 ⍀
0.03% Differential Gain Error; R L = 1 k⍀
0.03ⴗ Differential Phase Error; RL = 1 k⍀
Low Distortion
–80 dBc Total Harmonic @ 1 MHz; RL = 100 ⍀
Outstanding Load Drive Capability
Drives 45 mA, 0.5 V from Supply Rails
Drives 50 pF Capacitive Load (G = +1)
Low Power of 4.4 mA/Amplifier
APPLICATIONS
Coaxial Cable Driver
Active Filters
Video Switchers
Professional Cameras
CCD Imaging Systems
CD/DVD
PRODUCT DESCRIPTION
The AD8091 (single) and AD8092 (dual) are low-cost, voltage
feedback, high-speed amplifiers designed to operate on +3 V, +5 V,
or ± 5 V supplies. They have true single-supply capability with
an input voltage range extending 200 mV below the negative rail
and within 1 V of the positive rail.
Despite their low cost, the AD8091/AD8092 provide excellent overall performance and versatility. The output voltage swing extends
to within 25 mV of each rail, providing the maximum output
dynamic range with excellent overdrive recovery. This makes the
AD8091/AD8092 useful for video electronics, such as cameras,
video switchers, or any high-speed portable equipment. Low distortion and fast settling make them ideal for active filter applications.
Low-Cost, High-Speed
Rail-to-Rail Amplifiers
AD8091/AD8092
CONNECTION DIAGRAMS
SOIC-8
(R-8)
NC 1
AD8091
8
NC
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
␮SOIC-8 and SOIC-8
(RM-8, R-8)
OUT1 1
–IN1 2
+IN1 3
–VS 4
AD8092
–
+
–
+
8
+VS
7
OUT
6
–IN2
5
+IN2
SOT23-5
(RT-5)
VOUT 1
AD8091
5 +V
S
–VS 2
+IN 3
4 –IN
The AD8091/AD8092 offer a low-power supply current and
can operate on a single +3 V power supply. These features are
ideally suited for portable and battery-powered applications
where size and power are critical.
The wide bandwidth and fast slew rate make these amplifiers
useful in many general-purpose, high-speed applications where
dual power supplies of up to ± 6 V and single supplies from +3 V
to +12 V are needed.
All of this low-cost performance is offered in an 8-lead SOIC
(AD8091/AD8092), along with a tiny SOT23-5 package
(AD8091) and a µSOIC package (AD8092).
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
25ⴗC, V = +5 V, R = 2 k⍀ to +2.5 V,
AD8091/AD8092–SPECIFICATIONS (@unlessT =otherwise
noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion*
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
S
Conditions
Min
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to +2.5 V,
RF = 806 Ω
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
70
100
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
G = +2, RL = 150 Ω to +2.5 V
RL = 1 kΩ to +2.5 V
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
L
AD8091A/AD8092A
Typ
MHz
MHz
20
145
35
50
MHz
V/µs
MHz
ns
–67
16
850
0.09
0.03
0.19
0.03
–60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
1.7
10
1.4
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ to +2.5 V
TMIN to TMAX
RL = 150 Ω to +2.5 V
TMIN to TMAX
86
76
0.1
98
96
82
78
72
RL = 10 kΩ to +2.5 V
RL = 2 kΩ to +2.5 V
RL = 150 Ω to +2.5 V
VOUT = +0.5 V to +4.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1
0.015 to 4.985
0.100 to 4.900 0.025 to 4.975
0.300 to 4.625 0.200 to 4.800
45
45
80
130
50
3
70
OPERATING TEMPERATURE RANGE
–40
10
25
2.5
3.25
0.75
290
1.4
–0.2 to +4
88
VCM = 0 V to +3.5 V
⌬VS = ± 1 V
Unit
110
50
TMIN to TMAX
Offset Drift
Input Bias Current
Max
4.4
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
kΩ
pF
V
dB
V
V
V
mA
mA
mA
mA
pF
12
5
V
mA
dB
+85
°C
*Refer to TPC 7.
Specifications subject to change without notice.
–2–
REV. A
AD8091/AD8092
SPECIFICATIONS (@ T = 25ⴗC, V = +3 V, R = 2 k⍀ to +1.5 V, unless otherwise noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion*
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
S
L
Conditions
Min
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V,
RF = 402 Ω
G = –1, VO = 2 V Step
G = +1, VO = 1 V p-p
G = –1, VO = 2 V Step
70
90
fC = 5 MHz, VO = 2 V p-p,
G = –1, RL = 100 Ω to +1.5 V
f = 10 kHz
f = 10 kHz
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V
RL = 1 kΩ to +1.5 V
G = +2, VCM = +1 V
RL = 150 Ω to +1.5 V
RL = 1 kΩ to +1.5 V
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
AD8091A/AD8092A
Typ
Max
110
50
MHz
MHz
17
135
65
55
MHz
V/µs
MHz
ns
–47
16
600
dB
nV/√Hz
fA/√Hz
0.11
0.09
%
%
0.24
0.10
–60
Degrees
Degrees
dB
1.6
TMIN to TMAX
Offset Drift
Input Bias Current
10
1.3
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ
TMIN to TMAX
RL = 150 Ω
TMIN to TMAX
80
74
VCM = 0 V to 1.5 V
72
RL = 10 kΩ to +1.5 V
RL = 2 kΩ to +1.5 V
RL = 150 Ω to +1.5 V
VOUT = +0.5 V to +2.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1
0.15
96
94
82
76
∆VS = +0.5 V
68
–40
*Refer to TPC 7.
Specifications subject to change without notice.
–3–
10
25
2.6
3.25
0.8
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
290
1.4
–0.2 to +2.0
88
kΩ
pF
V
dB
0.01 to 2.99
0.02 to 2.98
0.125 to 2.875
45
45
60
90
45
V
V
V
mA
mA
mA
mA
pF
3
OPERATING TEMPERATURE RANGE
REV. A
0.075 to 2.9
0.20 to 2.75
Unit
4.2
80
12
4.8
V
mA
dB
+85
°C
25ⴗC, V = ⴞ5 V, R = 2 k⍀ to Ground,
AD8091/AD8092–SPECIFICATIONS (@unlessT =otherwise
noted.)
A
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
S
Conditions
Min
G = +1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω,
RF = 1.1 kΩ
G = –1, VO = 2 V Step
G = +1, VO = 2 V p-p
G = –1, VO = 2 V Step
70
105
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
f = 5 MHz, G = +2
DC PERFORMANCE
Input Offset Voltage
L
AD8091A/AD8092A
Typ
Max
110
50
MHz
MHz
20
170
40
50
MHz
V/µs
MHz
ns
–71
16
900
0.02
0.02
0.11
0.02
–60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
1.8
TMIN to TMAX
Offset Drift
Input Bias Current
10
1.4
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
RL = 2 kΩ
TMIN to TMAX
RL = 150 Ω
TMIN to TMAX
88
78
0.1
96
96
82
80
72
RL = 10 kΩ
RL = 2 kΩ
RL = 150 Ω
VOUT = –4.5 V to +4.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1 (AD8091/AD8092)
–4.98 to +4.98
–4.85 to +4.85 –4.97 to +4.97
–4.45 to +4.30 –4.60 to +4.60
45
45
100
160
50
3
68
OPERATING TEMPERATURE RANGE
–40
11
27
2.6
3.5
0.75
290
1.4
–5.2 to +4.0
88
VCM = –5 V to +3.5 V
∆VS = ± 1 V
Unit
4.8
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
kΩ
pF
V
dB
V
V
V
mA
mA
mA
mA
pF
12
5.5
V
mA
dB
+85
°C
Specifications subject to change without notice.
–4–
REV. A
AD8091/AD8092
RMS output voltages should be considered. (If RL is referenced
to VS–, as in single-supply operation, then the total drive power is
VS ⫻ IOUT.)
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . ± VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 2.5 V
Output Short Circuit Duration . . . . . . . . . . . . . See Figure 1
Storage Temperature Range . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300°C
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS /4 for RL to midsupply:
VS 
 4
 
PD = (VS × IS ) +
RL
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(In single-supply operation with RL referenced to VS–, worst case is
VOUT = VS /2.)
Airflow will increase heat dissipation, effectively reducing ␪JA. Also,
more metal directly in contact with the package leads from metal
traces, through holes, ground, and power planes will reduce the ␪JA.
Care must be taken to minimize parasitic capacitances at the input
leads of high-speed op amps as discussed in the board layout
section.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic will change its properties.
Even temporarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting the
parametric performance of the AD8091/AD8092. Exceeding a
junction temperature of 175°C for an extended period of time can
result in changes in the silicon devices, potentially causing failure.
Figure 1 shows the maximum safe power dissipation in the package
versus the ambient temperature for the SOIC-8 (125°C/W),
SOT23-5 (180°C/W), and µSOIC-8 (150°C/W) packages on a
JEDEC standard four-layer board.
2.0
TJ = 150ⴗC
MAXIMUM POWER DISSIPATION – W
The still-air thermal properties of the package (␪JA), ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as follows:
TJ = TA + (PD × θ JA )
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (VS) times the quiescent current
(IS). Assuming the load (RL) is referenced to midsupply, then the
total drive power is VS /2 ⫻ IOUT, some of which is dissipated in
the package and some in the load (VOUT ⫻ IOUT). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
1.5
SOIC-8
␮SOIC-8
1.0
SOT23-5
0.5
0
–40 –30 –20 –10
0 10 20 30 40 50 60
AMBIENT TEMPERATURE – ⴗC
70
80
90
Figure 1. Maximum Power Dissipation vs. Temperature
for a Four-Layer Board
PD = quiescent power + (total drive power – load power)
2
V
 V
V
PD = (VS × IS ) +  S × OUT  –  OUT 
RL   RL 
 2
REV. A
2
–5–
AD8091/AD8092
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Outline
AD8091AR
AD8091AR-REEL
AD8091AR-REEL7
AD8091ART-REEL
AD8091ART-REEL7
AD8092AR
AD8092AR-REEL
AD8092AR-REEL7
AD8092ARM
AD8092ARM-REEL
AD8092ARM-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
5-Lead SOT-23
5-Lead SOT-23
8-Lead SOIC
8-Lead SOIC
8-Lead SOIC
8-Lead µSOIC
8-Lead µSOIC
8-Lead µSOIC
SO-8
13" Tape and Reel
7" Tape and Reel
RT-5, 13" Tape and Reel
RT-5, 7" Tape and Reel
SO-8
13" Tape and Reel
7" Tape and Reel
RM-8
13" Tape and Reel
7" Tape and Reel
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8091/AD8092 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–6–
Branding
Information
HVA
HVA
HWA
HWA
HWA
WARNING!
ESD SENSITIVE DEVICE
REV. A
Typical Performance Characteristics–AD8091/AD8092
6.3
3
2
0
6.1
G = +5
RF = 2k⍀
–1
G = +1
RF = 0
G = +10
RF = 2k⍀
–2
GAIN FLATNESS – dB
1
NORMALIZED GAIN – dB
6.2
G = +2
RF = 2k⍀
–3
–4
VS = +5V
GAIN AS SHOWN
RF AS SHOWN
RL = 2k⍀
VO = 0.2V p-p
–5
–6
–7
0.1
1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
10
FREQUENCY – MHz
100
5.3
0.1
500
TPC 1. Normalized Gain vs. Frequency; VS = +5 V
1
10
FREQUENCY – MHz
100
TPC 4. 0.1 dB Gain Flatness vs. Frequency; G = +2
3
9
2
VS = +5V
VO = 2V p-p
8
VS = +3V
VS = +5V
1
7
0
6
5
GAIN – dB
VS = ⴞ5V
–1
GAIN – dB
VS = +5V
G = +2
RL = 150⍀
RF = 806⍀
VO = 0.2V p-p
–2
–3
4
–4
2
VS AS SHOWN
G = +1
RL = 2k⍀
VO = 0.2V p-p
–5
–6
–7
0.1
1
1
0
10
FREQUENCY – MHz
100
VS AS SHOWN
G = +2
RL = 2k⍀
RF = 2k⍀
VO AS SHOWN
–1
0.1
500
TPC 2. Gain vs. Frequency vs. Supply
VS = ⴞ5V
VO = 4V p-p
3
1
10
FREQUENCY – MHz
100
500
TPC 5. Large Signal Frequency Response; G = +2
3
70
2
VS = +5V
RL = 2k⍀
60
–40ⴗC
1
GAIN – dB
+85ⴗC
+25ⴗC
–1
–2
–3
–4
–5
–6
–7
0.1
VS = +5V
G = +1
RL = 2k⍀
VO = 0.2V p-p
TEMPERATURE AS SHOWN
1
10
FREQUENCY – MHz
30
GAIN
0
–45
20
PHASE
10
–90
–135
0
–10
100
–20
0.1
500
TPC 3. Gain vs. Frequency vs. Temperature
REV. A
40
PHASE – Degrees
OPEN-LOOP GAIN – dB
50
0
–180
50ⴗ PHASE
MARGIN
1
10
FREQUENCY – MHz
100
500
TPC 6. Open-Loop Gain and Phase vs. Frequency
–7–
AD8091/AD8092
ⴚ30
DIFFERENTIAL
GAIN ERROR – %
VS = +3V, G = ⴚ1
RF = 2k⍀, RL = 100⍀
VO = 2V p-p
VS = +5V, G = +2
RF = 2k⍀, RL = 100⍀
VS = +5V, G = +1
RL = 100⍀
ⴚ40
ⴚ50
ⴚ60
DIFFERENTIAL
PHASE ERROR – Degrees
TOTAL HARMONIC DISTORTION – dBc
ⴚ20
ⴚ70
VS = +5V, G = +1
RL = 2k⍀
ⴚ80
VS = +5V, G = +2
RF = 2k⍀, RL = 2k⍀
ⴚ90
ⴚ100
ⴚ110
1
2
3
4
5
6 7
FUNDAMENTAL FREQUENCY – MHz
8 9 10
0.10
0.08
0.06
0.04
0.02
0.00
ⴚ0.02
ⴚ0.04
ⴚ0.06
ⴚ0.15
ⴚ0.20
ⴚ0.25
20
30
40
50
60
70
80
90
100
90
100
RL = 1k⍀
RL = 150⍀
VS = +5, G = +2
RF = 2k⍀, RL AS SHOWN
0
10
20
30
40
50
60
70
80
MODULATING RAMP LEVEL – IRE
1000
VS = +5V
VOLTAGE NOISE – nA Hz
10MHz
ⴚ50
ⴚ60
ⴚ70
ⴚ80
5MHz
ⴚ90
1MHz
ⴚ100
ⴚ110
100
10
VS = +5V
RL = 2k⍀
G = +2
ⴚ120
0
0.5
1.0
1.5
2.0 2.5
3.0 3.5
OUTPUT VOLTAGE – V p-p
4.0
4.5
1
10
5.0
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 8. Worst Harmonic vs. Output Voltage
TPC 11. Input Voltage Noise vs. Frequency
5.0
100
4.5
4.0
VS = +5V
VS = +5V
G = –1
RF = 2k⍀
RL = 2k⍀
CURRENT NOISE – pA Hz
WORST HARMONIC – dBc
10
ⴚ0.05
ⴚ0.10
ⴚ40
0.5%) – V p-p
0
TPC 10. Differential Gain and Phase Errors
ⴚ30
3.5
OUTPUT VOLTAGE SWING (THD
RL = 1k⍀
VS = +5, G = +2
RF = 2k⍀, RL AS SHOWN
0.10
0.05
0.00
TPC 7. Total Harmonic Distortion
ⴚ130
RL = 150⍀
NTSC SUBSCRIBER (3.58MHz)
3.0
2.5
2.0
1.5
1.0
10
1
0.5
0
0.1
1
FREQUENCY – MHz
10
0.1
10
50
TPC 9. Low Distortion Rail-to-Rail Output Swing
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 12. Input Current Noise vs. Frequency
–8–
REV. A
AD8091/AD8092
–10
–20
VS = +5V
10
0
–10
–40
PSRR – dB
CROSSTALK – dB
–30
20
VS = +5V
RF = 2k⍀
RL = 2k⍀
VO = 2V p-p
–50
–60
–70
–PSRR
–20
–30
+PSRR
–40
–50
–80
–60
–90
–70
–100
0.1
1
10
FREQUENCY – MHz
100
–80
0.01
500
TPC 13. AD8092 Crosstalk (Output-to-Output) vs. Frequency
SETTLING TIME TO 0.1% ⴚ ns
CMRR – dB
–40
–50
–60
–70
–80
50
40
30
20
10
–90
0.1
1
10
FREQUENCY – MHz
100
0
0.5
500
TPC 14. CMRR vs. Frequency
VS = +5V
3.1
1
0.31
0.1
0.031
0.90
0.80
VOH = +85ⴗC
VOH = +25ⴗC
0.70
VOH = –40ⴗC
VOL = +85ⴗC
0.60
0.50
0.40
0.30
VOL = +25ⴗC
0.20
VOL = –40ⴗC
0.10
0
1
10
FREQUENCY – MHz
100
0
500
TPC 15. Closed-Loop Output Resistance vs. Frequency
REV. A
2.0
1.00
VS = +5V
G = +1
10.0
0.01
0.1
1.0
1.5
INPUT STEPS – V p-p
TPC 17. Settling Time vs. Input Step
OUTPUT SATURATION VOLTAGE – V
OUTPUT RESISTANCE – ⍀
31.0
500
VS = +5V
G = –1
RL = 2k⍀
60
–30
100.0
100
70
VS = +5V
–20
–100
0.03
1
10
FREQUENCY – MHz
TPC 16. PSRR vs. Frequency
0
–10
0.1
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT – mA
TPC 18. Output Saturation Voltage vs. Load Current
–9–
AD8091/AD8092
100
OPEN-LOOP GAIN – dB
RL = 2k⍀
90
3.5V
RL = 150⍀
2.5V
80
1.5V
70
VS = +5V
60
0
0.5
1.0
2.5 2.5
1.5
3.0 3.5
OUTPUT VOLTAGE – V
4
4.5
5
TPC 19. Open-Loop Gain vs. Output Voltage
TPC 22. Large Signal Step Response; VS = +5 V, G = +2
5V
1.50V
2.5V
TPC 23. Output Swing; G = –1, RL = 2 kΩ
TPC 20. 100 mV Step Response; G = +1
4V
3V
2V
2.60V
1V
2.50V
ⴚ1V
ⴚ2V
2.40V
ⴚ3V
ⴚ4V
20ns
TPC 24. Large Signal Step Response; VS = ± 5 V, G = +1
TPC 21. 200 mV Step Response; VS = +5 V, G = +1
–10–
REV. A
AD8091/AD8092
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Input-to-Output Coupling
Power supply pins are actually inputs and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply to
ground at all frequencies, thereby shunting or filtering a majority
of the noise.
Decoupling schemes are designed to minimize the bypassing impedance at all frequencies with a parallel combination of capacitors.
0.01 µF or 0.001 µF (X7R or NPO) chip capacitors are critical
and should be as close as possible to the amplifier package. Larger
chip capacitors, such as the 0.1 µF capacitor, can be shared among
a few closely spaced active components in the same signal path.
A 10 µF tantalum capacitor is less critical for high-frequency
bypassing and, in most cases, only one per board is needed at
the supply inputs.
The input and output signal traces should not be parallel to minimize capacitive coupling between the inputs and output, avoiding
any positive feedback.
DRIVING CAPACITIVE LOADS
A highly capacitive load will react with the output of the amplifiers,
causing a loss in phase margin and subsequent peaking or even
oscillation, as illustrated in Figures 2 and 3. There are two
methods to effectively minimize its effect.
1. Put a small value resistor in series with the output to isolate
the load capacitor from the amps’ output stage.
2. Increase the phase margin with higher noise gains or by adding a
pole with a parallel resistor and capacitor from –IN to the output.
8
6
Grounding
4
The length of the high-frequency bypass capacitor leads are most
critical. A parasitic inductance in the bypass grounding will work
against the low impedance created by the bypass capacitor. Place
the ground leads of the bypass capacitors at the same physical
location. Because load currents flow from the supplies as well,
the ground for the load impedance should be at the same physical
location as the bypass capacitor grounds. For the larger value
capacitors, which are intended to be effective at lower frequencies,
the current return path distance is less critical.
0
ⴚ2
ⴚ4
VS = +5V
G = +1
RL = 2k⍀
CL = 50pF
VO = 200mV p-p
ⴚ6
ⴚ8
ⴚ10
0.1
1
10
FREQUENCY – MHz
100
500
Figure 2. Closed-Loop Frequency Response: CL = 50 pF
p
2.60V
Input Capacitance
Along with bypassing and ground, high-speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance will reduce the input impedance at high
frequencies, in turn increasing the amplifier’s gain, causing peaking
of the frequency response or even oscillations, if severe enough.
It is recommended that the external passive components, which
are connected to the input pins, be placed as close as possible to
the inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a distance of at least 0.05 mm from the
input pins on all layers of the board.
REV. A
2
GAIN – dB
A ground plane layer is important in densely packed PC boards to
spread the current minimizing parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high-speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high-frequency impedance of
the path. High-speed currents in an inductive ground return will
create an unwanted voltage noise.
–11–
2.55V
2.50V
2.45V
2.40V
Figure 3. 200 mV Step Response: CL = 50 pF
AD8091/AD8092
As the closed-loop gain is increased, the larger phase margin allows
for large capacitor loads with less peaking. Adding a low value resistor in series with the load at lower gains has the same effect. Figure 4
shows the effect of a series resistor for various voltage gains. For
large capacitive loads, the frequency response of the amplifier
will be dominated by the series resistor and capacitive load.
10000
CAPACITIVE LOAD ⴚ PF
VS = 5V
30%
OVERSHOOT
RS = 3⍀
1000
Active Filters
Active filters at higher frequencies require wider bandwidth op amps
to work effectively. Excessive phase shift produced by lower
frequency op amps can significantly impact active filter performance.
Figure 6 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps. Such circuits are sometimes used in
medical ultrasound systems to lower the noise bandwidth of the
analog signal before A/D conversion. Please note that the
unused amplifiers’ inputs should be tied to ground.
RS = 0⍀
R6
1k⍀
C1
50pF
100
RG
RF
VIN
100mV STEP
50⍀
10
R2
2k⍀
RS
VOUT
VIN
CL
R1
3k⍀
R4
2k⍀
2
1
R3
2k⍀
C2
50pF
6
7
3
R5
2k⍀ 2
6
5
1
AD8092
1
2
3
4
AC L – V / V
5
3
AD8092
6
AD8091
Figure 6. 2 MHz Biquad Band-Pass Filter
Figure 4. Capacitive Load Drive vs. Closed-Loop Gain
Overdrive Recovery
VOUT
The frequency response of the circuit is shown in Figure 7.
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive condition. As shown in Figure 5, the AD8091/AD8092
recovers within 60 ns from negative overdrive and within 45 ns
from positive overdrive.
0
GAIN – dB
ⴚ10
ⴚ20
ⴚ30
ⴚ40
10k
100k
1M
FREQUENCY – Hz
10M
100M
Figure 7. Frequency Response of 2 MHz Band-Pass
Biquad Filter
Sync Stripper
Figure 5. Overdrive Recovery
Synchronizing pulses are sometimes carried on video signals so as
not to require a separate channel to carry the synchronizing information. However, for some functions, such as A/D conversion, it
is not desirable to have the sync pulses on the video signal. These
–12–
REV. A
AD8091/AD8092
pulses will reduce the dynamic range of the video signal and do
not provide any useful information for such a function.
A sync stripper will remove the synchronizing pulses from a video
signal while passing all the useful video information. Figure 8 shows
a practical single-supply circuit that uses only a single AD8091.
It is capable of directly driving a reverse terminated video line.
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
VBLANK
GROUND
+3V OR +5V
0.1␮F
+
10␮F
VIN
Some circuits use a sync tip clamp to hold the sync tips at a relatively constant level to lower the amount of dynamic signal swing
required. However, these circuits can have artifacts like sync tip
compression unless they are driven by a source with a very low
output impedance. The AD8091/AD8092 have adequate signal
swing when running on a single +5 V supply to handle an ac-coupled
composite video signal.
TO A/D
AD8091
The other extreme is a full white video signal. The blanking intervals
and sync tips of such a signal will have negative-going excursions
in compliance with the composite video specifications. The
combination of horizontal and vertical blanking intervals limit
such a signal to being at the highest (white) level for a maximum of
about 75% of the time.
As a result of the duty cycles between the two extremes presented
above, a 1 V p-p composite video signal that is multiplied by a
gain of 2 requires about 3.2 V p-p of dynamic voltage swing at the
output for an op amp to pass a composite video signal of arbitrary
varying duty cycle without distortion.
GROUND
+0.4V
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
100⍀
R2
1k⍀
R1
1k⍀
+0.8V
(OR 2 ⴛ VBLANK)
The input to the circuit in Figure 9 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac-coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
Figure 8. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to 2
via the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 for the input signal to have the sync pulses
stripped at the proper level.
+5V
4.99k⍀
4.99k⍀
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by 2 by
the amplifier. This level must be at ground at the output in
order for the sync stripping action to take place. Since the gain of
the amplifier from the input of R1 to the output is –1, a voltage
equal to 2 ⫻ VBLANK must be applied to make the blanking level
come out at ground.
COMPOSITE
47␮F
VIDEO
+
IN
RT
10k⍀
75⍀
10␮F
0.1␮F
+
10␮F
1000␮F
+
AD8091
RBT
75⍀
RL
75⍀
RF
1k⍀
VOUT
0.1␮F
RG
1k⍀
Single-Supply Composite Video Line Driver
220␮F
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
may arise from such techniques.
Figure 9. Single-Supply Composite Video Line Driver
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst case,
the dynamic signal swing will approach twice the peak-to-peak
value. The two conditions that define the maximum dynamic
swing requirements are a signal that is mostly low but goes high
with a duty cycle that is a small fraction of a percent. The opposite condition defines the other extreme.
REV. A
+
The feedback circuit provides unity gain for the dc biasing of the
input and provides a gain of 2 for any signals that are in the video
bandwidth. The output is ac-coupled and terminated to drive
the line.
The capacitor values were selected for providing minimum “tilt”
or field time distortion of the video signal. These values would be
required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as “consumer video,” is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of 5 with minimum visible degradation in the picture.
–13–
AD8091/AD8092
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches)
Dimensions shown in inches and (mm)
8-Lead SOIC
(R-8)
8-Lead ␮SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
1
4
5
8
6.20 (0.2440)
5.80 (0.2284)
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
4
PIN 1
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
SEATING
PLANE
PIN 1
2.59 (0.102)
2.39 (0.094)
0.49 (0.0192)
0.35 (0.0138)
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE
FOR USE IN DESIGN
0.011 (0.28)
0.003 (0.08)
33°
27°
0.028 (0.71)
0.016 (0.41)
Dimensions shown in mm and (inches)
5-Lead Plastic Surface Mount
(RT-5)
3.10 (0.122)
2.70 (0.106)
1.80 (0.071)
1.50 (0.059)
5
1
4
2
3.00 (0.118)
2.50 (0.098)
3
PIN 1
0.95 (0.037) REF
1.90 (0.075)
REF
1.30 (0.051)
0.90 (0.035)
0.15 (0.059)
0.00 (0.000)
0.20 (0.008)
0.09 (0.004)
1.45 (0.057)
0.90 (0.035)
0.50 (0.020)
0.30 (0.012)
SEATING
PLANE
10
0
0.60 (0.024)
0.10 (0.004)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR
USE IN DESIGN
–14–
REV. A
AD8091/AD8092
Revision History
Location
Page
5/02–Data Sheet changed from REV. 0 to REV. A.
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edit to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to TPCs 21–24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
REV. A
–15–
–16–
PRINTED IN U.S.A.
C02859–0–5/02(A)