A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Features and Benefits Description ▪ 2.5 to 9 V operation ▪ Internal PWM current limit control ▪ Synchronous rectification for reduced power dissipation ▪ Peak current output flag ▪ Undervoltage lockout ▪ Low RDS(on) outputs ▪ Small package ▪ Brake mode for DC motors ▪ Sleep function ▪ Crossover-current protection ▪ Thermal shutdown Designed for pulse width modulated (PWM) control of low voltage stepper motors, and single and dual DC motors, the A3906 is capable of output currents up to 1 A per channel and operating voltages from 2.5 to 9 V. The A3906 has an internal fixed off-time PWM timer that sets a peak current based on the selection of a current sense resistor. An overcurrent output flag is provided that notifies the user when the current in the motor winding reaches the peak current determined by the sense resistor. The fault output does not affect driver operation. The A3906 is provided in a 20-contact, 4 mm × 4 mm, 0.75 mm nominal overall height QFN, with exposed pad for enhanced thermal dissipation. It is lead (Pb) free, with 100% matte tin leadframe plating. Package: 20-contact QFN (suffix ES) Applications include the following: ▪ Digital still cameras (DSC) ▪ Cell phone cameras ▪ USB powered devices ▪ Battery powered devices Approximate size Typical Applications 0.1 μF 0.1 μF CP1 CP2 CP3 CP4 CP1 VCP 0.1 μF 0.1 μF CP2 CP4 CP3 VCP 0.1 μF SLEEP A3906 A3906 IN2 M OUT1B IN4 +5 V SENSE1 VBB 10 μF 10 V IN1 OUT1A IN3 +5 V SLEEP 10 μF 10 V IN1 IN2 0.1 μF VBB OUT1A IN3 OUT1B IN4 SENSE1 M OUT2A M FL1 OUT2B FL2 GND SENSE2 Dual DC motor application 3906-DS, Rev. 4 OUT2A FL1 OUT2B FL2 SENSE2 GND Stepper motor application A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Selection Guide Part Number Packing A3906SESTR-T Package 1500 pieces per 7-in. reel 20-pin QFN with exposed thermal pad Absolute Maximum Ratings Characteristic Symbol Load Supply Voltage VBB Logic Input Voltage Range VIN Sense Voltage VSENSEx Output Current IOUT Output Current in Paralleled Operation IOUT(par) Operating Temperature Range TA Junction Temperature Notes Continuous Pulsed, tw < 1 μs May be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Continuous Peak, DC < 30% Continuous Peak, DC < 30% Range S Rating Units 9.6 V –0.3 to 7 V 0.5 V 1 V 1 A 1.5 A 2 A 2.5 A –20 to 85 °C TJ(max) 150 °C Tstg –40 to 150 °C Storage Temperature Range Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Symbol RθJA Package Thermal Resistance Test Conditions* Value Units 4-layer PCB based on JEDEC standard 37 ºC/W *Additional thermal information available on the Allegro website. Terminal List Table 16 OUT1A 17 VCP 18 CP3 19 CP1 20 CP4 Pin-out Diagram CP2 1 15 SENSE1 GND 2 14 OUT1B SLEEP 3 13 VBB IN1 4 12 OUT2B IN2 5 11 SENSE2 7 8 9 IN4 FL1 FL2 OUT2A 10 6 IN3 PAD Number 1 2 3 4 5 Name CP2 GND SLEEP IN1 IN2 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 – IN3 IN4 FL1 FL2 OUT2A SENSE2 OUT2B VBB OUT1B SENSE1 OUT1A VCP CP3 CP1 CP4 PAD Function Charge pump capacitor terminal 2 Ground Sleep logic input, active low Control input Control input Control input Control input Current limit flag, bridge 1 Current limit flag bridge 2 DMOS full-bridge 2, output A Current sense resistor terminal, bridge 2 DMOS full-bridge 2, output B Supply Voltage DMOS full-bridge 1, output B Current sense resistor terminal, bridge 1 DMOS full-bridge 1, output A Reservoir capacitor terminal Charge pump capacitor terminal 3 Charge pump capacitor terminal 1 Charge pump capacitor terminal 4 Exposed pad for enhanced thermal performance Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Functional Block Diagram 0.1 μF 0.1 μF 10 μF 10 V CP4 CP3 CP2 CP1 VCP 0.1 μF VBB VCP Charge Pump VBB GND Regulator +5 V +5 V OUT1A Sense1 Sense2 OUT1B SLEEP Sense1 SENSE1 FL1 FL2 PWM Latch and Blanking Comparator Bridge 2 VBB IN1 IN2 RS1 VCP PWM Latch and Blanking Comparator Bridge 1 OUT2A OUT2B Control Logic IN3 IN4 Sense2 SENSE2 RS2 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver ELECTRICAL CHARACTERISTICS1,2 valid at TA = 25°C and VBB = 2.5 to 9 V, unless otherwise noted Characteristics Symbol Operating Voltage Range VBB VBB Supply Current IBB Output Resistance RDS(on) Current Trip Sense Voltage VSENSE Test Conditions Output Leakage Current Vf IDSS Typ. Max. Units 2.5 – 9 V IOUT = 0 mA, PWM = 50 kHz, Duty Cycle = 50% – 5 – mA IOUT = 0 mA, outputs disabled, VBB = 9.6 V – 3 – mA Sleep mode, VIN < 0.4 V – 150 500 nA Source driver, IOUT = 400 mA , VBB = 3 V, TJ = 25°C – 0.52 0.60 Ω Source driver, IOUT = 400 mA , VBB = 3 V, TJ = 85°C – 0.78 – Ω Sink driver, IOUT = 400 mA, VBB = 3 V, TJ= 25°C – 0.62 0.74 Ω Sink driver, IOUT = 400 mA, VBB = 3 V, TJ= 85°C Clamp Diode Voltage Min. FLx falling edge I = 400 mA Outputs, VOUT = 9 V – 0.93 – Ω 160 200 240 mV – – 1 V –20 – 20 μA Control Logic Logic Input Voltage Logic Input Current Input Hysteresis S̄¯L̄¯Ē¯Ē¯P̄¯ Input VIN(1) 2.0 – 5.5 V VIN(0) – – 0.8 V IIN(1) VIN = 5.5 V – <100 500 nA IIN(0) VIN = 0.8 V – <–100 –500 nA VINhys – 150 – mV VSLEEP(0) – – 0.4 V VSLEEP(1) 2 – – V Fault Output VFLx Flag asserted, IFLx = 1 mA – – 200 mV Fault Output Leakage Current IFLx VFLx = 5 V – – 1 μA tFLx Reset of PWM latch – 300 – μs 2.1 3 3.9 μs Fault Output Timer Blank Time Fixed Off-Time Propagation Delay Time tBLANK – 30 – μs tpd(on) tOFF Input high to source on, input low to source off 100 235 350 ns tpd(off) Input low to sink off, input high to sink on 50 100 200 ns Protection Circuitry Crossover Delay tCOD 200 425 650 ns 2.2 2.31 2.45 V VBBUVHYS 200 300 400 mV TJTSD – 165 – °C TJTSDHYS – 15 – °C VBB Undervoltage Lockout Threshold VBBUVLO VBB Undervoltage Lockout Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis VBB rising 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2Specifications over the operating temperature range are assured by design and characterization. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Fault Timing Diagram ITRIP ILOAD tFLx Fault Asserted FLx tFLx Fault Asserted Fault Asserted NOTE: Timer resets after each reset of the PWM latch. Control Logic DC Motor Operation IN1 IN2 IN3 IN4 OUT1A OUT1B OUT2A OUT2B Function 0 0 0 0 Off Off Off Off Disabled 1 0 1 0 High Low High Low Forward 0 1 0 1 Low High Low High Reverse 1 1 1 1 Low Low Low Low Brake Stepper Motor Operation IN1 IN2 IN3 IN4 OUT1A OUT1B OUT2A OUT2B 0 0 0 0 Off Off Off Off Disabled Function Disabled 1 0 1 0 High Low High Low Full Step 1 ½ Step 1 0 0 1 0 Off Off High Low – ½ Step 2 0 1 1 0 Low High High Low Full Step 2 ½ Step 3 0 1 0 0 Low High Off Off – ½ Step 4 0 1 0 1 Low High Low High Full Step 3 ½ Step 5 0 0 0 1 Off Off Low High – ½ Step 6 1 0 0 1 High Low Low High Full Step 4 ½ Step 7 1 0 0 0 High Low Off Off – ½ Step 8 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Functional Description Device Operation The A3906 is a dual full-bridge low voltage motor driver capable of operating one stepper motor, two DC motors, or one high current DC motor. MOSFET output stages substantially reduce the voltage drop and the power dissipation of the outputs of the A3906, compared to typical drivers with bipolar transistors. pump is used to create a supply voltage greater than VBB , to drive the source-side DMOS gates. For pumping purposes, a 0.1 μF ceramic capacitor should be connected between CP1 and CP2, and between CP3 and CP4. A 0.1 uF ceramic capacitor is required between VCP and VBB, to act as a reservoir to operate the highside DMOS devices. Output current can be regulated by pulse width modulating (PWM) the inputs. In addition supporting external PWM of the driver, the A3906 limits the peak current by internally PWMing the source driver when the current in the winding exceeds the peak current, which is determined by a sense resistor. A fault output notifies the user that peak current was reached. If internal current limiting is not needed, the sense pin should be shorted to ground. Thermal Shutdown The A3906 will disable the outputs if the junction temperature reaches 165°C. When the junction temperature drops 15°C, the outputs will be enabled. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout, internal clamp diodes, and crossover current protection. The A3906 is designed for portable applications, providing a power-off low current sleep mode and an operating voltage of 2.5 to 9 V. External PWM Output current regulation can be achieved by pulse width modulating the inputs. Slow decay mode is selected by holding one input high while PWMing the other input. Holding one input low and PWMing the other input results in fast decay. Refer to the Applications Information section for further information. Blanking This function blanks the output of the current sense comparator when the outputs are switched. The comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of the clamp diodes or to switching transients related to the capacitance of the load. The blank time, tBLANK , is approximately 3 μs. Sleep Mode An active-low control input used to minimize power consumption when the A3906 is not in use. This disables much of the internal circuitry including the output drivers, internal regulator, and charge pump. A logic high allows normal operation. When coming out of sleep mode, wait 1.5 ms before issuing a command, to allow the internal regulator and charge pump to stabilize. Enable When all logic inputs are pulled to logic low, the outputs of the bridges are disabled. The charge pump and internal circuitry continue to run when the outputs are disabled. Charge Pump (CP1, CP2, CP3, and CP4) When supply voltages are lower than 3.5 V, the two-stage charge pump triples the input voltage to a maximum of 7 V above the supply. The charge Brake Mode When driving DC motors, the A3906 goes into brake mode (turns on both sink drivers) when both of its inputs are high (IN1 and IN2, or IN3 and IN4). There is no protection during braking, so care must be taken to ensure that the peak current during braking does not exceed the absolute maximum current. Internal PWM Current Control Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink DMOS outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the internal reference voltage, the current sense comparator resets the PWM latch, which turns off the source driver. The maximum value of current limiting, ITRIP(max) , is set by the selection of the sense resistor, RSx, and is approximated by a transconductance function: ITRIP(max) = 0.2 / RS . It is critical to ensure the maximum rating on SENSEx pins (0.5 V) is not exceeded. Synchronous Rectification When a PWM off-cycle is triggered by an internal fixed off-time cycle, load current recirculates in slow decay SR mode. During slow decay, current recirculates through the sink-side FET and the sink-side body diode. The SR feature enables the sink-side FET, effectively shorting out the body diode. The sink driver is not enabled until the source driver is turned off and the crossover delay has expired. This feature helps lower the voltage drop during current recirculation, lowering power dissipation in the bridge. Overcurrent Output Flag When the peak current (set by the external resistor) is reached, the fault pin, FLx, is pulled low. When a reset of the PWM latch occurs, the fault timer begins. At each PWM latch reset, the timer is reset to zero. After approximately 300 μs, if no peak current event was triggered, the timer expires and the fault is released. This ensures that during PWM current limiting, the fault pin remains in a fault state. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver Applications Information External PWM If external PWM is used, the internal current control can either be disabled by shorting the SENSEx pin to ground, or it can be used to limit the peak current to a value under the stall current to prevent motor heating. External PWM IN1 control is shown in the upper figure. Stepper Motor Control The A3906 also can be used to control a bipolar stepper motor. The control logic for stepper motor control is shown in the lower figure. The driver is capable of operating in full- and half-step modes. VIN(1) IN1, IN3 GND VIN(1) PWM current control in fast and slow decay modes IN2, IN4 GND +IREG IOUTx 0A -IREG Forward/ Fast Decay Reverse/ Fast Decay Forward/ Slow Decay Reverse/ Slow Decay VIN(1) IN1 GND VIN(1) IN2 GND VIN(1) Stepper motor control in full- and half-step modes IN3 GND IN4 VIN(1) GND IOUT1 , IOUT2 IOUT3 , IOUT4 +VBB/ Rmotor 0A –VBB/ Rmotor +VBB/ Rmotor 0A –VBB/ Rmotor Full Step Sleep Half Step Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver load current for a very short period of time. Propagation delays are characterized and guard banded to protect the driver from damage during these events. Parallel Operation The A3906 can be paralleled for applications that require higher output currents. In paralleled mode the driver can source 2 A continuous. The A3906 has two completely independent bridges with separate overcurrent latches. This allows the device to supply two separate loads, and as a result, when paralleled it is imperative that the internal current control is disabled by shorting the sense pins to ground. Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A3906 must be soldered directly onto the board. On the underside of the A3906 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Because the overcurrent trip threshold is internally fixed at 0.2 V, the trace resistance must be kept small so the internal current latch is not triggered prematurely. With acceptable margin, the voltage drop across the trace resistance should be under 0.1 V. At a peak current of 2.5 A, the trace resistance should be kept below 40 mΩ to prevent false tripping of the overcurrent latch. Grounding In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the ground plane directly under the A3906, that area Each bridge has some variation in propagation delay. During this time it is possible that one bridge will have to support the full 0.1 μF 0.1 μF VBB CP2 CP1 CP2 CP1 VCP 0.1 μF OUT1A 10 μF 10 V OUT1B GND IN1 OUT2A IN2 A3906 IN3 OUT2B IN4 SLEEP SENSE1 FL1 SENSE2 FL2 DC Motor Operation (Parallel Bridge) IN1/IN3 IN2/IN4 OUT1A/2A OUT1B/2B Function 0 0 OFF OFF Disabled 1 0 H L FOR 0 1 L H REV 1 1 L L BRAKE Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The recommended PCB layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. Sense Pins The sense resistors, RSx, should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. As shown in the layout below, the SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor should be closer to the pins than the bulk capacitor. This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. Note: When selecting a value for the sense resistors, be sure not to exceed the maximum voltage on the SENSEx pins of ±500 mV. PCB Layout C2 C3 C3 C2 C1 R1 CP2 GND SLEEP OUT1A CP3 IN2 SENSE2 OUT2A OUT2B OUT1B VBB VBB OUT2B IN3 R2 R4 PAD IN1 IN4 VBB R1 OUT1B FL2 GND SENSE1 A3906 FL1 OUT1B VCP CP4 C1 U1 CP1 OUT1A OUT1A OUT2B R2 OUT2A +5V R4 OUT2A GND R3 R3 +5V A3906 Solder Trace (2 oz.) Signal (1 oz.) PCB Ground (1 oz.) Thermal (2 oz.) Thermal Vias Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A3906 Low Voltage Stepper and Single/Dual DC Motor Driver ES Package, 20-Contact QFN with Exposed Thermal Pad 0.30 4.00 ±0.15 1 2 0.50 20 20 0.95 A 1 2 4.00 ±0.15 2.45 4.10 2.45 4.10 21X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.75 ±0.05 0.50 C C PCB Layout Reference View For Reference Only (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) +0.15 0.40 –0.10 B 2.45 2 1 C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 20 2.45 Copyright ©2008-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10