Micrel MIC8030 High-voltage display driver Datasheet

MIC8030
Micrel
MIC8030
High-Voltage Display Driver
General Description
Features
The MIC8030 is a CMOS high voltage liquid crystal display
driver. Up to 38 segments can be driven from four CMOS level
inputs (CLOCK, DATA IN, LOAD and CHIP SELECT). The
MIC8030 is rated at 50V. Data is loaded serially into a shift
register, and transferred to latches which hold the data until
new data is received.
• High Voltage Outputs capable of a driving up to 100 volt
outputs from 5 to 15 volt logic
• Drives 30, 32, or 38 segments
• Cascadable
• On chip Oscillator or External Backplane Input
• CMOS construction for wide supply range and low
power consumption
• Schmitt Triggers on all inputs
• CMOS, PMOS, and NMOS compatible
The backplane can be driven from external source, or the
internal oscillator can be used. If the internal oscillator is
used, the frequency of the backplane will be determined by an
external resistor and capacitor. The oscillator need not be
used if a DC output is desired.
Applications
•
•
•
•
Functional Diagram
Dichroic and Standard Liquid Crystal Displays
Flat Panel Displays
Print Head Drives
Vacuum Fluorescent Displays
Ordering Information
Part Number
Data
Clock
MIC8030-01CV
S
38 Bit Static Shift Register
S
Temperature Range Package
0°C to +70°C
44-pin PLCC
Data Out 38
Data Out 32
CS
Load
Data Out 30
S
38 Bit Latch
S
LCD0
LCD0 Opt
Oscillator
Voltage Translators
Voltage
Translator
HV Output Drivers
HV Output
Driver
Segments
Back Plane
MIC8030
8-16
October 1998
MIC8030
Micrel
Back Plate
Seg 19
N/C
Seg 18
42
41
40
Data Out 32
44
43
Seg 21
Seg 22
3
Seg 20
Seg 23
2
Seg 24
4
1
Seg 25
6
5
Pin Configuration
Seg 26
7
39 Seg 17
Seg 27
8
38 Seg 16
Seg 28
9
37 Seg 15
Seg 29
10
Seg 30
11
36 VBB
35 Seg 14
MIC8030-01
34 Seg 13
Seg 7 28
Seg 6 27
Seg 5 26
LCD
Data In
24
29 Seg 8
Seg 4 25
30 Seg 9
17
Seg 3
16
Load
23
Clock
22
31 Seg 10
Seg 1
15
Seg 2
32 Seg 11
Chip Select
21
14
VCC
33 Seg 12
VSS
LCD Opt. 20
13
19
12
Seg 32
18
Seg 31
44-Pin PLCC (-V)
Functional Description
With CHIP SELECT tied low, serial data is clocked into the
shift register at each falling edge of the CLOCK input. Pulling
LOAD high will cause a parallel loading of the shift register
contents into the latches. If load is left high, the latches are
transparent.
A logic “1” clocked into the shift register corresponds to that
segment being on, and that segment is out of phase with the
backplane.
The backplane may be externally driven or the internal
oscillator can be used. If LCDφ is externally driven, the
backplane will be in phase with the input; LCDφ OPT is not
connected. The internal oscillator is used by shorting LCDφ
OPT to LCDφ, connecting a capacitor to ground, and a
resistor to VCC. The frequency of the backplane will be 1/256
of the input frequency, and is given as: f = 10/[R(C + .0002)]
at VDD = 5V, R in kΩ, C in µF.
For displays with more than 38 segments, two or more
MIC8030 may be cascaded by connecting DATA OUT of the
previous stage with DATA IN of the next stage; CLOCK,
LOAD and CHIP SELECT of all following stages should be
tied to the control lines of the first MIC8030. The backplane
output of the first stage should be tied to LCDφ of all following
stages, the LCDφ OPT must be left unconnected on those
stages. If the internal oscillator is used, and VBB > 50V then
an external 330 kΩ resistor must be used between the
BACKPLANE of the first stage and LCDφ of all following
stages.
Packaging options available include DATA OUT 30, 32 or 38
with the corresponding number of segments, and the availability of LCDφ OPT. Types of packages include plastic and
ceramic DIPs, surface mount packages, plastic and ceramic
Leadless Chip Carriers and custom packaging.
Example: R = 150 kΩ, C = 420 pF: f = 108 Hz
October 1998
8-17
MIC8030
8
MIC8030
Micrel
Internal Oscillator Circuit
V CC
200kΩ
–
+
200kΩ
Q
Divide by
256
Counter
–
+
200kΩ
O
Reset
–
+
Q
Clock
200kΩ
1kΩ
LCD0
30
kΩ
VZ
65V
VZ
35V
LCD0 Opt
Typical Application
External Oscillator
Chip Select
Clock
Load
Load Clock CS
Data In
Data
Load Clock CS
Data In
Data Out
MIC8030
LCD0
Load Clock CS
Data In
Data Out
MIC8030
LCD0
BP
Segments
1-32
Data Out
MIC8030
LCD0
BP
Segments
33-64
BP
Segments
65-96
Back Plane
Internal Oscillator
Chip Select
Clock
Load
Load Clock CS
Data
150kΩ
Data In
Load Clock CS
Data In
Data Out
MIC8030
Load Clock CS
Data In
Data Out
MIC8030
Data Out
MIC8030
*330kΩ
LCD0
470pF
BP
LCD0
LCD0
BP
BP
LCD0 Opt
Segments
1-32
Segments
33-64
Back Plane
Segments
65-96
*Required if using MIC8031 with VBB > 50V.
MIC8030
8-18
October 1998
MIC8030
Micrel
Absolute Maximum Ratings
VCC
VBB (MIC8030)
Inputs (CLK, DATA IN, LOAD, CS)
Inputs (LCD0)
Storage Temperature
Operating Temperature
Maximum Current into and out of
any segment
Maximum Power Dissipation,
any segment
Maximum Total power dissipation
18V
75V
–0.5V to 18V
–0.5V to 50V
–65°C to +150°C
–55°C to +125°C
DC Electrical Characteristics:
VCC = 5V, VSS = 0V, VBB = 50V, –55°C ≤ TA ≤ +125°C, unless otherwise noted.
Symbol
20 mA
50 mW
600 mW
Parameter
Condition
Min
Typ
Max
Units
Power Supply
VCC
Logic Supply Voltage
4.5
5
5.5
V
VBB
Display Supply Voltage
20
35
50
V
ICC
Supply Current (external oscillator)
Note 1
35
250
µA
Supply Current (internal oscillator)
Note 1
35
250
µA
Display Driver Current
fBP = 100Hz, no loads
7
100
µA
VCC
V
2.5
2.0
V
<1
5
µA
5
10
pF
IBB
Inputs (CLK, DATA IN, LOAD, CS)
VIH
Input High Level
VCC-1.5 VCC-1.8
VIL
Input Low Level
IL
Input Leakage Current
CI
Input Capacitance
Note 2
VIH
LCD0 Input High Level
Externally driven
0.9VCC
VCC
50
V
VIL
LCD0 Input Low Level
Externally driven
–0.5V
0
0.1VCC
V
ILCD0
LCD0 Leakage Current
VLCD0 = 15V
2
10
µA
ILCD0
LCD0 Leakage Current
VLCD0 = 35V
6
100
µA
ILCD0
LCD0 Leakage Current
VLCD0 = 50V
1
mA
0
Input LCD0
Capacitance Loads (typical)
CLSEG
Segment Output
fBP < 100Hz
100
pF
CLBP
Backplane Output
fBP < 100Hz
4000
pF
VOAVG
DC Bias (Average) Any Segment
fBP < 100Hz, Note 2
+25
mV
Output to Backplane
RSEG
Segment Output Impedance
IL = 100µA
1.4
10
kΩ
RBP
Backplane Output Impedance
IL = 100µA
170
312
Ω
RDATA OUT
Data Out Output Impedance
IL = 100µA
1.8
3
kΩ
Note 1: CMOS input levels. No loads.
Note 2: Guaranteed by design but not tested on a production basis.
October 1998
8-19
MIC8030
8
MIC8030
Micrel
AC Electrical Characteristics:
VCC = 5V, VSS = 0V, VBB = 50V, –55°C ≤ TA ≤ +125°C
Symbol
Parameter
Min
tCYC
Cycle Time
500
ns
tOL, tOH
Clock Pulse Width low/high
250
ns
tr, tf
Clock rise/fall
tDS
Data In Setup
100
ns
tCSC
CS Setup to Clock
100
ns
tDH
Data Hold
10
ns
tCCS
CS Hold
220
ns
tCL
Load Pulse Setup
250
ns
tLCS
CS Hold (rising load to rising CS)
200
ns
tLW
Load Pulse Width
300
ns
tLC
Load Pulse Delay (falling load to
falling clock)
0
ns
tCDO
Data Out Valid from Clock
tCSL
CS Setup to LOAD
0
FBP
Backplane Frequency
50
3.5V
1.5V
*
tDH
tCCS
2000
Hz
QN(SR)
QN(DRIVER)
X
X
1
X
NC
NC
QN(L)
0
↑
0
0
NC
NC
QN(L)
0
↑
0
1
NC
NC
QN(L)
0
↓
0
0
0
QN - 1→QN
QN(L)
0
↓
0
1
0
QN - 1→QN
QN(SR)
1
↑
0
0
NC
NC
QN(L)
1
↑
0
1
NC
NC
QN(L)
1
↓
0
0
1
QN - 1→QN
QN(L)
1
↓
0
1
1
QN - 1→QN
QN(SR)
tLCS
*
tCSL
tCL
tLC
tLW
Load
tCDO
Data
Out
* The CS high-to-low transition will generate a clock pulse.
MIC8030
100
tr
Data
In
CS
ns
Data
Chip
In
Clock Select Load Q1(SR)
Clock
tCSC
ns
Logic Truth Table
tOH
tDS
Units
µs
220
tCYC
tOL
Max
1
Timing Diagram
tf
Typ
↑ = Rising Edge, ↓ = Falling Edge
8-20
October 1998
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