GENLINX II ™ GS9000D Serial Digital Decoder DATA SHEET DEVICE DESCRIPTION • fully compatible with SMPTE 259M-ABC The GS9000D is a CMOS integrated circuit specifically designed to deserialize SMPTE 259M serial digital signals at data rates up to 270Mb/s. The GS9000D is a pin and functional equivalent to the GS9000C, with the exception of SDI input levels which are compatible for direct interfacing to the GS7025, GS9025A and GS9035A. • decodes 8 and 10 bit serial digital signals for data rates to 270Mb/s • recommended alternative to GS9000C for use when interfacing directly to GS7025, GS9025A or GS9035A • incorporates automatic standards selection The device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry. • 325mW power dissipation at 270MHz clock rate • Pb-free and Green • operates from single +5 or -5 volt supply Differential pseudo-ECL inputs for both serial clock and data are internally level shifted to CMOS levels. Digital outputs such as parallel data, parallel clock, HSYNC, Sync Warning and Standard Select are all TTL compatible. • 28 pin PLCC packaging APPLICATIONS • 4ƒSC and 4:2:2 serial digital interfaces • Automatic standards select controller for serial routing and distribution applications The GS9000D is packaged in a 28 pin PLCC and operates from a single 5 volt, ±5% power supply. ORDERING INFORMATION PART NUMBER PACKAGE TEMPERATURE Pb-FREE AND GREEN GS9000DCPJ 28 Pin PLCC 0°C to 70°C No GS9000DCTJ 28 Pin PLCC Tape 0°C to 70°C No GS9000DCPJE3 28 Pin PLCC 0°C to 70°C Yes GS9000DCTJE3 28 Pin PLCC Tape 0°C to 70°C Yes GS9000D SERIAL DATA IN LEVEL SHIFT SERIAL DATA IN SERIAL CLOCK IN SERIAL CLOCK IN LEVEL SHIFT DESCRAMBLER 30 - BIT SHIFT REG SYNC DETECT (3FF 000 000 HEX) SCLK Sync SYNC CORRECTION ENABLE Word Boundary SP PARALLEL TIMING GENERATOR PARALLEL DATA OUT (10 BITS) PARALLEL CLOCK OUT SYNC CORRECTION Sync Error HSYNC OUTPUT SYNC WARNING (Schmitt Trigger Comparator) SYNC WARNING CONTROL SYNC WARNING FLAG AUTO STANDARD SELECT STANDARDS SELECT CONTROL OSC 2 BIT COUNTER SS0 SS1 Hsync Reset FUNCTIONAL BLOCK DIAGRAM Revision Date: June 2004 Document No. 18784 - 3 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected] www.gennum.com GS9000D FEATURES ABSOLUTE MAXIMUM RATINGS PARAMETER VALUE 7V Input Voltage Range (any input) -0.3 to (VDD + 0.3) DC Input Current (any one input) GS9000D Supply Voltage (VS = VDD - VSS) ±10µA Operating Temperature Range 0°C to 70°C Storage Temperature Range -65°C to +150C Lead Temperature (Soldering, 10 seconds) 260°C DC ELECTRICAL CHARACTERISTICS VDD = 5V, TA = 0°C to 70°C unless otherwise shown PARAMETER SYMBOL CONDITIONS NOTES TEST LEVEL MIN TYP MAX UNITS 4.75 5.00 5.25 V 3 Supply Voltage VS Operating range Power Consumption (outputs unloaded) PC ƒ = 143MHz - 235 - mW 7 ƒ = 270MHz - 325 - mW 7 3.4 - - V 1 - - 1.5 V 1 CMOS Input Voltage VIHMIN TA = 25°C VILMAX Output Voltage Input Leakage Current VOHMIN IOH = 4mA, 25°C 2.4 4.5 - V 1 VOLMAX IOL = 4mA, 25°C - 0.2 0.5 V 1 ΙIN VIN = VDD or VSS - - ±10 µA 3 3.0 - 4.05 V Serial Clock and Data Inputs Common Mode Voltage VCM TA = 25°C, VIN = 700 to 1200mVpp Centre of Swing 1 TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 2 of 9 GENNUM CORPORATION 18784 - 3 AC ELECTRICAL CHARACTERISTICS VDD = 5V, TA = 0°C to 70°C unless otherwise shown PARAMETER Serial Input Clock Frequency Serial Input Data Rate SYMBOL NOTES TEST LEVEL MIN TYP MAX UNITS ƒSCI 100 - 270 MHz 1 DRSDI 100 - 270 Mb/s 1 TA = 25°C Setup tSU 1.0 - - ns 7 Hold tHOLD 1.0 - - ns 7 VIN 700 800 1200 mVpp 1 TA = 25° - 1.0 - ns p-p 7 TA = 25°C, - 3 - ns 20% to 80% 7 - - ±3 ns Rising edge of PCLK to bit period centre 7 Signal Swing Parallel Clock: Jitter tJCLK Parallel Data: Risetime and Falltime tR-PDn CL = 10pF PDn to PCLK Delay Tolerance tD TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 3 of 9 GENNUM CORPORATION 18784 - 3 GS9000D Serial Data and Clock Inputs: CONDITIONS VSS SWF 4 3 VSS HSYNC 2 (MSB) PD9 28 PD8 27 VSS 26 5 25 PD7 SDI 6 24 PD6 SCI 7 23 PD5 SCI 8 22 PD4 SS1 9 21 PD3 SS0 10 20 PD2 SSC 11 19 PD1 GS9000D SDI GS9000D TOP VIEW 12 13 14 15 16 17 18 VDD VDD SCE SWC PCLK PD0 VDD (LSB) Fig. 1 GS9000D Pin Outs, 28 Pin PLCC Package PIN DESCRIPTIONS PIN NO. SYMBOL TYPE DESCRIPTION 1 HSYNC Output Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected. 2 VSS 3 SWF 4 VSS 5, 6 SDI/SDI Inputs Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.05V for operation up to 270MHz. See AC Electrical Characteristics Table for details. 7, 8 SCI/SCI Inputs Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.05V for operation up to 270MHz. See AC Electrical Characteristics Table for details. 9,10 SS1/SS0 Output Standard Select Outputs. CMOS (TTL compatible) outputs is generated by a 2-bit internal binary counter which stops cycling when a valid TRS is detected by the GS9000D. 11 SSC Input 12 VDD Power Supply. Most positive power supply connection. 13 VDD Power Supply. Most positive power supply connection. 14 SCE Power Supply. Most negative power supply connection. Output Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC input. Power Supply. Most negative power supply connection. Input Standards Select Control. Analog input used to set a time constant for the standards select hunt period. An external RC sets the time constant. Sync Correction Enable. Active high CMOS input which enables sync correction by not resetting the GS9000D’s internal parallel timing on the first sync error. If the next incoming sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE is low, a valid sync will always reset the GS9000D’s parallel timing generator 4 of 9 GENNUM CORPORATION 18784 - 3 PIN DESCRIPTIONS PIN NO. SYMBOL TYPE DESCRIPTION 15 SWC Input 16 PCLK Output Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7. 17 PD0 Output Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing the least significant bit (LSB). 18 VDD 19-25 PD1 - PD7 26 VSS 27 PD8 Output Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing data bit 8. 28 PD9 Output Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial to parallel convertor representing the most significant bit (MSB). Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is accomplished by an external RC time constant connected to this pin. Outputs Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from the serial to parallel convertor representing data bit 1 through data bit 7. Power Supply. Most negative power supply connection. INPUT/OUTPUT CIRCUITS VDD VDD VDD REXT SDI SSC SCI BIAS EXTERNAL COMPONENTS VDD Fig. 2 Pin 11 SSC SDI SCI VDD VDD Fig. 4 Pins 5 - 8 SDI - SCI SCE Fig. 3 Pin 14 SCE 5 of 9 GENNUM CORPORATION 18784 - 3 GS9000D Power Supply. Most positive power supply connection. VDD VDD VDD REXT SWC 6k8 GS9000D OUTPUT CEXT EXTERNAL COMPONENTS GND Fig. 5 Pin 15 SWC Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28 SWF, HSYNC, SSI, SSD, PCLK, PD0-9 1/ T 2 tCLKL = tCLKH 2 T PARALLEL DATA (PDn) 50% SERIAL CLOCK (SCI) 1/ PARALLEL CLOCK (PCLK) SERIAL DATA (SDI) tSU tHOLD 50% tD Fig. 7 Waveforms TEST SET-UP & APPLICATION INFORMATION Figure 8 shows the test set-up for the GS9000D operating from a VDD supply of +5 volts. The differential pseudo ECL inputs for DATA and CLOCK (pins 5,6,7 and 8) must be biased between +3.0 and +4.05 volts. In the application circuit shown in Figure 11, these inputs can be directly driven from the outputs of the GS7025 Reclocking Receiver with their resistor values set as shown. If the automatic standard select function is not used, the Standard Select bits (pins 9 and 10) do not need to be connected, however the control input (pin 11) should be grounded. In other cases, such as true ECL level driver outputs, two biasing resistors are needed on the DATA and CLOCK inputs and the signals must be AC coupled. It is critical that the decoupling capacitors connected to pins 12,13 and 18 are chip types and are located as close as possible to the device pins. The critical high speed inputs, such as Serial Data (pins 5 and 6) and Serial Clock (pins 7 and 8), are located along one side of the device package to maintain very short interconnections when interfacing with the GS7025 Receiver. 6 of 9 GENNUM CORPORATION 18784 - 3 ** Locate the three 0.10µF decoupling capacitors as close as possible to the corresponding pins on the GS9000D. Chip capacitors are recommended. +5V 22µ 3 x 100n HSYNC OUTPUT ** 12 SDIIN SCIIN SCIIN STANDARDS SELECT BIT 1 STANDARDS SELECT BIT 0 +5V 100k 820p 18 1 VDD VDD VDD HSYNC 17 PD0 DECODER 19 PDI 5 SDI GS9000D 20 PD2 6 SDI 21 PD3 7 SCI PD4 22 8 SCI 23 PD5 9 SS1 24 PD6 10 SS0 PD7 25 11 SSC PD8 27 PARALLEL DATA BIT 0 PARALLEL DATA BIT 1 PARALLEL DATA BIT 2 PARALLEL DATA BIT 3 PARALLEL DATA BIT 4 PARALLEL DATA BIT 5 PARALLEL DATA BIT 6 PARALLEL DATA BIT 7 PARALLEL DATA BIT 8 PD9 28 PCLK SCE VSS VSS VSS SWC SWF 2 4 26 15 3 GS9000D SDIIN 13 PARALLEL DATA BIT 9 16 PARALLEL CLOCK OUT 14 SYNC CORRECTION ENABLE 10p SYNC WARNING FLAG 13 x 425 39k All resistors in ohms, all capacitors in farads, unless otherwise specified. +5V Fig. 8 GS9000D Test Set-Up With synchronized serial data and clock connected to the GS9000D, the HSYNC output (pin 1) will toggle for each HSYNC detected. The Parallel Data bits PD0 through PD9 and the Parallel Clock can be observed on an oscilloscope or fed to a logic analyzer. To directly drive parallel inputs to receiving equipment, such as monitors or digital to analog converters, these outputs can be fed through a suitable TTL to ECL converter. The HSYNC output toggles to indicate the presence of the TRS on the falling edge of PCLK, one data symbol prior to the output of the first word in the TRS. In the following diagram, data is indicated in 10-bit Hex. PCLK PDN In operation, the HSYNC output from the GS9000D decoder toggles on each occurrence of the timing reference signal (TRS). The state of the HSYNC output is not significant, but the time at which it toggles is significant. 4ƒSC DATA STREAM T R S ACTIVE VIDEO & H BLANKING E A V H BLNK T R S ACTIVE VIDEO & H BLANKING XXX 3FF 000 000 XXX XXX 3FF 000 000 XXX HSYNC Fig. 10 Operation of HSYNC with Respect to PCLK T R S HSYNC OUT 4:2:2 DATA STREAM S A V ACTIVE VIDEO E A V H BLNK S A V HSYNC OUT Fig. 9 Operation of HSYNC Output 7 of 9 GENNUM CORPORATION 18784 - 3 TYPICAL APPLICATION CIRCUIT - Adjustment Free Multi-standard Serial To Parallel Convertor Vcc 8.2nH 100nF Vcc 1uF Serial Data Output 1uF 100nF 75 5 VEE GS9000D 6 SDI 90.9 SDI 90.9 VCC 7 GS9028 4 RSET 3 100nF VEE 2 SDO 1 SDO 37.5 8 75 Vcc 59 Vcc LOCK Vcc Vcc Vcc 22k CD Vcc 4.75k 150 150 CLK_EN 150 CLK_EN Vcc Vcc 100nF SSC Vcc 8 22 9 21 10 20 11 NC 19 12 13 14 15 16 17 PD6 100 PD5 100 PD4 100 PD3 100 PD2 100 PD1 100 Vcc 100nF NC 100 PD7 100 18 VDD Vcc 270 Vcc VSS 22 NC GS9000D 100 21 Vcc 68k 22nF 100nF 100nF VCC RVCO 365 Vcc 20 CBG VEE 15nF RVCO_RTN LFS LF- VEE 1.8k 19 SS0 23 PCLK 18 VEE 24 PD0 17 SS1 PD9 16 LF+ AGC+ 100nF 100pF VCC 100k 15 SCO PD8 23 14 SCI 100 26 6 100nF 11 SCO 27 7 SCE 24 SCI 28 SWC 10 VEE 1 25 VDD 25 SDI 2 100 5 VDD 26 9 SDO 3 HSYNC 27 13 3k3 28 SDI VSS 29 GS7025 (2) 4 SDO SWF 30 12 Pot 100 31 4 VSS 3 VEE 90.9 32 90.9 100nF AGC- 33 8 VEE Vcc 34 7 VCC CD_ADJ 35 VEE 10n VCC 75 Vcc 37.5 36 2 6 SDI 37 1 5 SDI 38 CLK_EN 10n 39 VEE 75 40 COSC 15nH (1) 100nF VEE 4.7nF 75 VCC 41 LOCK VCC_75 SSI/CD 100nF Serial Data Input DDI 42 A/D DDI Vcc 43 MOD VCC 44 OEM_TEST Vcc Vcc * 3.3pF NOTE: Value of SDO and SCO pull-up resistors is 90.9Ω ± 1% (1) Typical value for input return loss matching (2) The GS7025 can be replaced by either the GS9025A or GS9035A for applications at data rates less then 270Mb/s or when equalization is not required Fig. 11 GS9000D and GS7025 INTERCONNECTIONS Figure 11 shows an application of the GS9000D in a 270Mb/s serial to parallel converter. This circuit uses the GS7025 Serial Digital Receiver. For datarates below 270Mb/s the GS9025A can be used. If cable equalization is not required the GS7025 or GS9025A may be replaced with a GS9035A Reclocker IC. The GS9028 Cable Equalizer allows a serial loop through after the reclocker. 8 of 9 GENNUM CORPORATION 18784 - 3 SYNC WARNING FLAG OPERATION GS9000D Each time HSYNC is not correctly detected, the Sync Warning Flag output (pin 3 ) will go HIGH. The RC network connected to the Sync Warning Control input (pin 15) sets the number of sync errors that will cause the SWF pin to go HIGH. The component values of the RC network shown in Figure 12 set the SWF error rate to approximately one HSYNC error in 10 lines. These component values are chosen for optimum performance of the SWF pin, and should not be adjusted. Typically, HSYNC errors become visible on a monitor before the SWF provides an indication of HSYNC errors. As a result, the SWF function can be used in applications where the detection of significant signal degradation is desired. A high SWF goes low when the input error rate decreases below the set rate. A small amount of hysteris in the comparator ensures noise immunity. VDD COMPARATOR 15 VDD SYNC WARNING CONTROL 6k8 + 3 SYNC WARNING FLAG (SWF) SYNC ERROR Fig. 12 Sync Warning Flag Circuit CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION REVISION NOTES: Added lead-free and green information. PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice. GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright May 2000 Gennum Corporation. All rights reserved. Printed in Canada. 9 of 9 18784 - 3