TI FB2041A 7-bit ttl/btl transceiver Datasheet

SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
D
D
D
D
D
Compatible With IEEE Std 1194.1-1991
(BTL)
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
Open-Collector B-Port Outputs Sink
100 mA
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion or Withdrawal
D
D
High-Impedance State During Power Up
and Power Down
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
TTL-Input Structures Incorporate Active
Clamping to Aid in Line Termination
TMS
GND
1B1
2AO1
1AI1
1AO1
VCC
BIAS VCC
1OEA
OEB
1OEB
TCK
VCC
RC PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
GND
2B1
GND
2B2
GND
2B3
GND
3B1
GND
3B2
GND
3B3
GND
3OEB
3OEA
2OEB
BG GND
2OEA
TDO
TDI
VCC
14 15 16 17 18 19 20 21 22 23 24 25 26
3AI2
GND
3AO3
BG VCC
3AI3
GND
2AI1
2AI2
2AO2
GND
2AO3
GND
2AI3
3AI1
3AO1
GND
3AO2
GND
description
The SN74FB2041A is a 7-bit transceiver designed to translate signals between TTL and backplane transceiver
logic (BTL) environments. The device is specifically designed to be compatible with IEEE Std 1194.1-1991.
The B port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is high and OEB is low, the B port is active
and reflects the inverse of the data present at the A-input pins. When OEB is low, OEB is high, or VCC is less
than 2.1 V, the B port is turned off. The enable/disable logic partitions the device as two 3-bit sections and one
1-bit section.
The A port operates at TTL signal levels and has split input and output pins. The A outputs reflect the inverse
of the data at the B port when the A-port output enable (OEA) is high. When OEA is low or when VCC is less
than 2.1 V, the A outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
description (continued)
The pins TMS, TCK, TDI, and TDO are nonfunctional, i.e., not intended for use with the IEEE Std 1149.1 (JTAG)
test bus. TMS and TCK are not connected and TDI is shorted to TDO.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
ORDERING INFORMATION
PACKAGE†
TA
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C QFP – RC Tube
SN74FB2041ARC
FB2041A
† Package drawings, standard packing quantities, thermal data,
symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
2
OEB
OEB
OEA
L
X
L
X
H
L
FUNCTION
Isolation
L
X
H
X
H
H
H
L
L
AI data to B bus
H
L
H
AI data to B bus, B data to AO bus
B data
d t to
t AO bus
b
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SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
functional block diagram
OEB
1OEB
1OEA
1AI1
1AO1
2OEB
2OEA
2AI1
2AO1
46
45
47
40
51
50
25
20
38
2
2B1
52
36
3
2AI2
2AO2
2B2
4
34
8
2B3
2AI3
2AO3
1B1
6
26
3OEB
24
3OEA
3AI1
3AO1
3AI2
3AO2
3AI3
32
9
3B1
10
30
14
3B2
12
28
18
3B3
16
3AO3
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3
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 3.5 V
Voltage range applied to any B output in the disabled or power-off state, VO . . . . . . . . . . . . . . –0.5 V to 3.5 V
Voltage range applied to any output in the high state, VO: A port . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC
Input clamp current, IIK: Except B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Current applied to any single output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θJA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
VCC,
BIAS VCC,
BG VCC
Supply voltage
VIH
High level input voltage
High-level
VIL
Low level input voltage
Low-level
IIK
IOH
Input clamp current
IOL
Low level output current
Low-level
B port
Except B port
B port
Except B port
High-level output current
AO port
AO port
B port
MIN
NOM
MAX
4.5
5
5.5
1.62
2.3
2
0.75
1.47
0.8
UNIT
V
V
V
–18
mA
–3
mA
24
100
mA
TA
Operating free-air temperature
0
70
°C
NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: A and control inputs to VCC(5 V) or GND, and
B inputs to GND only. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
MIN
TYP†
MAX
II = –18 mA
II = –40 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = –3 mA
IOL = 24 mA
2.5
AO port
VCC = 4
4.5
5V
IOL = 80 mA
IOL = 100 mA
0.75
B portt
II
Except B port
VCC = 5.5 V,
VI = 5.5 V
50
µA
IIH‡
Except B port
VCC = 5.5 V,
VCC = 5.5 V,
VI = 2.7 V
VI = 0.5 V
50
µA
Except B port
–50
B port
VCC = 5.5 V,
VI = 0.75 V
–100
IOH
IOZH
B port
VCC = 0 to 5.5 V,
VCC = 5.5 V,
VO = 2.1 V
VO = 2.7 V
100
µA
50
µA
IOZL
IOZPU
AO port
VO = 0.5 V
VO = 0.5 V to 2.7 V
–50
µA
AO port
VCC = 5.5 V,
VCC = 0 to 2.1 V,
50
µA
IOZPD
IOS§
AO port
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V
–50
µA
AO port
VCC = 5.5 V,
VO = 0
–180
mA
VCC = 5
5.5
5V
V,
IO = 0
VOH
VOL
IIL‡
ICC
Except B port
AO port
AO port
AI port to B port
B port to AO port
AI port
Ci
Control inputs
Co
AO port
Cio
B port per
IEEE Std 1194.1-1991
–1.2
UNIT
VCC = 4.5 V,
VCC = 4.5 V,
VIK
B port
TEST CONDITIONS
–0.5
3.3
0.35
V
0.5
1.1
–30
45
65
5.5
mA
pF
5
VCC = 4.5 V to 5.5 V
µA
A
pF
3
VO = 0.5 V or 2.5 V
VCC = 0 to 4.5 V
V
1.15
3
VI = 0.5
0 5 V or 2.5
25V
V
5
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
live-insertion specifications over recommended operating free-air temperature range
PARAMETER
ICC (BIAS VCC)
VO
IO
B port
B port
TEST CONDITIONS
VCC = 0 to 4.5 V
VCC = 4.5 V to 5.5 V
VB = 0 to 2 V,
V
Vl (BIAS VCC) = 4.5
4 5 V to 5
5.5
5V
VCC = 0,
VCC = 0,
VI (BIAS VCC) = 5 V
VB = 1 V,
Vl (BIAS VCC) = 4.5 V to 5.5 V
VCC = 0 to 5.5 V,
VCC = 0 to 2.2 V,
MIN
MAX
450
10
µA
2.1
V
OEB = 0 to 0.8 V
100
µA
OEB = 0 to 5 V
100
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5
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
AI
B
tPLH
tPHL
B
AO
tPLH
tPHL
OEB
B
tPLH
tPHL
OEB
B
tPZH
tPZL
OEA
AO
tPHZ
tPLZ
OEA
AO
PARAMETER
tsk(p)†
tsk(o)†
tt
t(pr)
MIN
MAX
5.1
2
5.6
4.1
5
2.5
5.3
MIN
TYP
MAX
2.3
3.9
2.6
2
3.6
4.8
1.7
5.3
2.3
3.8
4.9
2
6.4
3
4.6
5.8
2.6
6.3
3.1
4.7
6
3.1
6.2
2.7
4.3
5.6
2.6
5.8
2.7
4.2
5.3
2.5
6.4
1.5
3.2
5.2
1.5
5.2
1.1
2.8
5
1
5
1
2.4
3.9
1
4.2
2.2
3.8
5.6
1.7
5.8
UNIT
ns
ns
ns
ns
ns
ns
Pulse skew, AI to B or B to AO
0.5
ns
Output skew, AI to B or B to AO
0.4
ns
Rise time, 1.3 V to 1.8 V, B outputs
1
1.6
2.4
1
2.5
Fall time, 1.8 V to 1.3 V, B outputs
1
1.4
2.3
1
2.4
B-port input pulse rejection
1
† Skew values are applicable for through mode only.
6
VCC = 5 V,
TA = 25°C
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1
ns
ns
SN74FB2041A
7-BIT TTL/BTL TRANSCEIVER
SCBS172M – NOVEMBER 1991 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
2.1 V
16.5 Ω
7V
S1
500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Open
CL = 30 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR A OUTPUTS
Input
1.5 V
Test
Point
From Output
Under Test
LOAD CIRCUIT FOR B OUTPUTS
3V
TEST
S1
0V
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
1.5 V
tPHL
tPLH
1.55 V
1.55 V
VOH
Output
VOL
3V
Output
Control
tPZL
2V
1.55 V
1.55 V
1V
tPHL
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
3.5 V
1.5 V
tPZH
tPLH
VOH
Output
1.5 V
0V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
Input
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES (A PORT)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
SN74FB2041ARC
ACTIVE
QFP
RC
52
96
TBD
CU SNPB
SN74FB2041ARCG3
ACTIVE
QFP
RC
52
96
Green (RoHS &
no Sb/Br)
CU SN
SN74FB2041ARCR
ACTIVE
QFP
RC
52
500
TBD
CU SNPB
SN74FB2041ARCRG3
ACTIVE
QFP
RC
52
500
Green (RoHS &
no Sb/Br)
CU SN
MSL Peak Temp (3)
Level-2-240C-1YR
Level-3-260C-168 HR
Level-2-240C-1YR
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MQFP003 – OCTOBER 1994
RC (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
0,65
39
0,13 M
27
40
26
52
14
0,16 NOM
1
13
7,80 TYP
10,20
SQ
9,80
13,45
SQ
12,95
Gage Plane
0,25
0,05 MIN
2,20
1,80
0°– 7°
1,03
0,73
Seating Plane
2,45 MAX
0,10
4040151 / B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
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