AD AD7303BR 2.7 v to 5.5 v, serial input, dual voltage output 8-bit dac Datasheet

a
+2.7 V to +5.5 V, Serial Input, Dual
Voltage Output 8-Bit DAC
AD7303
FEATURES
Two 8-Bit DACs in One Package
8-Pin DIP/SOIC and microSOIC Packages
+2.7 V to +5.5 V Operation
Internal & External Reference Capability
Individual DAC Power-Down Function
Three-Wire Serial Interface
QSPI™, SPI™ and Microwire™ Compatible
On-Chip Output Buffer
Rail-to-Rail Operation
On-Chip Control Register
Low Power Operation: 2.3 mA @ 3.3 V
Full Power-Down to 1 mA max, typically 80 nA
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
FUNCTIONAL BLOCK DIAGRAM
AD7303
INPUT
REGISTER
DAC
REGISTER
I DAC A
I/V
VOUT A
INPUT
REGISTER
DAC
REGISTER
I DAC B
I/V
VOUT B
CONTROL (8)
DATA (8)
DIN
SCLK
SYNC
MUX
POWER ON
RESET
16-BIT SHIFT REGISTER
÷2
GND
REF
VDD
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7303 is a dual, 8-bit voltage out DAC that operates
from a single +2.7 V to +5.5 V supply. Its on-chip precision output buffers allow the DAC outputs to swing rail to rail. This device uses a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz, and is compatible with QSPI, SPI, microwire
and digital signal processor interface standards. The serial input
register is sixteen bits wide; 8 bits act as data bits for the DACs,
and the remaining eight bits make up a control register.
1. Low power, single supply operation. This part operates from
a single +2.7 V to +5.5 V supply and consumes typically
15 mW at 5.5 V, making it ideal for battery powered
applications.
The on-chip control register is used to address the relevant
DAC, to power down the complete device or an individual
DAC, to select internal or external reference and to provide a
synchronous loading facility for simultaneous update of the
DAC outputs with a software LDAC function.
4. High speed serial interface with clock rates up to 30 MHz.
2. The on-chip output buffer amplifiers allow the outputs of the
DACs to swing rail to rail with a settling time of typically 1.2 µs.
3. Internal or external reference capability.
5. Individual power-down of each DAC provided. When completely powered down, the DAC consumes typically 80 nA.
The low power consumption of this part makes it ideally suited
to portable battery operated equipment. The power consumption is 7.5 mW max at 3 V, reducing to less than 3 µW in full
power-down mode.
The AD7303 is available in an 8-pin plastic dual in-line package, 8-lead SOIC and microSOIC packages.
QSPI and SPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
V to +5.5 V, Internal Reference; R = 10 kV to V
AD7303–SPECIFICATIONS (Vto GND;= +2.7
all specifications T to T unless otherwise noted)
DD
L
MIN
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error @ +25°C
Full-Scale Error
Gain Error3
Zero-Code Temperature Coefficient
B Versions1
Units
8
±1
±1
3
–0.5
+1
100
Bits
LSB max
LSB max
LSB max
LSB typ
% FSR typ
µV/°C typ
DAC REFERENCE INPUT
REFIN Input Range
REFIN Input Impedance
Internal Voltage Reference Error 4
1 to VDD/2
10
±1
V min to max
ΜΩ typ
% max
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Digital to Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DC Output Impedance
Short Circuit Current
Power Supply Rejection Ratio
0 to VDD
2
7.5
0.5
0.2
0.2
± 0.2
40
14
0.0001
V min to max
µs max
V/µs typ
nV-s typ
nV-s typ
nV-s typ
LSB typ
Ω typ
mA typ
%/% max
± 10
0.8
0.6
2.4
2.1
5
µA max
V max
V max
V min
V min
pF max
2.7/5.5
V min/max
LOGIC INPUTS
Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 3.3 V
@ +25°C
TMIN – TMAX
VDD = 5.5 V
@ +25°C
TMIN – TMAX
IDD (Full Power-Down)
@ +25°C
TMIN – TMAX
2.1
2.3
mA max
mA max
2.7
3.5
mA max
mA max
80
1
nA typ
µA max
DD
and GND; CL = 100 pF
MAX
Conditions/Comments
Note 2
Guaranteed Monotonic
All Zeros Loaded to DAC Register
All Ones Loaded to DAC Register
Typically 1.2 µs
1 LSB Change Around Major Carry
∆ VDD = ± 10%
VDD = +5 V
VDD = +3 V
VDD = +5 V
VDD = +3 V
Both DACs Active and Excluding Load Currents,
VIH = VDD, VIL = GND
See Figure 8
VIH = VDD, VIL = GND
See Figure 19
NOTES
1
Temperature ranges are as follows: B Version, –40°C to +105°C.
2
Relative Accuracy is calculated using a reduced digital code range of 15 to 245.
3
Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4
Internal Voltage Reference Error = (Actual V REF – Ideal VREF/Ideal V REF) • 100. Ideal V REF = VDD/2, actual VREF = voltage on reference pin when internal reference
is selected.
Specifications subject to change without notice.
ORDERING GUIDE
Model
Temperature
Range
Package
Options*
AD7303BN
AD7303BR
AD7303BRM
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
N-8
SO-8
RM-8
*N = Plastic DIP; R = SOIC; RM = microSOIC.
–2–
REV. 0
AD7303
TIMING CHARACTERISTICS1, 2
(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD /2 Reference; all specifications
TMIN to TMAX unless otherwise noted)
Parameter
Limit at TMIN, TMAX (B Version)
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
33
13
13
5
5
4.5
4.5
33
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC Setup Time
Data Setup Time
Data Hold Time
SYNC Hold Time
Minimum SYNC High Time
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2,
tr and tf should not exceed 1 µs on any input.
2
See Figures 1 and 2.
t1
SCLK (I)
t2
t8
t3
t7
t4
t4
SYNC (I)
t5
t6
DIN (I)
DB15
DB0
Figure 1. Timing Diagram for Continuous 16-Bit Write
t1
SCLK (I)
t2
t8
t3
t7
t4
SYNC (I)
t5
t5
t6
DIN (I)
DB15
t6
DB8
DB7
Figure 2. Timing Diagram for 2 × 8-Bit Writes
REV. 0
–3–
DB0
AD7303
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 157°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
VOUT A, VOUT B to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 800 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7303 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
(DIP, SOIC and microSOIC)
8 VOUT B
VOUT A 1
VDD 2
AD7303
7 SYNC
TOP VIEW
6 DIN
(Not to Scale)
5 SCLK
REF 4
GND 3
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
VOUT A
Analog Output Voltage from DAC A. The output amplifier swings rail to rail on its output.
2
VDD
Power Supply Input. These parts can be operated from +2.7 V to +5.5 V and should be decoupled to GND.
3
GND
Ground reference point for all circuitry on the part.
4
REF
External Reference Input. This can be used as the reference for both DACs, and is selected by setting the
INT/EXT bit in the control register to a logic one. The range on this reference input is 1 V to VDD/2. When
the internal reference is selected, this voltage will appear as an output for decoupling purposes at the REF Pin.
When using the internal reference, external voltages should not be connected to the REF Pin, see Figure 21.
5
SCLK
Serial Clock. Logic Input. Data is clocked into the input shift register on the rising edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
6
DIN
Serial Data Input. This device has a 16-bit shift register, 8 bits for data and 8 bits for control. Data is clocked
into the register on the rising edge of the clock input.
7
SYNC
Level Triggered Control Input (active low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the rising edges of the following
clocks. The rising edge of the SYNC causes the relevant registers to be updated.
8
VOUT B
Analog output voltage from DAC B. The output amplifier swings rail to rail on its output.
–4–
REV. 0
AD7303
TERMINOLOGY
DIGITAL-TO-ANALOG GLITCH IMPULSE
INTEGRAL NONLINEARITY
For the DACs, relative accuracy or endpoint nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function. A graphical representation of the transfer curve is shown
in Figure 15.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected and the software LDAC used to update the DAC.
It is normally specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.
DIFFERENTIAL NONLINEARITY
DIGITAL FEEDTHROUGH
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change of any two adjacent codes. A
specified differential nonlinearity of ± 1 LSB maximum ensures
monotonicity.
Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital inputs of the same
DAC, but is measured when the DAC is not updated. It is
specified in nV-s and measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa.
ZERO CODE ERROR
Zero code error is the measured output voltage from VOUT of
either DAC when zero code (all zeros) is loaded to the DAC
latch. It is due to a combination of the offset errors in the DAC
and output amplifier. Zero-scale error is expressed in LSBs.
DIGITAL CROSSTALK
GAIN ERROR
ANALOG CROSSTALK
This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale value. Gain error is calculated between Codes 15 and 245.
Analog crosstalk is a change in output of any DAC in response
to a change in the output of the other DAC. It is measured in
LSBs.
Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a digital code change to another DAC.
It is specified in nV-s.
POWER SUPPLY REJECTION RATIO (PSRR)
FULL-SCALE ERROR
Full-Scale Error is a measure of the output error when the DAC
latch is loaded with FF Hex. Full-scale error includes the offset
error.
REV. 0
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
rejection ratio is quoted in terms of % change in output per %
of change in VDD for full-scale output of the DAC. VDD is varied
± 10%. This specification applies to an external reference only
because the output voltage will track the VDD voltage when internal reference is selected.
–5–
AD7303–Typical Performance Characteristics
5
3.5
4.92
3.25
800
640
480
VOUT – Volts
400
320
249
80
0
2
4
6
SINK CURRENT – mA
8
Figure 3. Output Sink Current Capability with VDD = 3 V and VDD = 5 V
4.6
4.52
2.5
2.25
1.5
1.25
1
8
1
2
3
4
5
6
SOURCE CURRENT – mA
7
8
Figure 5. Output Source Current
Capability with VDD = 3 V
5.5
5
LOGIC INPUTS = VIH OR VIL
4
IDD – mA
INL ERROR
0.25
0.2
3.5
INTERNAL REFERENCE
VDD = +5V
INTERNAL REFERENCE
TA = 25°C
4
LOGIC INPUTS = VIH OR VIL
3.5
3
3
DNL ERROR
2.5
0.1
LOGIC INPUTS = VDD OR GND
2.5
2
0.05
LOGIC INPUTS = VDD OR GND
2
–60 –40 –20
1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
REFERENCE VOLTAGE – Volts
Figure 6. Relative Accuracy vs.
External Reference
1.5
2.5
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 7. Supply Current vs.
Temperature
SYNC
1
–5
–10
T
VDD = +3V
INTERNAL VOLTAGE REFERENCE
FULL SCALE CODE CHANGE 00H-FFH
TA = 25°C
3.5
4
4.5
VDD – Volts
5.5
5
POWER UP TIME
VDD = +5V
INTERNAL REFERENCE
BOTH DACS IN POWER DOWN INITIALLY
5
0
3
Figure 8. Supply Current vs.
Supply Voltage
10
ATTENUATION – dB
0
4.5
0.3
0
1
VDD = +3V
INTERNAL REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = 25°C
2
1.75
4.44
4.5
0.35
ERROR – LSBs
4.68
5
VDD = +5V
TA = 258C
0.4
0.15
2.75
Figure 4. Output Source Current
Capability with VDD = 5 V
0.5
0.45
3
4.76
VDD = +5V
4.36 INTERNAL REFERENCE
DAC REGISTER LOADED WITH FFHEX
4.28
TA = 25°C
4.2
0
2
4
6
SOURCE CURRENT – mA
160
0
4.84
IDD – mA
VOUT – mV
560
VOUT – Volts
VDD = +5V AND +3V
INTERNAL REFERENCE
TA = 258C
DAC LOADED WITH 00HEX
720
SYNC
2
2
–15
VDD = +5V
EXTERNAL SINE WAVE REFERENCE
DAC REGISTER LOADED WITH FFHEX
TA = 25°C
–20
–25
VOUT
VOUT
VOUT
–30
1
–35
–40
3
1
10
100
1000
FREQUENCY – kHz
10000
Figure 9. Large Scale Signal
Frequency Response
CH1 5V, CH2 1V, CH3 20mV
TIME BASE = 200ns/div
Figure 10. Full-Scale Settling Time
–6–
CH1 = 2V/div, CH2 = 5V/div,
TIME BASE = 2µs/div
Figure 11. Exiting Power-Down (Full
Power-Down)
REV. 0
AD7303
7
SYNC
2
6
DAC B EXITING
POWER DOWN
VOUT B
SYNC
1
5
DAC A = NORMAL OPERATION←
DAC B INITIALLY IN POWER
DOWN
IDD – mA
T
VDD = +5V
INTERNAL REFERENCE
TA = 258C
4
VDD = +5V
VDD = +5V
INTERNAL VOLTAGE
REFERENCE
10 LSB STEP CHANGE
TA = 258C
VOUT
3
2
1
VDD = +3V
1
2
0
CH1 2V, CH2 5V, M 500ns
0
INL ERROR – LSB
0.3
0.2
DAC A
0.1
0
–0.1
DAC B
–0.2
INL ERROR – LSB
VDD = +5V
INTERNAL REFERENCE
5kΩ 100pF LOAD
LIMITED CODE RANGE (10-245)
TA = 25°C
1.5
2
2.5
3
3.5
4
4.5
CH1 5.00V, CH2 50.0mV, M 250ns
5
Figure 14. Small Scale Settling
Time
Figure 13. Supply Current vs.
Logic Input Voltage
0.5
0.4
1
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0
DNL ERROR – LSB
Figure 12. Exiting Power-Down
(Partial Power-Down)
0.5
VDD = +5V
INTERNAL REFERENCE
–0.1
–0.2
0.1
0
VDD = +5V
INTERNAL REFERENCE
–0.1
–0.2
–0.3
–0.3
–0.3
–0.4
–0.4
–0.4
–0.5
–0.5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE – 8C
–0.5
–60 –40 –20
0
32
64
96
128 160 192 224 255
Input Code (10 to 245)
Figure 15. Integral Linearity Plot
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
Figure 17. Typical DNL vs.
Temperature
Figure 16. Typical INL vs.
Temperature
500
POWER-DOWN CURRENT – nA
INT REFERENCE ERROR – 6%
1.0
0.8
VDD = +5V
0.6
0.4
VDD = +5.5V
VIL AND VIH = 0V OR VDD
300
200
100
0.2
0
–60 –40 –20
0
–50 –25
0 20 40 60 80 100 120 140
TEMPERATURE – 8C
0
25
50
75 100 125
TEMPERATURE – 8C
150
Figure 19. Power-Down Current vs.
Temperature
Figure 18. Typical Internal Reference
Error vs. Temperature
REV. 0
400
–7–
AD7303
reference appears at the reference pin as an output voltage for
decoupling purposes. When using the internal reference, external
references should not be connected to the REF pin. If external reference is selected, both switches are open and the externally
applied voltage to the REF pin is applied to the reference amplifier.
GENERAL DESCRIPTION
D/A Section
The AD7303 is a dual 8-bit voltage output digital-to-analog
converter. The architecture consists of a reference amplifier and
a current source DAC, followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of
the DAC. Figure 20 shows a block diagram of the basic DAC
architecture.
VDD
AD7303
REFERENCE
AMPLIFIER
Decoupling capacitors applied to the REF pin decouple both
the internal reference and external reference. In noisy environments it is recommended that a 0.1 µF capacitor be connected
to the REF pin to provide added decoupling even when the internal reference is selected.
11.7kΩ
Analog Outputs
30kΩ
CURRENT
DAC
REF
11.7kΩ
30kΩ
The AD7303 contains two independent voltage output DACs
with 8-bit resolution and rail-to-rail operation. The output buffer
provides a gain of two at the output. Figures 3 to 5 show the sink
and source capabilities of the output amplifier. The slew rate of the
output amplifier is typically 8 V/µs and has a full-scale settling to 8
bits with a 100 pF capacitive load in typically 1.2 µs.
VO A/B
OUTPUT
AMPLIFIER
The input coding to the DAC is straight binary. Table I shows
the binary transfer function for the AD7303. Figure 22 shows
the DAC transfer function for binary coding. Any DAC output
voltage can ideally be expressed as:
Figure 20. DAC Architecture
Both DAC A and DAC B outputs are internally buffered and
these output buffer amplifiers have rail-to-rail output characteristics. The output amplifier is capable of driving a load of 10 kΩ
to both VDD and ground and 100 pF to ground. The reference
selection for the DAC can be either internally generated from
V DD or externally applied through the REF pin. Reference
selection is via a bit in the control register. The range on the
external reference input is from 1.0 V to VDD/2. The output
voltage from either DAC is given by:
VOUT = 2 × VREF (N/256)
where:
N
VREF
VO A/B = 2 × VREF × (N/256)
where:
VREF is the voltage applied to the external REF pin or
VDD/2 when the internal reference is selected.
N
is the decimal equivalent of the code loaded to the DAC
register and ranges from 0 to 255.
Table I. Binary Code Table for AD7303 DAC
Digital Input
MSB . . . LSB
1111 1111
1111 1110
1000 0001
1000 0000
0111 1111
0000 0001
0000 0000
Reference
The AD7303 has the facility to use either an external reference
applied through the REF pin or an internal reference generated
from VDD. Figure 21 shows the reference input arrangement
where the internal VDD/2 has been selected.
VDD
30kΩ
AD7303
Analog Output
2 × 255/256 × VREF V
2 × 254/256 × VREF V
2 × 129/256 × VREF V
VREF V
2 × 127/256 × VREF V
2 × VREF/256 V
0V
2.VREF
INT/EXT
DAC OUTPUT VOLTAGE
REF
0.1µF
30kΩ
is the decimal equivalent of the binary input code.
N ranges from 0 to 255.
is the voltage applied to the external REF pin when
the external reference is selected and is VDD/2 if the
internal reference is used.
REFERENCE
AMPLIFIER
VREF
Figure 21. Reference Input
When the internal reference is selected during the write to the
DAC, both switches are closed and VDD/2 is generated and
applied to the reference amplifier. This internal VDD/2 reference
appears at the reference pin as an output voltage for decoupling
purposes. When using the internal reference, external references
should not be connected to the REF Pin. This internal VDD/2
0
DAC INPUT
CODE
00
01
7F
80
81
FE
FF
Figure 22. DAC Transfer Function
–8–
REV. 0
AD7303
SERIAL INTERFACE
The AD7303 contains a versatile 3-wire serial interface that is
compatible with SPI, QSPI and Microwire interface standards as well as a host of digital signal processors. An active
low SYNC enables the shift register to receive data from the
serial data input DIN. Data is clocked into the shift register on
the rising edge of the serial clock. The serial clock frequency
can be as high as 30 MHz. This shift register is 16 bits wide as
shown in Figures 23 and 24. The first eight bits are control bits
and the second eight bits are data bits for the DACs. Each
transfer must consist of a 16-bit transfer. Data is sent MSB first
and can be transmitted in one 16-bit write or two 8-bit writes.
SPI and Microwire interfaces output data in 8-bit bytes and
thus require two 8-bit transfers. In this case the SYNC input to
the DAC should remain low until all sixteen bits have been
transferred to the shift register. QSPI interfaces can be pro-
MSB
INT/EXT
The input shift register is 16 bits wide. The first eight bits consist of control bits and the last eight bits are data bits. Figure 23
shows a block diagram of the logic interface on the AD7303
DAC. The seven bits in the control word are taken from the input shift register to a latch sequencer that decodes this data and
provides output signals that control the data transfers to the input and data registers of the selected DAC, as well as output
updating and various power-down features associated with the
control section. A description of all bits contained in the input
shift register is given below.
DAC A BIAS
DAC B POWER-DOWN
LATCH
SEQUENCER
LDAC
BANDGAP
BIAS GEN
BANDGAP POWER-DOWN
7
DAC B BIAS
REF
SELECTOR
LATCH & CLK
DRIVERS
PDA
16-BIT SHIFT REGISTER
INPUT SHIFT REGISTER DESCRIPTION
DAC A POWER-DOWN
SYNC
X
PDB
grammed to transfer data in 16-bit words. After clocking all sixteen bits to the shift register, the rising edge of SYNC executes
the programmed function. The DACs are double buffered
which allows their outputs to be simultaneously updated.
A/B
INT
REFERENCE
CURRENT
SWITCH
16
CR1
CLOCK BUS
CR0
REF
RESISTOR
SWITCH
DB7
8
DB6
INPUT
REGISTER
8
8 TO 32
DECODER
30
DAC
REGISTER
30
DAC A
VOUT A
DAC B
VOUT B
DB5
DB4
8
DB3
DB2
DB1
LSB
8
INPUT
REGISTER
8
8 TO 32
DECODER
30
DAC
REGISTER
DB0
SYNC
SCLK
DIN
Figure 23. Logic Interface on the AD7303
REV. 0
–9–
30
AD7303
DB15 (MSB)
INT/EXT
X
LDAC
PDB
PBA
A/B
CR1
CR0
DB7
DB6
DB5
DB4
DB3
DB2
DB0 (LSB)
DB1
DB0
|––––––––––––––––––––––––– Control Bits –––––––––––––––––––––––––|––––––––––––––––––––––––– Data Bits –––––––––––––––––––––––––|
Figure 24. Input Shift Register Contents
Bit Location
Mnemonic
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7–DB0
Description
Selects between internal and external reference.
Uncommitted bit.
Load DAC bit for synchronous update of DAC outputs.
Power-down DAC B.
Power-down DAC A.
Address bit to select either DAC A or DAC B.
Control Bit 1 used in conjunction with CR0 to implement the various data loading functions.
Control Bit 0 used in conjunction with CR1 to implement the various data loading functions.
These bits contain the data used to update the output of the DACs. DB7 is the MSB and
DB0 the LSB of the 8-bit data word.
INT/EXT
X
LDAC
PDB
PDA
A/B
CR1
CR0
Data
CONTROL BITS
LDAC
A/B
CR1
CR0
Function Implemented
0
0
0
0
0
0
0
1
X
0
1
0
1
0
1
0
0
0
0
1
1
1
1
X
0
1
1
0
0
1
1
X
1
1
X
X
Both DAC registers loaded from shift register.
Update DAC A input register from shift register.
Update DAC B input register from shift register.
Update DAC A DAC register from input register.
Update DAC B DAC register from input register.
Update DAC A DAC register from shift register.
Update DAC B DAC register from shift register.
Load DAC A input register from shift register and update
both DAC A and DAC B DAC registers.
Load DAC B input register from shift register and update
both DAC A and DAC B DAC registers outputs.
INT/EXT
Function
0
1
Internal VDD/2 reference selected.
External reference selected; this external reference is applied at the REF pin and ranges from
1 V to VDD/2.
PDA
PDB
Function
0
0
1
1
0
1
0
1
Both DACs active.
DAC A active and DAC B in power-down mode.
DAC A in power-down mode and DAC B active.
Both DACs powered down.
–10–
REV. 0
AD7303
POWER-ON RESET
AD7303 to 68HC11/68L11 Interface
The AD7303 has a power-on reset circuit designed to allow output
stability during power-up. This circuit holds the DACs in a reset
state until a write takes place to the DAC. In the reset state all zeros
are latched into the input registers of each DAC, and the DAC registers are in transparent mode. Thus the output of both DACs are
held at ground potential until a write takes place to the DAC.
Figure 27 shows a serial interface between the AD7303 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the CLKIN of the AD7303, while the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/
68L11 should be configured so that its CPOL bit is a 0 and its
CPHA bit is a 0. When data is being transmitted to the DAC,
the SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as above, data appearing on the MOSI output is
valid on the rising edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. In order to load data to the AD7303, PC7 is left low after
the first eight bits are transferred, and a second serial write operation is performed to the DAC and PC7 is taken high at the
end of this procedure.
POWER-DOWN FEATURES
Two bits in the control section of the 16-bit input word are used to
put the AD7303 into low power mode. DAC A and DAC B can be
powered down separately. When both DACs are powered down,
the current consumption of the device is reduced to less than 1 µA,
making the device suitable for use in portable battery powered
equipment. The reference bias servo loop, the output amplifiers
and associated linear circuitry are all shut down when the powerdown is activated. The output sees a load of approximately 23 kΩ
to GND when in power-down mode as shown in Figure 25. The
contents of the data registers are unaffected when in power-down
mode. The time to exit power-down is determined by the nature of
the power-down, if the device is fully powered down the bias generator is also powered down and the device takes typically 13 µs to
exit power-down mode. If the device is only partially powered
down, i.e., only one channel powered down, in this case the bias
generator is active and the time required for the power-down channel to exit this mode is typically 1.6 µs. See Figures 11 and 12.
68HC11/68L11*
PC7
SCK
SCLK
MOSI
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
VDD
11.7kΩ
Figure 27. AD7303 to 68HC11/68L11 Interface
AD7303 to 80C51/80L51 Interface
IDAC
VO A/B
11.7kΩ
VREF
Figure 25. Output Stage During Power-Down
MICROPROCESSOR INTERFACING
AD7303 to ADSP-2101/ADSP-2103 Interface
Figure 26 shows a serial interface between the AD7303 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT Transmit Alternate Framing
Mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: Internal Clock Operation, Active Low Framing,
16-Bit Word Length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled. The data
is clocked out on each falling edge of the serial clock and clocked
into the AD7303 on the rising edge of the SCLK.
ADSP-2101/
ADSP-2103*
Figure 28 shows a serial interface between the AD7303 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TXD of the 80C51/80L51 drives SCLK of the AD7303,
while RXD drives the serial data line of the part. The SYNC
signal is again derived from a bit programmable pin on the port.
In this case port line P3.3 is used. When data is to be transmitted to the AD7303, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format which has the LSB
first. The AD7303 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.
AD7303*
TFS
DT
SCLK
SYNC
80C51/80L51*
AD7303*
P3.3
SYNC
TXD
SCLK
RXD
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
Figure 28. AD7303 to 80C51/80L51 Interface
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. AD7303 to ADSP-2101/ADSP-2103 Interface
REV. 0
AD7303*
SYNC
–11–
AD7303
AD7303 to Microwire Interface
Bipolar Operation Using the AD7303
Figure 29 shows an interface between the AD7303 and any
microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the AD7303
on the rising edge of the SK.
The AD7303 has been designed for single supply operation, but
bipolar operation is achievable using the circuit shown in Figure
31. The circuit shown has been configured to achieve an output
voltage range of –5 V < VO < +5 V. Rail-to-rail operation at the
amplifier output is achievable using an AD820 or OP295 as the
output amplifier.
MICROWIRE*
AD7303*
VDD = +5V
SYNC
CS
SK
SCLK
SO
DIN
R4
20kΩ
0.1µF
10µF
+5V
R3
10kΩ
±5V
VIN
*ADDITIONAL PINS OMITTED FOR CLARITY
EXT
REF
Figure 29. AD7303 to Microwire Interface
REF
0.1µF
AD7303
VDD = +3V TO +5V
0.1µF
10µF
VDD
REF
VOUTA
0.1µF
AD7303
SCLK
VOUTB
DIN
AD780/ REF192
WITH VDD = +5V
OR
AD589 WITH VDD = +3V
SYNC
DIN
R2
20kΩ
SYNC
GND
SERIAL
INTERFACE
Figure 31. Bipolar Operation Using the AD7303
The output voltage for any input code can be calculated as
follows:
VO = [(1+R4/R3)*(R2/(R1+R2)*(2*VREF*D/256)] – R4*VREF/R3
where
D is the decimal equivalent of the code loaded to the DAC
and
VREF is the reference voltage input.
VIN
VOUT
AD780/ REF192
WITH VDD = +5V
OR
AD589 WITH VDD = +3V
–5V
R1
10kΩ
VOUTA
SCLK
Figure 30 shows a typical setup for the AD7303 when using an
external reference. The reference range for the AD7303 is from
1 V to VDD/2 V. Higher values of reference can be incorporated
but will saturate the output at both the top and bottom end of
the transfer function. From input to output on the AD7303
there is a gain of two. Suitable references for 5 V operation are
the AD780 and REF192. For 3 V operation, a suitable external
reference would be the AD589, a 1.23 V bandgap reference.
GND
VOUT
GND
APPLICATIONS
Typical Application Circuit
EXT
REF
VDD
GND
SERIAL
INTERFACE
Figure 30. AD7303 Using External Reference
The AD7303 can also be used with its own internally derived
VDD/2 reference. Reference selection is through the INT/EXT
bit of the 16-bit input word. The internal reference, when
selected, is also provided as an output at the REF pin and can
be decoupled at this point with a 0.1 µF capacitor for noise
reduction purposes. AC references can also be applied as external references to the AD7303. The AD7303 has limited multiplying capability, and a multiplying bandwidth of up to 10 kHz
is achievable.
With VREF = 2.5 V, R1 = R3 = 10 kΩ and R2 = R4 = 20K and
VDD = 5 V.
VOUT = (10 × D/256) – 5
Opto-Isolated Interface for Process Control Applications
The AD7303 has a versatile 3-wire serial interface making it
ideal for generating accurate voltages in process control and
industrial applications. Due to noise, safety requirements or distance, it may be necessary to isolate the AD7303 from the controller. This can easily be achieved by using opto-isolators,
which will provide isolation in excess of 3 kV. The serial loading
structure of the AD7303 makes it ideally suited for use in optoisolated applications. Figure 32 shows an opto-isolated interface
to the AD7303 where DIN, SCLK and SYNC are driven from
opto-couplers. In this application the reference for the AD7303
is the internal VDD/2 reference. It is being decoupled at the REF
pin with a 0.1 µF ceramic capacitor for noise reduction purposes.
–12–
REV. 0
AD7303
AD7303 as a Digitally Programmable Window Detector
+5V
REGULATOR
10µF
POWER
A digitally programmable upper/lower limit detector using the
two DACs in the AD7303 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B which,
in turn, set the limits on the CMP04. If a signal at the VIN input
is not within the programmed window, a led will indicate the fail
condition.
0.1µF
VDD
10kΩ
VDD
SCLK
SCLK
REF
0.1µF
+5V
AD7303
VDD
0.1µF
10µF
VOUTA
SYNC
SYNC
VOUTA
VOUTB
AD7303
DATA
VOUTB
SCLK
SCLK
AGND
PASS/FAIL
DIN
DIN
DIN
1/2
CMP04
SYNC
SYNC
10kΩ
1kΩ
PASS
VDD
REF
0.1µF
VDD
1kΩ
FAIL
VIN
10kΩ
1/6 74HC05
GND
Figure 32. AD7303 in Opto-Isolated Interface
Figure 34. Window Detector Using AD7303
Decoding Multiple AD7303
Programmable Current Source
The SYNC pin on the AD7303 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same serial clock and serial data, but only the
SYNC to one of the DACs will be active at any one time allowing access to two channels in this eight-channel system. The
74HC139 is used as a 2- to 4-line decoder to address any of the
DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 33 shows a diagram of a typical setup for decoding multiple AD7303 devices in
a system.
Figure 35 shows the AD7303 used as the control element of a
programmable current source. In this circuit, the full-scale current is set to 1 mA. The output voltage from the DAC is applied
across the current setting resistor of 4.7 kΩ in series with the
full-scale setting resistor of 470 Ω. Suitable transistors to place
in the feedback loop of the amplifier include the BC107 and the
2N3904, which enable the current source to operate from a min
VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail
operation on their outputs. The current for any digital input
code can be calculated as follows:
I = 2 × VREF × D/(5E + 3 × 256) mA
AD7303
SCLK
SYNC
VDD = +5V
DIN
DIN
VDD
SCLK
0.1µF
VCC
ENABLE
CODED
ADDRESS
1G
1Y0
1A
1Y1
1Y2
1B
74HC139
1Y3
10µF
VSOURCE
AD7303
VIN
SYNC
DIN
SCLK
+5V
VDD
EXT
REF
VOUT
GND
REF
0.1µF
AD7303
DGND
AD820/
OP295
SCLK
AD7303
AD780/ REF192
WITH VDD = +5V
SYNC
4.7kΩ
DIN
SYNC
GND
DIN
SCLK
SERIAL
INTERFACE
AD7303
SYNC
Figure 35. Programmable Current Source
DIN
SCLK
Figure 33. Decoding Multiple AD7303 Devices in a System
REV. 0
–13–
LOAD
VOUTA
470Ω
AD7303
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7303 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD7303 is in a system where multiple
devices require an AGND to DGND connection, the connection should be made at one point only. The star ground point
should be established as closely as possible to the AD7303. The
AD7303 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as closely to the package as
possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should
have low Effective Series Resistance (ESR) and Effective Series
Inductance (ESI), like the common ceramic types that provide a
low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
The power supply lines of the AD7303 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane while signal traces are placed on the solder side.
AD7303 to 68HC11 Interface Program Source Code
*
PORTC
EQU
$1003
*
Port C Control Register
"SYNC, 0, 0, 0, 0, 0, 0, 0"
DDRC
EQU
$1007
Port C Data Direction
PORTD
EQU
$1008
Port D Data Register
*
"0, 0, 0, SCLK, DIN, 0, 0, 0"
DDRD
EQU
$1009
Port D Data Direction
SPCR
EQU
$1028
SPI Control Register
EQU
$1029
SPI Status Register
*
SPSR
"SPIE, SPE, DWOM, MSTR, CPOL, CPHA, SPR1, SPR0"
*
SPDR
"SPIF, WCOL, 0, MODF, 0, 0, 0, 0"
EQU
$102A
SPI Data Register, Read Buffer, Write Shifter
*
* SDI RAM Variables:
DIN 1 is eight MSBs, Control BYTE
DIN 2 is eight LSBs, Data BYTE
DAC requires 2*8-bit Writes
DIN1
EQU
$00
DIN BYTE 1: " INT/EXT, X, LDAC, PDB, PBA, A/B, CR1, CR0"
DIN2
EQU
$01
DIN BYTE 2: " DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0"
ORG
$C000
Start of users ram
LDS
#$CFFF
Top of C page Ram
LDAA
#$80
1, 0, 0, 0, 0, 0, 0, 0
*
INIT
*
*
SYNC is High
STAA
PORTC
Initialize Port C Outputs
LDAA
#$80
1, 0, 0, 0, 0, 0, 0, 0
STAA
DDRC
SYNC enabled as output
LDAA
#$00
0, 0, 0, 0, 0, 0, 0, 0
*
*
SCLK is low, DIN is low
STAA
PORTD
Initialize Port D outputs
–14–
REV. 0
AD7303
LDAA
#$18
*
0, 0, 0, 1, 1, 0, 0, 0
SCLK and DIN enabled as outputs
LDAA
#$53
STAA
SPCR
SPI on, Master mode, CPOL=0, CPHA=0, Clock rate =E/32
BSR
UPDATE
Update AD7303 output.
JMP
#$E000
Restart.
*
*
UPDATE
PSHX
Save relevant registers.
PSHY
PSHA
*
LDAA
#$00
Control Word "0, 0, 0, 0, 0, 0, 0, 0"
STAA
DIN 1
Load both DAC A and DAC B DAC registers from shift register
with internal reference selected.
LDAA
#$AA
Data Word "1, 0, 1, 0, 1, 0, 1, 0"
STAA
DIN 2
LDX
#DIN1
Stack pointer at first first byte to send via DIN 1.
LDY
#$1000
Stack pointer at on chip registers.
BCLR
PORTC,Y $80
Assert SYNC.
LDAA
0,X
Get BYTE to transfer via SPI.
STAA
SPDR
Write to DIN register to start transfer.
LDAA
SPSR
Wait for SPIF to be set to indicate that transfer has been completed.
BPL
WAIT
SPIF is the MSB of the SPCR. SPIF is automatically reset if in a set
state when the status register is read.
*
*
TRANSFER
*
WAIT
*
INX
Increment counter for transfer of second byte.
CPX
#DIN 2+1
16 bits transferred?
BNE
TRANSFER
If not, transfer second BYTE.
PORTC,Y $80
Bring SYNC back high.
*Execute instruction
BSET
PULA
Restore registers.
PULY
PULX
RTS
REV. 0
Return to main program.
–15–
AD7303
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP
(N-8)
8
C2224–12–1/97
0.430 (10.92)
0.348 (8.84)
5
0.280 (7.11)
0.240 (6.10)
1
4
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
8-Lead microSOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
4
PIN 1
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
PRINTED IN U.S.A.
0.0256 (0.65) BSC
0.018 (0.46)
0.008 (0.20)
0.011 (0.28)
0.003 (0.08)
–16–
33°
27°
0.028 (0.71)
0.016 (0.41)
REV. 0