CXP84412/84416 CMOS 8-bit Single Chip Microcomputer Description The CXP84412/84416 is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, 32kHz timer/counter, remote control reception circuit and other servo systems besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port. The CXP84412/84416 also provides and a sleep/ stop function that enables lower power consumption. 80 pin QFP (PIastic) Features • Wide-range instruction system (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions • Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation • Incorporated ROM capacity 12Kbytes (CXP84412) 16Kbytes (CXP84416) • Incorporated RAM capacity 448bytes • Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 2 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter — Remote control reception circuit Incorporated 6-stage FIFO 8-bit measurement counter — PWM output for tuner 14 bits • Interruption 12 factors, 12 vectors, multi-interruption possible • Standby mode SLEEP/STOP • Package 80-pin plastic QFP • Piggyback/evaluation chip CXP84400 80-pin ceramic QFP Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E93909-ST PE5/ADJ 8 BIT TIMER 1 FIFO FIFO PE5/TO SERIAL INTERFACE UNIT 0 REMOCON 14 BIT PWM GENERATOR A/D CONVERTER AVss 8 BIT TIMER/COUNTER 0 8 2 2 PI0/INT0 PI1/INT1 PI2/INT2 PI3/INT3 INTERRUPT CONTROLLER AVREF PE0/EC PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 PB0/CS1 PB6/SI1 PB7/SO1 PB5/SCK1 PE2/RMC PE4/PWM AN0 to AN7 PRESCALER/ TIME BASE TIMER ROM 12K/16K BYTES SPC700 CPU CORE TEX TX EXTAL XTAL RST VDD Vss 32kHz TIMER/COUNTER RAM 448 BYTES CLOCK GEN./ SYSTEM CONTROL PORT E PORT D PORT C PORT B PORT A PORT H PORT G PORT F –2– PORT I Block Diagram PF0 to PF7 PG0 to PG7 PH0 to PH7 8 8 8 PI0 to PI7 PE4 to PE5 2 8 PE0 to PE3 PD0 to PD7 PC0 to PC7 PB0 to PB7 PA0 to PA7 4 8 8 8 8 CXP84412/84416 PE3/NMI CXP84412/84416 PI5 PI6 PI7 PG0 PG1 PG2 PG3 VDD NC PG4 PG5 PG6 PG7 PF0 PF1 PF2 Pin Assignment (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PF3 1 64 PI4 PF4 2 63 PI3/INT3 PF5 3 62 PI2/INT2 PF6 4 61 PI1/INT1 PF7 5 60 PI0/INT0 PD0 6 59 PE5/TO/ADJ PD1 7 58 PE4/PWM PD2 8 57 PE3/NMI PD3 9 56 PE2/RMC PD4 10 55 PE1 PD5 11 54 PE0/EC PD6 12 53 PB7/SO1 PD7 13 52 PB6/SI1 PC0 14 51 PB5/SCK1 PC1 15 50 PB4/SO0 PC2 16 49 PB3/SI0 PC3 17 48 PB2/SCK0 PC4 18 47 PB1/CS0 PC5 19 46 PB0/CS1 PC6 20 45 PA7/AN7 PC7 21 44 PA6/AN6 PH0 22 43 PA5/AN5 PH1 23 42 PA4/AN4 PH2 24 41 PA3/AN3 Note) NC (Pin 73) must be connected to VDD. –3– PA2/AN2 PA1/AN1 AVREF PA0/AN0 AVSS TEX TX VSS XTAL EXTAL PH7 RST PH6 PH5 PH4 PH3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CXP84412/84416 Pin Description Pin code I/O PA0/AN0 to PA7/AN7 I/O/analog input PB0/CS1 I/O/input PB1/CS0 I/O/input PB2/SCK0 I/O/I/O PB3/SI0 I/O/input PB4/SO0 I/O/output PB5/SCK1 I/O/input/output PB6/SI1 I/O/input PB7/SO1 I/O/output Functions (Port A) 8-bit I/O port. I/O can be set in single bit units. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) Chip select input for serial interface (CH1). (Port B) 8-bit I/O port. I/O can be set in single bit units. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). I/O (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) PE0/EC Input/input PC0 to PC7 PE1 Input PE2/RMC Input/input PE3/NMI Input/input PE4/PWM Output/output PE5/TO/ADJ Output/output/ output PF0 to PF7 I/O External event inputs for timer/counter. (Port E) 6-bit port. Lower 4 bits are for inputs; upper 2 bits are for outputs. Incorporation of pull-up resistor can be set through the software. (8 pins) Remote control reception circuit input. Non-maskable interruption request input. 14-bit PWM output. Rectangular wave output for 16-bit timer/ counter (duty output 50%). Output for 32kHz oscillation frequency demultiplication. (Port F) 8-bit output port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) –4– CXP84412/84416 Pin code PG0 to PG7 PH0 to PH7 I/O Functions I/O (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) I/O (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pullup resistor can be set through the software in a unit of 4 bits. (8 pins) (Port I) 8-bit output ports. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. PI0/INT0 to PI3/INT3 I/O/input PI4 to PI7 I/O EXTAL Input XTAL Output TEX Input TX Output Crystal connectors for 32kHz timer/counter clock generation circuit. Connect a 32.768kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and open TX. RST Input Low-level active, system reset. NC. Under normal operating conditions, connect to VDD. NC AVREF Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Input Reference voltage input for A/D converter. AVss A/D converter GND. VDD Vcc supply. Vss GND –5– CXP84412/84416 I/O Circuit Format for Pins Pin Port A AAAA AAAA AAAA AAAA AAAA AAA AAA AAA AAA AAA Circuit format ∗ Pull-up resistance "0" when reset AA AAAA Port A data PA0/AN0 to PA7/AN7 When reset Port A direction IP "0" when reset Input protection circuit Hi-Z Data bus RD (Port A) Port A input selection Input multiplexer "0" when reset A/D converter 8 pins Port B ∗ Pull-up resistance "0" when reset AA AA AA AA Port B data PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1 Port B direction IP "0" when reset 4 pins Port B CS1 CS0 SI0 SI1 ∗ Pull-up transistors approx. 100kΩ AAAA AAAA AAAA AAAA AAAA AAAA ∗ Pull-up resistance "0" when reset SCK OUT Output enable AA AAAA Port B output selection "0" when reset PB2/SCK0 PB5/SCK1 IP Port B data Port B direction "0" when reset Data bus Schmitt input RD (Port B) 2 pins Hi-Z Schmitt input Data bus RD (Port B) ∗ Pull-up transistors approx. 100kΩ ∗ Pull-up transistors approx. 100kΩ SCK0 in SCK1 –6– Hi-Z CXP84412/84416 Pin Circuit format Port B When reset AAAA AAAA AAAA AAAA AAAA AAAA ∗ Pull-up resistance AA AAAA SO Output enable Port B output selection "0" at reset PB4/SO0 PB7/SO1 IP Port B data Port B direction Hi-Z "0" when reset Data bus RD (Port B) ∗ Pull-up transistors approx. 100kΩ 2 pins Port C AAAA AAAA AAAA AAAA ∗2 Pull-up resistance "0" when reset AA AAAA Port C data PC0 to PC7 ∗1 Port C direction "0" when reset Data bus RD (Port C) of 12mA possible Port E PE0/EC PE1 PE2/RMC PE3/NMI AA AA AAAA EC RMC/NMI IP Note : PE1 No schmitt input. Port E AAAA AAAA AAAA PWM Port E output selection "0" when reset Port E data 1 pin approx. 100kΩ Schmitt input 4 pins PE4/PWM ∗2 Pull-up transistors ∗1 High current drive 8 pins Hi-Z IP Data bus "1" when reset RD (Port E) –7– Data bus Hi-Z RD (Port E) AA AA H level CXP84412/84416 Pin Circuit format AA AAA AA AAA AAA AAA AAA When reset Port E PE5/TO/ADJ Output enable TO ADJ16K ADJ2K Port E output selection Port E output selection "00" when reset MPX AA AA Port E output selection "0" when reset Port E data 1 pin ∗ ADJ signals are frequency division outputs for 32kHz oscillation frequency adjustment ADJ2K provides usage as buzzer output. "1" when reset Data bus RD (Port B) Port D Port F Port G AAAA AAAA AAAA AAAA Port H Port I ∗ Pull-up resistance "0" when reset PD0 to PD7 PF0 to PF7 PG0 to PG7 PH0 to PH7 PI4 to PI7 H level Port data Port direction "0" when reset AA AAAA IP Hi-Z Data bus RD ∗ Pull-up transistors approx. 100kΩ 36 pins Port I AAAA AAAA AAAA AAAA ∗ Pull-up resistance "0" when reset Port data PI0/INT0 to PI3/INT3 Port direction "0" when reset AA AAAA IP Data bus RD 4 pins INT0 INT1 INT2 INT3 –8– Schmitt input ∗ Pull-up transistors approx. 100kΩ Hi-Z CXP84412/84416 Pin EXTAL XTAL 2 pins TEX TX 2 pins RST 1 pin Circuit format AA AA A AA AA AA A AA IP EXTAL When reset • Diagram shows circuit composition during oscillation. IP • Feedback resistor is removed during stop, and XTAL becomes "High". Oscillation XTAL IP TEX • Digram shows circuit circuit composition during oscillation. IP • When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively. TX AA AA Pull-up resistor OP AA Mask option IP –9– Schmitt input Oscillation Hi-z or L level (When pull-up resistance is added) CXP84412/84416 Absolute Maximum Ratings (Vss = 0V reference) Item Symbol Supply voltage Ratings Unit VDD –0.3 to +7.0 V AVSS V Remarks Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗1 Output voltage VOUT –0.3 to +7.0∗1 V High level output current IOH –5 mA Output per pin High level total output current ∑IOH –50 mA Total for all output pins IOL 15 mA IOLC 20 mA Value per pin, excluding high current outputs Value per pin∗2 for high current outputs Low level total output current ∑IOL 100 mA Total for all output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW Low level output current V ∗1 VIN and VOUT must not exceed VDD + 0.3V. ∗2 The high current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions Item Supply voltage High level input voltage Symbol Min. Max. 4.5 5.5 3.5 5.5 2.7 5.5 Guaranteed operation range with TEX clock 2.5 5.5 VIH 0.7VDD VDD V Guaranteed data hold range during STOP ∗2 VIHS 0.8VDD VDD V VDD VIHEX Low level input voltage Operating temperature (Vss = 0V reference) Unit V VDD – 0.4 VDD + 0.3 Remarks High speed mode guaranteed operation range∗1 Low speed mode guaranteed operation range∗1 V Hysteresis input∗3 EXTAL∗4 ∗2 VIL 0 0.3VDD V VILS 0 0.2VDD V VILEX –0.3 0.4 V Topr –20 +75 °C Hysteresis input∗3 EXTAL∗4 ∗1 High speed mode is 1/2 frequency demultiplication clock selection; low-speed mode is 1/16 frequency demultiplication clock selection. ∗2 Value for each pin of normal input ports (PA, PB4, PB7, PC, PD, PE1, PF to PH, PI4 to PI7). ∗3 Value of the following pins: RST, CS0, CS1, SCK0, SCK1, SI0, SI1, EC, RMC, NMI, INT0, INT1, INT2, INT3. ∗4 Specifies only during external clock input. – 10 – CXP84412/84416 Electrical Characteristics DC Characteristics Item High level output current Low level output current (Ta = –20 to +75°C, Vss = 0V reference) Symbol Pins VOH PA to PD, PE4, PE5, PF to PI VOL PC IIHE IILE EXTAL IIHT Input current I/O leakage current IILT 3.5 V VDD = 4.5V, IOL = 1.8mA 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIL = 5.5V 0.1 10 µA –0.1 –10 µA –1.5 –400 µA –5.0 µA PA to PD∗2, PF to PI∗2 IIZ PE0 to PE3, VDD = 5.5V, RST∗1 PA to PD∗2, VI = 0, 5.5V PF to PI∗2 VDD = 5.5V, VIL = 0.4V VDD = 4.5V, VIL = 4.0V High-speed mode operation (1/2 frequency demultiplier clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) –3.3 µA ±10 µA 18 40 mA 35 100 µA 1.1 8 mA 9 30 µA 10 µA 20 pF SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) IDDS2 Unit VDD = 4.5V, IOH = –1.2mA IIL IDDS1 Max. V RST∗1 VDD Typ. 4.0 IILR IDD2 Min. VDD = 4.5V, IOH = –0.5mA TEX IDD1 Power supply current∗3 Conditions STOP mode IDDS3 Input capacity CIN VDD = 5.5V, 10MHz crystal oscillation; and termination of 32kHz oscillation Pins other than PE4, PE5, XTAL, TX, AVREF, AVss, VDD, VSS Clock 1MHz 0V for all pins excluding measured pins 10 ∗1 RST specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗2 Pins PA to PD, and PF to PI specifies the input current when pull-up resistance has been selected; leakage current when no resistance has been selected. ∗3 When all pins are open. – 11 – CXP84412/84416 AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol System clock frequency Event count input clock rise time, fall time System clock frequency fC Event count input clock input pulse width tTL, tTH tTR, tTF System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time Conditions Typ. Min. XTAL Fig. 1, Fig. 2 EXTAL fC tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock input pulse width Pin 1 EXTAL Fig. 1, Fig. 2 External clock drive EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 EC Fig. 3 TEX TX VDD=2.7 to 5.5V Fig. 2 (32kHz clock application condition) TEX Fig. 3 TEX Fig. 3 Max. Unit 10 MHz ns 37.5 200 tsys + 50∗ ns ns 20 ms kHz 32.768 µs 10 20 ms ∗ tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF tXL tCR Fig. 2. Clock application conditions AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAAAAAA Crystal oscillation Ceramic oscillation EXTAL C1 XTAL C2 External clock EXTAL 32kHz clock application condition Crystal oscillation TEX XTAL 74HCO4 – 12 – C1 TX C2 CXP84412/84416 Fig. 3. Event count clock timing 0.8VDD TEX EC 0.2VDD tEF tTF tEH tTH tEL tTL tER tTR (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss reference) (2) Serial transfer Item Symbol CS0 ↓ → SCK0 (CS1 ↓ → SCK1) delay time tDCSK CS0 ↑ → SCK0 (CS1 ↑ → SCK1) float delay time tDCSKF SCK0 CS0 ↓ → SO0 (CS1 ↓ → SO1) delay time tDCSO CS0 ↑ → SO0 (CS1 ↑ → SO1) float delay time Pin Condition Min. Max. Unit SCK0 Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) 1.5tsys + 200 ns Chip select transfer mode (SCK1) (SCK0 (SCK1) = output mode) 1.5tsys +200 ns SO0 (SO1) Chip select transfer mode 1.5tsys + 200 ns tDCSOF SO0 Chip select transfer mode 1.5tsys + 200 ns CS0 (CS1) High level width tWHCS CS0 Chip select transfer mode SCK0 (SCK1) cycle time tKCY SCK0 (SCK1) High, Low level width (SO1) tsys + 200 ns SCK0 Input mode (SCK1) Output mode 2tsys + 200 ns 16000/fc ns tKH tKL SCK0 Input mode (SCK1) Output mode tsys + 100 ns 8000/fc – 50 ns SI0 (SI1) input set-up time (for SCK0 ↑ (SCK1 ↑) ) SI0 (SI1) SCK0 (SCK1) input mode 100 ns tSIK SCK0 (SCK1) output mode 200 ns SI0 (SI1) input hold time (for SCK0 ↑ (SCK1 ↑) ) SI0 (SI1) SCK0 (SCK1) input mode tsys + 200 ns tKSI 100 ns SCK0 ↓ → SO0 (SCK1 ↓ → SO1) delay time tKSO SO0 (SO1) SCK0 (SCK1) input mode (CS1) SCK0 (SCK1) output mode SCK0 (SCK1) output mode tsys + 200 ns 100 ns Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL. – 13 – CXP84412/84416 Fig. 4. Serial transfer CH0 timing tWHCS CS0 (CS1) 0.8VDD 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 (SCK1) 0.2VDD tSIK tKSI 0.8VDD Input data SI0 (SI1) 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 (SO1) Output data 0.2VDD – 14 – CXP84412/84416 (3) A/D converter characteristics Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V Pin Condition Min. Typ. Max. Unit 8 Bits ±3 LSB Resolution Linearity error Zero transition voltage VZT∗1 Full-scale transition voltage VFT∗2 Conversion time tCONV tSAMP Sampling time Ta = 25°C VDD = 5.0V VSS = AVSS = 0V AVREF Analog input voltage AN0 to AN7 70 mV 4930 4970 5010 mV AVREF IREFS µs µs VDD – 0.5 VDD V 0 AVREF V 1.0 mA 10 µA 0.6 Operation mode IREF AVREF current 30 160/fADC∗3 12/fADC∗3 Reference input voltage VREF VIAN –10 SLEEP mode STOP mode 32kHz operation mode Fig. 5. Definition of A/D converter terms Digital conversion value FFH FEH ∗1 VZT : Value at which the digital transfer value changes from 00 H to 01H and vice versa. ∗2 VFT : Value at which the digital transfer value changes from FE H to FFH and vice versa. ∗3 fADC indicates the below values due to the contents of bit 6 (CKS) of A/D control resistor (address : 00F9H) and bits 6, 7 (PCK0, 1) of clock control resistor (address : 00FFH). Linearity error 01H 00H VZT VFT Analog input CKS PCK 1, 0 0 (φ/2 selection) 1 (φ selection) 00 (φ = fEX/2) fADC = fC/2 fADC = fC 01 (φ = fEX/4) fADC = fC/4 fADC = fC/2 11 (φ = fEX/16) fADC = fC/16 fADC = fC/8 – 15 – CXP84412/84416 (4) Interruption, reset input Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin Condition Min. External interruption High, Low level width tIH tIL INT0 INT1 INT2 INT3 NMI Reset input Low level width tRSL RST 32/fc tIH tIL Max. Unit 1 µs µs Fig 6. Interruption input timing 0.8VDD INT0 INT1 INT2 INT3 NMI (NMI specifies only for the falling edge) 0.2VDD tIL tIH Fig. 7. RST input timing tRSL RST 0.2VDD – 16 – CXP84412/84416 Appendix Fig. 8. Recommended oscillation circuit AAAA AAAA AAAA AAAA AAAAA AAAA AAAAA AAAA AAAAA (i) Main clock EXTAL EXTAL XTAL Rd C1 (iii) Sub clock (ii) Main clock EXTAL TEX XTAL XTAL TX Rd C2 Rd C2 C1 C 1 C2 Manufacturer MURATA MFG CO., LTD. Model C1 (pF) fc (MHz) CSA4.19MG 4.19 CSA8.00MTZ 8.00 CSA10.0MTZ 10.00 CST4.19MGW∗ CST8.00MTW∗ C2 (pF) Rd (Ω) Circuit example (i) 30 30 0 4.19 (ii) 8.00 CST10.0MTW∗ 10.00 4.19 FUJI SANGYO CO., LTD. HC-49/U03 12 8.00 12 0 10.00 (i) 4.19 27 27 10.00 20 20 32.768kHz 50 22 HC-49/U (-S) KINSEKI LTD. P3 8.00 0 1M Those marked with an asterisk (∗) signify types with built-in ground capacitance (C1, C2). Mask option table Content Item Reset pin pull-up resistance No Yes – 17 – (iii) CXP84412/84416 Characteristics Curve I DD vs. fc (V DD = 5V , Ta = 25°C, Typ ical) 20.0 1/2 dividing mode 10.0 1/4 dividing mode 5.0 1/16 dividing mode 1.0 SLEEP mode 0.5 32kHz mode (instruction) 0.1 (100µA) 0.05 (50µA) 20 IDD – Supply current [mA] IDD – Supply current [mA] I DD vs. V DD (fc = 10MHz, Ta = 25°C, Typ ical) 15 1/2 dividing mode 10 1/4 dividing mode 32kHz SLEEP mode 5 1/16 dividing mode 0.01 (10µA) SLEEP mode 2 3 4 5 6 7 0 VDD – Supply voltage [V] – 18 – 5 10 fc – System clock [MHz] 1 5 CXP84412/84416 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g – 19 – 0.8 ± 0.2 80