Sony CXD3021R Cd digital signal processor with built-in digital servo and dac Datasheet

CXD3021R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD3021R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a builtin RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 32× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 32× playback by switching the
built-in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL.
• Digital PLL master clock can be set to 2/3 the
conventional one.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 32× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error
detection
• Digital CLV spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• Digital Out can be generated from the audio serial
inputs.
• Supports three types of DA interface
(48 bits/64 bits/32 bits)
• DSP, servo and DAC blocks support sleep mode.
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump and surf brake functions supporting micro
two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
• Servo drive DAC output possible
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 8fs oversampling filter
• Adoption of a tertiary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD
–0.3 to +4.4
–0.3 to +4.4
• Input voltage
VI
(VSS – 0.3 to VDD + 0.3)
• Output voltage
VO
–0.3 to +4.4
• Storage temperature
Tstg
–40 to +125
• Supply voltage difference VSS – AVSS –0.3 to +0.3
VDD – AVDD –0.3 to +0.3
V
V
V
V
°C
V
V
Recommended Operating Conditions
• Supply voltage
VDD∗
3.0 to 4.0 V
• Operating temperature Topr
–20 to +75 °C
∗ The VDD (min.) for the CXD3021R varies according
to the playback speed and built-in VCO selection.
The VDD (min.) for the CXD3021R under various
conditions are as shown on the following page.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98209A9Z-PS
CXD3021R
Maximum Operating Speed
36
35
+25°C
34
33
[Multiple]
+55°C
32
+75°C
31
30
29
28
27
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
[V]
The Maximum Operating Speed graph shows the playback speed VDD (min.) at various temperatures.
The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W
mode with DSPB = 1.
–2–
CXD3021R
Block Diagram
DTS0
LMUTO
25 27 23
RMUTO
44
XWO
5
BCKI
PCMDI
4
LRCKI
XTSL
71
VPCO1
XTLI
70
VPCO2
XTLO
∗ : Asymmetry Correction
103 61 62 63
DAC Block
MCKO 45
74 PWMLP
V16M 113
75 PWMLN
VCKI 112
Clock
Generator
FSTIO 46
8Fs Digital Filter
+
1 bit DAC
32K RAM
67 PWMRP
66 PWMRN
C4M 47
C16M 48
VCTL 6
OSC
PDO 111
20 PSSL
Address
generator
PCO 9
EFM
Demodulator
FILI 8
24 DA16 (48PCM)
Serial/parallel
processor
Digital PLL
Vari-Pitch
double
speed
VCOO 108
Register
VCOI 109
Priority
encoder
8
FILO 7
26 DA15 (48BCK)
28 DA14 (64PCM)
29 DA13 (64BCK)
30 DA12 (64LRCK)
CLTV 10
RFAC 12
∗
ASYI 14
Sync
protector
MUX
31 to 35, DA011
37 to 42 to DA1
D/A data
processor
ASYO 15
52 MUTE
ASYE 19
WFCK 53
Timing
Generator1
SCOR 54
Subcode
P to W
processor
EXCK 56
SBSO 55
SQCK 58
Peak
detector
Error
corrector
Error Rate
counter
Subcode Q
processor
SQSO 57
51 DOUT
Digital out
50 MD2
MDS 99
81 DATA
MDP 98
Timing
Generator2
CLV processor
MON 97
83 CLOK
CPU interface
82 XLAT
FSW 90
Servo
auto
sequencer
18-times
oversampling
filter
Noise
Shaper
78 SENS
PWMI 106
Signal Processor Block
TEST 110
TES2 104
TES3 105
Servo
Interface
XRST 60
Servo Block
ADIO 117
85 COUT
MIRR
86 MIRR
DFCT
87 DFCT
FOK
88 FOK
RFDC 118
DAC
SERVO DSP
TE 120
OpAmp
AnaSw
SE 1
A/D
CONVERTER
FE 2
94 FAO
TRACKING SERVO
TRACKING
93 TAO
SLED SERVO
SLED
92 SAO
–3–
AVSS5
AVSS6
AVSS4
AVSS2
AVSS3
AVSS1
DVSS4
DVSS5
DVSS2
DVSS3
AVDD6
AVDD5
AVDD4
AVDD3
AVDD1
AVDD2
DVDD5
DVDD3
DVDD4
18 43 64 84 102 11 116 73 65 72 91
DVDD2
17 36 49 77 107 16 114 76 68 69 96
DVSS1
FOCUS
DVDD1
VC 3
OpAmp
FOCUS SERVO
95
BSSD
CE 119
CXD3021R
XWO
RMUTO
LMUTO
DVSS3
PWMRN
AVSS4
AVDD4
PWMRP
XTLO
AVDD5
XTLI
AVSS3
AVSS5
PWMLP
PWMLN
DVDD4
AVDD3
SCLK
SENS
ATSK
XLAT
DATA
CLOK
DVSS4
COUT
MIRR
DFCT
TESO
FOK
FSW
Pin Configuration
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60 XRST
AVSS6 91
SAO 92
59
SCSY
TAO 93
58
SQCK
FAO 94
57 SQSO
BSSD 95
56 EXCK
AVDD6 96
55
SBSO
MON 97
54
SCOR
MDP 98
53 WFCK
MDS 99
52 MUTE
LOCK 100
51 DOUT
SSTP 101
50
MD2
49 DVDD3
DVSS5 102
DTS0 103
48
C16M
47
C4M
TES3 105
46
FSTIO
PWMI 106
45
MCKO
DVDD5 107
44
XTSL
VCOO 108
43 DVSS2
TES2 104
VCOI 109
42 DA01
TEST 110
41 DA02
PDO 111
40 DA03
VCKI 112
39 DA04
V16M 113
38 DA05
37 DA06
AVDD2 114
IGEN 115
36
DVDD2
AVSS2 116
35
DA07
34 DA08
ADIO 117
DA12
DA13
BCKI
DA14
DA15
PCMDI
DA16
LRCKI
LRCK
PSSL
PCO
WDCK
FILI
ASYE
FILO
–4–
DVSS1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AVDD1
8
DVDD1
7
ASYI
6
ASYO
5
BIAS
4
RFAC
3
AVSS1
2
CLTV
1
VCTL
DA10
31 DA11
VPCO2
32
TE 120
VPCO1
CE 119
VC
DA09
FE
33
SE
RFDC 118
CXD3021R
Pin Description
Pin
No.
Symbol
I/O
Description
1
SE
I
Sled error signal input.
2
FE
I
Focus error signal input.
3
VC
I
Center voltage input.
4
VPCO1
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output.
5
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $EX
command FCSW.
6
VCTL
I
7
FILO
O
8
FILI
I
9
PCO
O
10
CLTV
I
11
AVSS1
12
RFAC
I
EFM signal input.
13
BIAS
I
Asymmetry circuit constant current input.
14
ASYI
I
Asymmetry comparator voltage input.
15
ASYO
O
16
AVDD1
Analog power supply.
17
DVDD1
Digital power supply.
18
DVSS1
Digital GND.
19
ASYE
I
Asymmetry circuit on/off (low = off, high = on).
20
PSSL
I
Audio data output mode switching input (low: serial, high: parallel).
21
WDCK
O
1, 0
D/A interface for 48-bit slot. Word clock f = 2Fs.
22
LRCK
O
1, 0
D/A interface for 48-bit slot. LR clock f = Fs.
23
LRCKI
I
24
DA16
O
25
PCMDI
I
26
DA15
O
27
BCKI
I
28
DA14
O
1, 0
DA14 output when PSSL = 1, 32-bit/64-bit slot serial data output (two'
complement, LSB first) when PSSL = 0.
29
DA13
O
1, 0
DA13 output when PSSL = 1, 32-bit/64-bit slot bit clock output when PSSL = 0.
30
DA12
O
1, 0
DA12 output when PSSL = 1, 32-bit/64-bit slot LR clock output when PSSL = 0.
31
DA11
O
1, 0
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
32
DA10
O
1, 0
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
33
DA09
O
1, 0
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
Wide-band EFM PLL VCO2 control voltage input.
Analog
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
1, Z, 0
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
1, 0
EFM full-swing output (low = VSS, high = VDD).
LR clock input to DAC (48-bit slot).
1, 0
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
1, 0
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
–5–
CXD3021R
Pin
No.
Symbol
34
DA08
O
1, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
35
DA07
O
1, 0
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
36
DVDD2
37
DA06
O
1, 0
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
38
DA05
O
1, 0
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
39
DA04
O
1, 0
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
40
DA03
O
1, 0
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
41
DA02
O
1, 0
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
42
DA01
O
1, 0
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
43
DVSS2
44
XTSL
I
45
MCKO
O
1, 0
Clock output. Inverted output of XTLI.
46
FSTIO
I/O
1, 0
Digital servo clock input/output.
(2/3 frequency division for XTLI pin is internally connected.)
47
C4M
O
1, 0
1/4 frequency division output for XTLI pin. Changes with variable pitch.
48
C16M
O
1, 0
16.9344MHz output. Changes simultaneously with variable pitch.
49
DVDD3
50
MD2
I
51
DOUT
O
52
MUTE
I
53
WFCK
O
1, 0
WFCK (Write Frame Clock) output.
54
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
55
SBSO
O
1, 0
Sub P to W serial output.
56
EXCK
I
57
SQSO
O
58
SQCK
I
SQSO readout clock input.
59
SCSY
I
GRSCOR resynchronization input. Normally low, resynchronization is
executed when high.
60
XRST
I
System reset. Reset when low.
61
XWO
I
Audio DAC sync window open input. Normally high, window open when low.
62
RMUTO
O
1, 0
Audio DAC right channel zero detection flag.
63
LMUTO
O
1, 0
Audio DAC left channel zero detection flag.
64
DVSS3
Digital GND.
65
AVSS4
Analog GND.
66
PWMRN
O
1, Z, 0
Audio DAC PWM output. Right channel, reversed phase.
67
PWMRP
O
1, Z, 0
Audio DAC PWM output. Right channel, forward phase.
Description
I/O
Digital power supply.
Digital GND.
Crystal selection input.
Digital power supply.
Digital Out on/off control (low = off, high = on).
1, 0
Digital Out output.
Mute (low: off, high: on).
SBSO readout clock input.
1, 0
Sub-Q 80-bit, PCM peak and level data 16-bit outputs.
–6–
CXD3021R
Pin
No.
Symbol
68
AVDD4
Analog power supply.
69
AVDD5
Master clock power supply.
70
XTLO
O
71
XTLI
I
72
AVSS5
Master clock GND.
73
AVSS3
Analog GND.
74
PWMLP
O
1, Z, 0
Audio DAC PWM output. Left channel, forward phase.
75
PWMLN
O
1, Z, 0
Audio DAC PWM output. Left channel, reversed phase.
76
AVDD3
Analog power supply.
77
DVDD4
Digital power supply.
78
SENS
O
79
SCLK
I
SENS serial data readout clock input. Set to high when not used.
80
ATSK
I
Anti-shock pin. Set to low when not used.
81
DATA
I
Serial data input from CPU.
82
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
83
CLOK
I
Serial data transfer clock input from CPU.
84
DVSS4
85
COUT
I/O
1, 0
Track count signal I/O.
86
MIRR
I/O
1, 0
Mirror signal I/O.
87
DFCT
I/O
1, 0
Defect signal I/O.
88
FOK
I/O
1, 0
Focus OK signal I/O.
89
TESO
O
90
FSW
O
91
AVSS6
92
SAO
O
Sled filter DAC analog output.
93
TAO
O
Tracking filter DAC analog output.
94
FAO
O
Focus filter DAC analog output.
95
BSSD
I
Constant current input for servo filter DAC analog output.
96
AVDD6
97
MON
O
1, 0
Spindle motor on/off control output.
98
MDP
O
1, Z, 0
Spindle motor servo control output.
99
MDS
O
1, Z, 0
Spindle motor servo control output.
100
LOCK
I/O
1, 0
I/O
1, 0
Description
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
1, Z, 0
SENS output to CPU.
Digital GND.
Test pin. Leave this open.
1, Z, 0
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Analog GND.
Analog power supply.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high. (See $3E.)
–7–
CXD3021R
Pin
No.
Symbol
101
SSTP
102
DVSS5
103
DTS0
I
Test pin. Normally fixed to low.
104
TES2
I
Test pin. Normally fixed to low.
105
TES3
I
Test pin. Normally fixed to low.
106
PWMI
I
Spindle motor external pin input.
107
DVDD5
108
VCOO
O
109
VCOI
I
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
110
TEST
I
Test pin. Normally fixed to low.
111
PDO
O
112
VCKI
I
113
V16M
O
114
AVDD2
115
IGEN
116
AVSS2
117
ADIO
O
Operational amplifier output.
118
RFDC
I
RF signal input.
119
CE
I
Center servo analog input.
120
TE
I
Tracking error signal input.
I/O
Description
Disc innermost track detection signal input.
I
Digital GND.
Digital power supply.
1, 0
1, Z, 0
Analog EFM PLL oscillation circuit output.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
1, 0
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
I
Connects the operational amplifier current source reference resistance.
Analog GND.
Notes) • The 32-bit/64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
–8–
CXD3021R
Electrical Characteristics
1. DC Characteristics
(VDD = AVDD = 3.3V ± 10%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Input voltage (1)
High level input voltage VIH (1)
Low level input voltage
Input voltage (2)
Input voltage (4)
VIL (1)
VIL (2)
High level input voltage VIH (3)
Low level input voltage
Min.
VIL (3)
Typ.
Max.
0.2VDD
Schmitt input
VI ≤ 5.5V
High level input voltage VIH (4) VI ≤ 5.5V
Low level input voltage VIL (4) Schmitt input
Unit
V
0.7VDD
High level input voltage VIH (2)
Low level input voltage
Input voltage (3)
Conditions
0.2VDD
0.2VDD
∗3
V
V
0.7VDD
∗2
V
V
0.7VDD
∗1, ∗12
V
V
0.7VDD
Applicable
pins
0.2VDD
V
∗4
Input voltage (5)
Input voltage
VIN (5) Analog input
VSS
VDD
V
∗5
Input voltage (6)
Input voltage
VIN (6) Analog input
VSS
VDD
V
∗6
VDD – 0.4
VDD
V
0
0.4
V
VDD – 0.4
VDD
V
0
0.4
V
VDD – 0.2
VDD
V
Low level output voltage VOL (3) IOL = 4mA
0
0.4
V
∗7, ∗10
∗12
Low level output voltage VOL (4) IOL = 4mA
0
0.4
V
∗8
High level output voltage VOH (5) IOH = –0.28mA VDD – 0.5
VDD
V
Low level output voltage VOL (5) IOH = 0.36mA
0
0.4
V
Output voltage (1)
Output voltage (2)
Output voltage (3)
Output voltage (4)
Output voltage (5)
High level output voltage VOH (1) IOH = –8mA
Low level output voltage VOL (1) IOL = 8mA
High level output voltage VOH (2) IOH = –4mA
Low level output voltage VOL (2) IOL = 4mA
High level output voltage VOH (3) IOH = –2mA
∗9
∗7, ∗10
∗12
∗11
Input leak current (1)
ILI (1)
VI = 0 to 5.5V
–10
10
µA ∗3, ∗4, ∗5
Input leak current (2)
ILI (2)
VI = 0.25VDD
to 0.75VDD
–20
20
µA
∗6
Tri-state pin output leak current
ILO
VO = 0 to 3.6V
–5
5
µA
∗10
Applicable pins
∗1 DTS0, TES2, TES3, TEST, PSSL
∗2 ASYE, VCKI
∗3 ATSK, DATA, MD2, PWMI, SSTP, XLAT, XTSL, PCMDI, XWO
∗4 CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST, BCKI, LRCKI
∗5 ASYI, BIAS, CLTV, FILI, IGEN, BSSD, RFAC, VCTL
∗6 CE, FE, SE, TE, VC, RFDC
∗7 ASYO, C16M, C4M, DA01 to DA16, DOUT, LRCK, MON, SBSO, SCOR, SQSO, WDCK, WFCK, PWMLP,
PWMLN, PWMRP, PWMRN, RMUTO, LMUTO
∗8 FSW
∗9 MCKO
∗10 MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2
∗11 FILO
∗12 COUT, DFCT, FOK, LOCK, MIRR, FSTIO
–9–
CXD3021R
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
Item
Oscillation
frequency
Symbol
Min.
Typ.
7
fMAX
Max.
Unit
34
MHz
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
tWHX
13
500
ns
Low level pulse
width
tWLX
13
500
ns
Pulse cycle
tCX
26
1000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time,
fall time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
XTLI
VDD/2
VIHX × 0.1
VILX
tR
tF
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
Item
Input amplitude
Symbol
Min.
VI
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
– 10 –
CXD3021R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Min.
Typ.
Max.
Unit
16
MHz
Clock frequency
fCK
Clock pulse width
tWCK
30
ns
Setup time
tSU
30
ns
Hold time
tH
30
ns
Delay time
tD
30
ns
Latch pulse width
tWL
750
ns
EXCK SQCK frequency
fT
0.65
EXCK SQCK pulse width tWT
CNIN frequency ∗
fT
CNIN pulse width ∗
tWT
ns
750
65
1/fCK
tWCK
tWCK
CLOK
DATA
tSU
tH
tD
tWL
EXCK
SQCK
CNIN
tWT
tWT
1/fT
SBSO
SQSO
tSU
kHz
µs
7.5
∗ Only when $44 and $45 are executed.
XLAT
MHz
tH
– 11 –
CXD3021R
(3) SCLK pin
XLAT
tDLS
tSPW
…
SCLK
1/fSCLK
Serial Readout Data
(SENS)
Item
…
MSB
Symbol
Min.
Typ.
Max.
Unit
16
MHz
SCLK frequency
fSCLK
SCLK pulse width
tSPW
31.3
ns
Delay time
tDLS
15
µs
(4) COUT, MIRR and DFCT pins
Operating frequency
LSB
(VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Signal
Symbol
Min.
Typ.
Max.
Unit
Conditions
COUT maximum operating frequency
fCOUT
40
kHz
∗1
MIRR maximum operating frequency
fMIRR
40
kHz
∗2
DFCT maximum operating frequency
fDFCTH
5
kHz
∗3
∗1 When using a high-speed traverse TZC.
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.11VDD to 0.23VDD
B
•
≤ 25%
A+B
∗3 During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
– 12 –
CXD3021R
(5) BCKI, LRCKI and PCMDI pins
Item
(VDD = 3.3V ± 10%, Topr = –20 to +75°C)
Symbol
Min.
Input BCKI frequency
tBCK
Input BCKI pulse width
tWIB
100
Input data setup time
tIDS
10
Input data hold time
tIDH
15
Input LRCK setup time
tILRH
10
Input LRCK hold time
tILRS
15
Typ.
Max.
Unit
4.5
MHz
ns
tWIB
tWIB
50%
BCKI
tIDS
tIDH
PCMDI
tILRH
LRCKI
– 13 –
tILRS
CXD3021R
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 384fs)
Item
Remarks
Typ.
Unit
S/N ratio
93
dB
(EIAJ) ∗1
THD + N
0.007
%
(EIAJ)
Dynamic range
91
dB
(EIAJ) ∗1, ∗2
Channel separation
91
dB
(EIAJ)
Output level
0.81
V (rms)
Difference in gain between channels
0.1
dB
∗1 Using "A" weighting filter
∗2 –60dB, 1kHz input
The analog characteristics measurement circuit is shown below.
47k
PWMLP
(PWMRP)
33k
8.2k
100p
33k
220p
100p
PWMLN
(PWMRN)
33k
8.2k
8.2k
100 10µ
33k
1000p
39k
100p
768fs
15k
15k
15k
15k
100k
0.1µ
SHIBASOKU (AM51A)
PWMLP
Analog
1ch
PWMLN
TEST DISC
DATA
CXD3021R
PWMRP
Audio Circuit
Audio Analyzer
2ch
PWMRN
Block diagram of analog characteristics measurement
– 14 –
CXD3021R
Servo Drive Analog Characteristics
(VDD = AVDD = 3.0 to 4.0V, VSS = AVSS = 0V, Topr = –20 to +75°C,
BSSD pin is connected to AVDD via a 33kΩ resistor.)
When the load resistance is 200kΩ or more
Item
Min.
Typ.
Max.
Unit
Applicable pins
Maximum output voltage
0.9VDD
0.97VDD
VDD
V
FAO, TAO, SAO
Minimum output voltage
VSS
0.03VDD
0.1VDD
V
FAO, TAO, SAO
Typ.
Max.
Unit
Applicable pins
V
FAO, TAO, SAO
V
FAO, TAO, SAO
When the load resistance is 60kΩ
Item
Min.
0.90VDD
Maximum output voltage
Minimum output voltage
VSS
0.03VDD
0.1VDD
– 15 –
CXD3021R
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 1-2. CPU Interface Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 1-3. CPU Command Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 1-4. Description of SENS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
28
34
[2] Subcode Interface
§ 2-1. P to W Subcode Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
§ 2-2. 80-bit Sub-Q Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
[3] Description of Modes
§ 3-1. CLV-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 3-2. CLV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 3-3. CAV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
§ 3-4. VCO-C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
79
79
80
[4] Description of Other Functions
§ 4-1. Channel Clock Recovery by Digital PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
§ 4-2. Frame Sync Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
§ 4-3. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
§ 4-4. DA Interface Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
§ 4-5. Digital Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
§ 4-6. Servo Auto Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
§ 4-7. Digital CLV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
§ 4-8. Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
§ 4-9. DAC Block Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
§ 4-10. DAC Block Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
§ 4-11. Asymmetry Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
§ 4-12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
§ 5-2. Digital Servo Block Master Clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
§ 5-4. E:F Balance Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
§ 5-5. FCS Bias Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
§ 5-6. AGCNTL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
§ 5-7. FCS Servo and FCS Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
§ 5-8. TRK and SLD Servo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
§ 5-9. MIRR and DFCT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
§ 5-10. DFCT Countermeasure Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
§ 5-11. Anti-Shock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
§ 5-12. Brake Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
§ 5-13. COUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
§ 5-14. Serial Readout Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
§ 5-15. Writing to Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
§ 5-16. DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
§ 5-17. Servo Status Changes Produced by LOCK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
§ 5-18. Description of Commands and Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
§ 5-19. List of Servo Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
§ 5-20. Filter Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
§ 5-21. TRACKING and FOCUS Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
[6] Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Explanation of abbreviations
AVRG:
Average
AGCNTL: Auto gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
– 16 –
CXD3021R
[1] CPU Interface
§ 1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
30ns or more
CLOK
DATA
D0
D1
D18
D19
D20
D21
D22
D23
750ns or more
XLAT
Registers
Valid
• The internal registers are initialized by a reset when XRST = 0.
§ 1-2. CPU Interface Command Table
Total bit length for each register
Register
Total bit length
0 to 2
8 bits
3
8 to 24 bits
4 to 6
16 bits
7
20 bits
8
32 bits
9
32 bits
A
28 bits
B
20 bits
C
28 bits
D
20 bits
E
20 bits
– 17 –
1
FOCUS
CONTROL
0
TRACKING
CONTROL
Command
Register
0001
0000
– 18 –
—
—
—
—
—
—
—
0
—
—
1
—
0
—
—
0
—
—
0
0
—
0
0
1
1
1
0
D18
—
—
1
0
—
—
—
—
1
1
1
0
—
—
D17
Data 1
1
D23 to D20 D19
Address
Command Table ($0X to 1X)
0
1
—
—
—
—
—
—
1
0
—
—
—
—
D16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0
—: Don't care
TRACKING GAIN UP
FILTER SELECT 2
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
TRACKING GAIN
NORMAL
BRAKE OFF
BRAKE ON
ANTI SHOCK OFF
ANTI SHOCK ON
FOCUS SEACH
VOLTAGE UP
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
CXD3021R
– 19 –
3
SELECT
Command
TRACKING
MODE
2
Register
Command
Register
0011
0
0
0
0
0
0
0
D18
0
D23 to D20 D19
—
—
—
—
—
—
1
1
—
0
1
—
1
0
Address
0010
0
D18
1
0
1
0
—
—
—
—
D16
1
1
0
0
D17
1
0
1
0
D16
Data 1
1
1
0
0
—
—
—
—
D17
Data 1
0
D23 to D20 D19
Address
Command Table ($2X to 3X)
—
—
—
—
D15
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
D13
—
—
—
—
D14
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
D14
Data 2
—
—
—
—
D12
—
—
—
—
—
—
—
—
D12
—
—
—
—
D11
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
D9
—
—
—
—
D10
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
D10
Data 3
—
—
—
—
D8
—
—
—
—
—
—
—
—
D8
—
—
—
—
D7
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
D5
—
—
—
—
D6
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
D6
Data 4
—
—
—
—
D4
—
—
—
—
—
—
—
—
D4
—
—
—
—
D3
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
D1
—
—
—
—
D2
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
D2
Data 5
—
—
—
—
D0
—
—
—
—
—
—
—
—
D0
—: Don't care
SLED KICK LEVEL
(±4 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±1 × basic value) (Default)
REVERSE SLED MOVE
FORWARD SLED MOVE
SLED SERVO ON
SLED SERVO OFF
REVERSE TRACK JUMP
FORWARD TRACK JUMP
TRACKING SERVO ON
TRACKING SERVO OFF
CXD3021R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0000
0
0
1
1
1
0
0
0
0
0
– 20 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($340X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K00)
SLED INPUT GAIN
CXD3021R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0001
0
0
1
1
1
0
0
0
0
0
– 21 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($341X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K18)
FIX
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
CXD3021R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0010
0
0
1
1
1
0
0
0
0
0
– 22 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($342X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K2F)
NOT USED
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
CXD3021R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0011
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
D10
– 23 –
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($343X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K3F)
NOT USED
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K32)
NOT USED
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K30)
SLED INPUT GAIN
(when TGup2 is accessed with SFSK = 1)
CXD3021R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0100
0
0
1
1
1
0
0
0
0
0
– 24 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($344X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K4F)
NOT USED
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K47)
NOT USED
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN
(when TGup2 is accessed with THSK = 1)
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
CXD3021R
3
Register
SELECT
Command
Address 2
0011
0100
1
1
0
0
0
1
1
1
1
1
1
D9
D8
THBON FHBON TLB1ON FLB1ON TLB2ON
0
1
SFBK1 SFBK2
1
1
0
– 25 –
0
0
0
D5
0
0
D4
D8
0
0
0
D7
D5
Data 2
D6
0
0
0
0
0
0
0
0
0
D1
FB9
TV9
0
0
FB7
TV7
FB8
TV8
TV6
FB6
0
0
0
0
D0
D4
0
D3
0
0
D2
D1
Data 3
0
TV5 TV4
FB5 FB4
TV3
FB3
TV2 TV1
FB2 FB1
TV0
—
—
D0
0
HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0
0
FAOZ TAOZ SAOZ
0
D2
MRT1 MRT0
D3
Data 3
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
1
0
D9
0
1
D10
0
0
Data 1
FAON TAON SAON
D11
0
0
D6
Data 2
COPY EMPH CAT DOUT DOUT DOUT WIN DOUT
EN
b8
D
EN DMUT WOD EN EN2
0
A/D
SEL
0
0
0
0
D7
0
D15 D14 D13 D12
1
D10
PGFS1 PGFS0 PFOK1 PFOK0
D11
Data 1
1
0
D12
Address 3
0
0
0
1
1
0
0
1
1
D13
Address 3
D14
D23 to D20 D19 to D16 D15
Address 1
Command Table ($348X to 34FX)
—: Don't care
Traverse Center Data
FCS Bias Data
FCS Bias Limit
Servo DAC output
Booster
Booster Surf Brake
DOUT
PGFS, PFOK, MIRR
CXD3021R
3
Register
SELECT
Command
0011
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
0
1
1
D18
0
1
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
D16
D17
Address 2
0
D23 to D20 D19
Address 1
Command Table ($35X to 3FX)
D13
FT0 FS5
D14
TJ4
FS4
D12
D10
D9
D8
TJ3
TJ2
TJ1
D6
D5
D4
D3
D2
D1
Data 4
D0
FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
D7
Data 3
TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
FS3 FS2 FS1 FS0
D11
Data 2
TRK jump, AGT
FCS search, AGF
FBON FBSS FBUP FBV1 FBV0
0
0
0
0
TJD0 FPS1 FPS0 TPS1 TPS0
0
0
0
– 26 –
0
TLD2 TLD1 TLD0
0
0
0
0
AGC4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
0
0
0
0
0
0
0
0
0
0
0
0
SLD filter
TZC, Cout, Bottom, Mirr
Mirr, DFCT, FOK
FCS Bias, Gain,
Surf jump/brake
Serial data read out
0
Clock, others
LKIN COIN MDFI MIRI XT1D Filter
0
0
SJHD INBK MTI0
0
ASFG FTQ LPAS SRO1 SRO0 AGHF
0
0
BTS1 BTS0 MRC1 MRC0
F1NM F1DM F3NM F3DM TINM TIUM T3NM T3UM DF1S TLCD
SFID SFSK THID THSK
COSS COTS CETZ CETF COT2 COT1 MOT2
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
0
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move
TDZC DTZC TJ5
FT1
D15
Data 1
CXD3021R
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence (N)
track jump count
setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
5
6
7
8
9
A
B
– 27 –
C
D
E
0
0
1
1
1
1
0
Auto sequence
4
D2
1
0
0
1
1
0
0
1
1
0
0
D1
Address
D3
Command
Register
Command Table ($4X to EX)
0
1
0
1
0
1
0
1
0
1
0
D0
SD2
TR2
AS2
D2
1024
KF2
0
MT2
D2
512
KF1
0
MT1
D1
KF0
0
MT0
D0
0
0
LSSL
D3
0
8192
Mute
4096
ATT
DCLV
CM3
PWM MD
CM2
TB
CM1
TP
2048
1024
512
VP7
VP6
VP5
CM0 EPWM SPDC ICAP
CLVS
Gain
KSL1
32
0
0
0
D1
DAC
SYCOF
ATT
KSL2
64
0
0
0
D2
Data 3
0
KSL0
16
0
0
0
D0
256
128
VP3
SFSL VC2C
VP4
VP1
SFP1
32
4
—
—
—
D2
2
—
—
—
D1
1
—
—
—
D0
8
4
2
1
ATTCH
ATD10 ATD9 ATD8
SEL
PLM3 PLM2 PLM1 PLM0
VC01 VCO1 XVCO2 VCO2
CS1
CS0 THRU CS
8
—
—
—
D3
Data 4
VP0
VP
CTL0
0
0
—: Don't care
INV
Gain Gain
FCSW
VPCO
CAV1 CAV0
VP
CTL1
SFP0 SRP3 SRP2 SRP1 SRP0
16
HIFC LPWR VPON
VP2
SFP2
64
PCT1 PCT2 MCSL SOC2 DCOF FMUT BSBST BBSL
Gain Gain Gain Gain Gain Gain
PCC1 PCC0 SFP3
MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0
32768 16384
0
DCLV DSPB ASEQ DPLL BiliGL BiliGL
DAC
FLFC XWOC
ON/OFF ON/OFF ON/OFF ON/OFF MAIN SUB
EMP
KSL3
2048
KF3
0
MT3
D3
CD- DOUT DOUT
VCO
VCO
ASHS SOCT0
WSEL
ROM Mute Mute-F
SEL1
SEL2
4096
SD0
TR0
AS0
D0
128
8192
SD1
TR1
AS1
D1
Data 2
256
32768 16384
SD3
TR3
AS3
D3
Data 1
CXD3021R
1
0
0
0
0
1
0
0
Address
0
0
1
0
Data 1
– 28 –
0010
TRACKING
MODE
Command
2
Register
SELECT
0001
TRACKING
CONTROL
1
3
0000
FOCUS
CONTROL
0
0011
0
D18
0
0
0
D18
0
1
D18
0
1
0
D16
0
D17
0
D17
0
D16
0
D16
0
D15
—
D15
—
—
—
D15
Data 2
Data 1
0
0
0
D17
Data 1
Address 1
0
D23 to D20 D19
0011
D23 to D20 D19
Address
0
0
0
D23 to D20 D19
Command
Register
Address
Command Preset Table ($0X to 344X)
§ 1-3. CPU Command Presets
coefficient setting
1
1
Audio CTRL
A
Spindle servo
1
Function
specification
9
C
1
MODE
specification
Command
8
Register
Command Table ($4X to EX) cont.
—
—
—
D13
—
D13
D14
D13
Address 2
—
D14
Data 2
—
—
—
D14
Data 2
Data 3
D12
—
D12
—
—
—
D12
D11
—
D11
—
—
—
D11
Data 4
D1
D0
SCOR
SCSY SOCT1
SEL
D2
0
0
D3
0
0
D2
0
OUTL
D1
Data 6
SLBS
0
D0
—
—
—
D9
—
D9
D9
D8
—
D8
—
—
—
D8
D7
—
D7
—
—
—
D7
—
—
—
D5
—
D5
D6
D5
Data 1
—
D6
Data 4
—
—
—
D6
Data 4
D4
—
D4
—
—
—
D4
See "Coefficient ROM Preset Values Table".
D10
Address 3
—
D10
Data 3
—
—
—
D10
Data 3
D3
—
D3
—
—
—
D3
—
—
—
D1
—
D0
D2
D0
Data 2
—
D2
Data 5
—
—
—
D2
Data 5
EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0
ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0
DAC DAC
ZMUT ZDPL
SMUTL SMUTR
ERC4
D3
Data 5
D0
—
D0
—
—
—
D0
—
—
DIV4
FSTIN
D3
0
D1
0
D0
—
—
—: Don't care
—
—
—: Don't care
KRAM DATA
($3400XX to $344fXX)
SLED KICK LEVEL
(±1 × basic value) (Default)
TRACKING SERVO OFF
SLED SERVO OFF
TRACKING GAIN UP
FILTER SELECT 1
FOCUS SERVO OFF,
0V OUT
—
—
DSP DSSP DAC
SLEEP SLEEP SLEEP
0
D2
Data 7
CXD3021R
3
Register
SELECT
Command
Address 2
0011
0100
1
1
0
0
0
1
1
1
1
– 29 –
1
1
D15 D14 D13
1
1
0
1
0
1
0
D12
0
0
0
0
0
0
D11
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
D7
0
0
0
D8
0
0
0
Data 1
0
0
0
0
0
0
0
0
0
D7
D8
D9
D9
0
0
0
0
0
0
D10
Data 1
D10
D12 D11
Address 3
0
0
0
1
1
0
0
1
1
D13
Address 3
D14
D23 to D20 D19 to D16 D15
Address 1
Command Preset Table ($348X to 34FX)
0
1
0
0
0
0
0
0
0
0
0
D6
D4
0
0
0
D5
0
0
0
0
0
0
0
D4
D5
Data 2
0
0
0
1
0
0
D6
Data 2
0
0
0
D3
0
0
0
0
0
0
D3
0
0
0
0
0
0
D1
0
0
0
D2
0
0
0
D1
Data 3
0
0
0
0
0
0
D2
Data 3
0
0
0
D0
0
0
0
0
0
0
D0
Traverse Center Data
FCS Bias Data
FCS Bias Limit
Servo DAC output
Booster
Booster Surf Brake
DOUT
CAV control
PGFS, PFOK, MIRR
CXD3021R
3
Register
SELECT
Command
0011
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
D18
– 30 –
1
1
0
0
1
1
0
0
1
1
0
D17
Address 2
0
D23 to D20 D19
Address 1
Command Preset Table ($35X to 3FX)
1
0
1
0
1
0
1
0
1
0
1
D16
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
D14
D15
0
0
0
0
1
0
0
0
0
0
0
D13
Data 1
0
0
0
0
0
0
0
0
1
0
1
D12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
D10
D11
0
0
0
0
0
0
0
0
0
1
0
D9
Data 2
0
0
0
0
0
0
0
0
0
0
0
D8
0
0
0
1
0
0
0
0
1
0
0
D7
0
0
0
0
1
0
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
1
1
1
D5
Data 3
0
0
0
0
1
0
0
0
1
0
0
D4
0
0
0
0
0
0
0
0
1
1
1
D3
0
0
0
0
0
0
0
0
0
1
1
D2
0
0
0
0
0
0
0
0
1
1
0
D1
Data 4
0
0
0
0
0
0
0
0
0
0
1
D0
Clock, others
Filter
SLD filter
TZC, Cout, Bottom, Mirr
Mirr, DFCT, FOK
FCS Bias, Gain,
Surf jump/brake
Serial data read out
DC measure, cancel
FZC, AGC, SLD move
TRK jump, AGT
FCS search, AGF
CXD3021R
– 31 –
0
1
1
1
1
1
1
1
Auto sequence
(N) track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
7
8
9
A
B
C
D
E
0
1
1
Audio CTRL
Spindle servo
coefficient setting
A
C
1
0
1
Function
specification
9
0
1
MODE
specification
0
1
0
0
0
0
1
0
1
1
1
0
0
0
0
1
1
Address
8
Command
0
Sled KICK,
BRAKE (D),
KICK (F)
6
Register
0
Blind (A, E),
Brake (B),
Overflow (C, G)
5
1
1
0
Auto sequence
4
D2
Data 1
1
0
0
1
1
0
0
1
1
0
0
D1
Address
D3
Command
Register
Command Preset Table ($4X to EX)
0
1
0
1
0
1
0
1
0
1
0
D0
Data 2
0
0
0
0
0
1
0
0
0
0
0
D3
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
D1
Data 3
D2
Data 1
Data 4
0
0
0
0
1
1
0
0
1
1
0
D0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
0
0
D3
0
0
0
0
0
0
0
0
0
0
0
D2
0
0
0
0
0
0
D1
0
0
D2
Data 5
0
0
0
0
0
0
0
0
0
0
0
D1
Data 2
0
0
0
1
0
1
0
1
0
0
0
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D1
0
0
0
0
D1
Data 6
D2
0
0
D3
0
0
1
0
0
0
0
0
0
0
0
D2
0
0
D0
0
0
1
0
0
0
0
0
0
0
0
D3
Data 3
0
0
0
0
0
0
0
0
0
0
0
D0
0
0
0
0
D0
0
0
0
0
0
1
0
0
—
—
—
D3
—
—
0
0
D3
0
0
0
0
1
0
0
0
—
—
—
D2
—
—
0
0
—
—
0
0
D1
Data 7
D2
0
0
1
0
0
1
0
0
—
—
—
D0
—
—
0
0
D0
—: Don't care
0
0
1
0
0
0
0
0
—
—
—
D1
Data 4
CXD3021R
CXD3021R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 32 –
CXD3021R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
DATA
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
04
7F
7F
79
17
6D
00
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN
(Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
– 33 –
CXD3021R
§ 1-4. Description of SENS Signals
SENS output
Microcomputer
serial register
(latching not required)
ASEQ = 0
ASEQ = 1
Output data length
$0X
Z
FZC
—
$1X
Z
AS
—
$2X
Z
TZC
—
$38
Z
AGOK∗
—
$38
Z
XAVEBSY∗
—
$30 to 37
Z
SSTP
—
$3A
Z
FBIAS Count STOP
—
$3B to 3F
Z
SSTP
—
$3904
Z
TE Avrg Reg.
9 bits
$3908
Z
FE Avrg Reg.
9 bits
$390C
Z
VC Avrg Reg.
9 bits
$391C
Z
TRVSC Reg.
9 bits
$391D
Z
FB Reg.
9 bits
$391F
Z
RFDC Avrg Reg.
8 bits
$4X
Z
XBUSY
—
$5X
Z
FOK
—
$6X
Z
0
—
$AX
GFS
GFS
—
$BX
COMP
COMP
—
$CX
COUT
COUT
—
$EX
OV64
OV64
—
Z
0
—
$7X, 8X, 9X,
DX, FX
∗ $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
– 34 –
CXD3021R
Description of SENS Signals
SENS output
Z
The SENS pin is high impedance.
XBUSY
Low while the auto sequencer is in operation, high when operation terminates.
FOK
Outputs the same signal as the FOK pin.
High for "focus OK".
GFS
High when the regenerated frame sync is obtained with the correct timing.
COMP
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, low when the initial Reg.B number is input by CNIN.
COUT
Counts the number of tracks set with Reg.B.
High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44
and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number.
OV64
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.
– 35 –
CXD3021R
The meaning of the data for each address is explained below.
$4X commands
Register name
4
AS3
Data 1
Data 2
Data 3
Command
MAX timer value
Timer range
AS2
Command
AS1
AS0
MT3
MT2
MT1
MT0
LSSL
0
0
AS3
AS2
AS1
AS0
Cancel
0
0
0
0
Fine Search
0
1
0
RXF
Focus-On
0
1
1
1
1 Track Jump
1
0
0
RXF
10 Track Jump
1
0
1
RXF
2N Track Jump
1
1
0
RXF
M Track Move
1
1
1
RXF
0
RXF = 0 Forward
RXF = 1 Reverse
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump commands ($44 to $45, $48 to $4D) are canceled, $25 is sent and the auto sequence
is interrupted.
MAX timer value
Timer range
MT3
MT2
MT1
MT0
LSSL
0
0
0
23.2ms
11.6ms
5.8ms
2.9ms
0
0
0
0
1.49s
0.74s
0.37s
0.18s
1
0
0
0
• To disable the MAX timer, set the MAX timer value to 0.
$5X commands
Timer
TR3
TR2
TR1
TR0
Blind (A, E), Overflow (C, G)
0.18ms
0.09ms
0.045ms
0.022ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.045ms
– 36 –
CXD3021R
$6X commands
Register name
6
SD3
Data 1
Data 2
KICK (D)
KICK (F)
SD2
SD1
SD0
Timer
KF3
KF2
KF1
KF0
SD3
SD2
SD1
SD0
When executing KICK (D) $44 or $45
23.2ms
11.6ms
5.8ms
2.9ms
When executing KICK (D) $4C or $4D
11.6ms
5.8ms
2.9ms
1.45ms
Timer
KICK (F)
KF3
KF2
KF1
KF0
0.72ms
0.36ms
0.18ms
0.09ms
$7X commands
Auto sequence track jump count setting
Command
Auto sequence track
jump count setting
Data 1
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is
executed and to set the jump count when fine search is executed for auto sequencer.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track
moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is
counted.
– 37 –
CXD3021R
$8X commands
MODE
specification
Data 2
Data 1
Command
D3
D2
D1
D0
D3
D2
D1
D0
VCO
VCO
CD- DOUT DOUT
WSEL
ASHS SOCT0
SEL1
SEL2
ROM Mute Mute-F
Command bit
C2PO timing
Processing
CDROM = 1
1-3
CDROM mode; average value interpolation and pre-value hold are not performed.
CDROM = 0
1-3
Audio mode; average value interpolation and pre-value hold are performed.
Processing
Command bit
DOUT Mute = 1
When Digital Out is on (MD2 pin = 1), DOUT output is muted.
DOUT Mute = 0
When Digital Out is on, DOUT output is not muted.
Processing
Command bit
D. out Mute F = 1
When Digital Out is on (MD2 pin = 1), DA output is muted.
D. out Mute F = 0
DA output mute is not affected when Digital Out is either on or off.
DA output for
48-bit slot
MD2
Other mute conditions∗
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
– ∞dB
1
0
1
0
0dB
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DOUT Mute D.out Mute F DOUT output
0dB
0dB
OFF
– ∞dB
– ∞dB
0dB
– ∞dB
0dB
0dB
– ∞dB
– ∞dB
∗ See "Mute conditions" (1), (2), and (4) to (6) under $AX commands for other mute conditions.
– 38 –
DA output for
64-bit slot
CXD3021R
$8X commands contin.
Sync protection window width
Command bit
Application
WSEL = 1
±26 channel clock
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
∗ In normal-speed playback, channel clock = 4.3218MHz.
Function
Command bit
ASHS = 0
The command transfer rate to SSP is set to normal speed.
ASHS = 1
The command transfer rate to SSP is set to half speed.
∗ See "§ 4-8. Playback Speed" for settings.
Command bit
Processing
SOCT0
SOCT1
0
—
Sub-Q is output from the SQSO pin.
1
0
Each output signal is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-4.)
1
1
The error rate is output from the SQSO pin. Input the readout clock to SQCK.
(See Timing Chart 2-6.)
—: Don't care
– 39 –
CXD3021R
$8X commands contin.
Data 2
Command
D3
MODE
specification
D2
D1
Data 3
D0
VCO
VCO
ASHS SOCT0
SEL1
SEL2
D3
D2
D1
D0
KSL3
KSL2
KSL1
KSL0
See the previous page.
Command bit
Processing
VCOSEL1 = 0
Multiplier PLL VCO1 is set to normal speed.
VCOSEL1 = 1
Multiplier PLL VCO1 is set to approximately twice the normal speed.
∗ This setting is valid only when the low-speed VCO is selected by VCO1 CS1 and CS0.
Command bit
Processing
KSL3
KSL2
0
0
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/1 frequency-divided.
0
1
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/2 frequency-divided.
1
0
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/4 frequency-divided.
1
1
Output of multiplier PLL VCO1 selected by VCO1, CS1 and CS0 is 1/8 frequency-divided.
Command bit
Processing
VCOSEL2 = 0
Wide-band PLL VCO2 is set to normal speed.
VCOSEL2 = 1
Wide-band PLL VCO2 is set to approximately twice the normal speed.
∗ This setting is valid only when the low-speed VCO is selected by VCO2CS.
Command bit
Processing
KSL1
KSL0
0
0
Output of wide-band PLL VCO2 selected by VCO2CS is 1/1 frequency-divided.
0
1
Output of wide-band PLL VCO2 selected by VCO2CS is 1/2 frequency-divided.
1
0
Output of wide-band PLL VCO2 selected by VCO2CS is 1/4 frequency-divided.
1
1
Output of wide-band PLL VCO2 selected by VCO2CS is 1/8 frequency-divided.
– 40 –
CXD3021R
$8X commands contin.
∗ Block Diagram of VCO Internal Path
VCO1SEL
No.1 VCO1
1/1
Selector
1/2
Selector
No.2 VCO1
To DSP interior
1/4
No.3 VCO1
VCO1CS1, 0
1/8
KSL3, 2
No.4 VCO1
VCO1 internal path
VCO2SEL
Selector
1/2
Selector
1/1
Low-speed
VCO2
1/4
High-speed
VCO2
VCO2CS
1/8
VCO2 internal path
– 41 –
KSL1, 0
To DSP interior
CXD3021R
$8X commands contin.
Data 4
Command
D3
MODE
specification
D2
D1
D0
VCO1 VCO1 XVCO2 VCO
CS1
CS0 THRU CS
Command bit
Processing
VCO1CS1 VCO1CS0
0
0
No.1 (Low-speed VCO for CXD3005R)
0
1
No.2 (Middle-speed VCO for CXD3005R)
1
0
No.3 (High-speed VCO for CXD3005R)
1
1
No.4
∗ The CXD3021R has four multiplier PLL VCO1s, and this command selects one of these VCO1s.
Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency.
Processing
Command bit
VCO2 THRU = 0
V16M output is connected internally to VCKI.
VCO2 THRU = 1
V16M output is not connected internally. Input the clock from VCKI.
∗ This command sets internal or external connection for the VCO2 used in CAV-W mode.
Processing
Command bit
VCO2 CS = 0
Low-speed wide-band PLL VCO2 is selected.
VCO2 CS = 1
High-speed wide-band PLL VCO2 is selected.
∗ The CXD3021R has two wide-band PLL VCO2s, and this command selects one of these VCO2s.
∗ The block diagram for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to KSL3, VCO1CS0,
VCO1CS1 and VCO2 CS is shown on the previous page.
– 42 –
CXD3021R
$8X commands contin.
MODE
specification
Data 6
Data 5
Command
D3
D2
ERC4
D1
D0
SCOR
SCSY SOCT1
SEL
Data 7
D3
D2
D1
D0
D3
D2
D1
D0
0
0
OUTL
0
FSTIN
0
0
0
Processing
Command bit
ERC4 = 0
C2 error double correction is performed when DSPB = 1.
ERC4 = 1
C2 error quadruple correction is performed even when DSPB = 1.
Processing
Command bit
SCOR SEL = 0
FSW signal is output.
SCOR SEL = 1
GRSCOR (protected SCOR) is output.
∗ Used when outputting GRSCOR from the FSW pin
Processing
Command bit
SCSY = 0
No processing.
SCSY = 1
GRSCOR (protected SCOR) synchronization is applied again.
∗ Used to resynchronize GRSCOR.
The rising edge signal of this command bit is used internally. Therefore, when resynchronizing GRSCOR, first
return the setting to 0 and then set to 1.
GRSCOR achieves the crystal accuracy by removing the jitter components included in the SCOR signal. This
signal is synchronized with PCMDATA.
The resynchronization conditions are when GTOP = high or when the SCSY pin = high.
(Same as when SCSY = 1 is sent by the $8X command.)
Command bit
Processing
No processing.
Outputs of C16M, FSTIO, GTOP, XUGF and XPLCK pins are low.
The PDO pin output is high impedance.
The power consumption can be reduced.
Command bit
Processing
FSTIN = 0
Clock switching for servo block; internally connected. (Preset)
The clock with 2/3 frequency of XTLO pin is input to the servo block.
The FSTIO pin serves as the output pin which monitors the clock for the servo block.
FSTIN = 1
Clock switching for servo block; externally input.
The FSTIO pin serves as the input pin.
The clock for the servo block is input from the FSTIO pin.
– 43 –
CXD3021R
$9X commands
Function
specification
Data 2
Data 1
Command
D3
D2
D1
DCLV
DSPB
A.SEQ
D.PLL
ON-OFF ON-OFF ON-OFF ON-OFF
Command bit
D2
D1
D0
BiliGL
MAIN
BiliGL
SUB
FLFC
XWOC
CLV mode
Contents
CLVS mode
FSW = low, MON = high, MDS = Z; MDP = servo control signal,
carrier frequency of 230Hz at TB = 0 and 460Hz at TB = 1.
CLVP mode
FSW = Z, MON = high; MDS = speed control signal,
carrier frequency of 7.35kHz; MDP = phase control signal,
carrier frequency of 1.8kHz.
DCLV on/off = 0
DCLV on/off = 1
(FSW, MON not
required)
D3
D0
CLVS and
CLVP modes
When DCLV
PWM and MD = 1
(Prohibited in CLV-W
and CAV-W modes)
MDS = PWM polarity signal, carrier
frequency of 132kHz
MDP = PWM absolute value output (binary),
carrier frequency of 132kHz
When DCLV
PWM and MD = 0
MDS = Z
MDP = ternary PWM output, carrier
frequency of 132kHz
When DCLV on/off = 1 for the Digital CLV servo, the sampling frequency of the internal digital filter switches
simultaneously with the CLVP/CLVS switching.
Therefore, the cut-off frequency for CLVS is fc = 70Hz when TB = 0, and fc = 140Hz when TB = 1.
Processing
Command bit
DSPB = 0
Normal-speed playback, C2 error quadruple correction.
DSPB = 1
Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1)
FLFC is normally 0.
FLFC is 1 in CAV-W mode for any playback speed.
Command bit
Meaning
DPLL = 0∗
RFPLL is analog. PDO, VCOI and VCOO are used.
DPLL = 1
RFPLL is digital. PDO is impedance.
∗ External parts for the FILI, FILO and PCO pins are required even when analog PLL is selected.
Command bit
BiliGL MAIN = 0
BiliGL MAIN = 1
BiliGL SUB = 0
STEREO
MAIN
BiliGL SUB = 1
SUB
Mute
Definition of bilingual capable MAIN, SUB and STEREO
The left channel input is output to the left and right channels for MAIN.
The right channel input is output to the left and right channels for SUB.
The left and right channel inputs are output to the left and right channels for STEREO.
– 44 –
CXD3021R
$9X commands contin.
Command bit
External pin
XWOC
XWO
0
L
0
H
1
L
1
H
Processing
DAC sync window is open.
DAC sync window is not open.
∗ This is used to perform resynchronization to DAC.
This command has the same function as the external pin XWO.
Set to high or 1 for the unused external pin or unused command register, respectively.
Data 3
Command
Function
specification
D3
D2
D1
D0
DAC
EMPH
DAC
ATT
SYCOF
0
Command bit
Processing
DAC EMPH = 1
Applies digital de-emphasis. The emphasis constants are τ1 = 50µs and τ2 = 15µs when
Fs = 44.1kHz.
DAC EMPH = 0
Turns digital de-emphasis off.
Command bit
Processing
DAC ATT = 1
Identical digital attenuation control is used for both the left and right channels. When
common attenuation data is specified, the attenuation values for the left channel are
used.
DAC ATT = 0
Independent digital attenuation control is used for both the left and right channels.
Command bit
Processing
SYCOF = 1
LRCK asynchronous mode.
SYCOF = 0
Normal operation.
∗ Set SYCOF = 0 in advance in order to resynchronize the DAC using $9 command XWOC or the external pin
XWO.
– 45 –
CXD3021R
$9X commands contin.
Data 4
Command
Function
specification
D3
D2
D1
D0
PLM3
PLM2
PLM1
PLM0
• DAC play mode
By controlling these command bits, the DAC output left channel and right channel can be output in 16
different combinations of left channel, right channel, left + right channel, and mute.
The relationship between the commands and the outputs is shown in the table below.
PLM3
PLM2
PLM1
PLM0
0
0
0
0
Mute
Mute
0
0
0
1
L
Mute
0
0
1
0
R
Mute
0
0
1
1
L+R
Mute
0
1
0
0
Mute
L
0
1
0
1
L
L
0
1
1
0
R
L
0
1
1
1
L+R
L
1
0
0
0
Mute
R
1
0
0
1
L
R
1
0
1
0
R
R
1
0
1
1
L+R
R
1
1
0
0
Mute
L+R
1
1
0
1
L
L+R
1
1
1
0
R
L+R
1
1
1
1
L+R
L+R
Left channel output Right channel output
Note) The output data of L + R is (L + R)/2 to prevent overflow.
– 46 –
Remarks
Mute
Reverse
Stereo
Mono
CXD3021R
$9X commands contin.
Data 5
Command
Function
specification
D3
D2
D1
D0
DAC
SMUTL
DAC
SMUTR
ZMUT
ZDPL
Processing
Command bit
DAC SMUTL = 1
Left channel soft mute is on.
DAC SMUTL = 0
Left channel soft mute is off.
Processing
Command bit
DAC SMUTR = 1
Right channel soft mute is on.
DAC SMUTR = 0
Right channel soft mute is off.
Processing
Command bit
ZMUT = 1
Zero detection mute is on.
ZMUT = 0
Zero detection mute is off.
Processing
Command bit
ZDPL = 1
LMUTO and RMUTO are high during mute.
ZDPL = 0
LMUTO and RMUTO are low during mute.
∗ See the description of "Mute flag output" for the mute flag output conditions.
– 47 –
CXD3021R
Command
Data 6
Data 7
D3
D2
D1
D0
D3
D2
D1
D0
0
0
0
SLBS
DIV4
DSP
SLEEP
DSSP
SLEEP
DAC
SLEEP
Function
specification
This command bit switches the audio serial output format from the DA12, 13 and 14 pins.
32-bit slot or 64-bit slot can be selected.
Processing
Command bit
SLBS = 0
32-bit/64-bit slot outputs switching; 64-bit slot output. (Preset)
SLBS = 1
32-bit/64-bit slot outputs switching; 32-bit slot output. (Preset)
The master clock of the digital PLL is switched.
The conventional mode or 2/3 mode of the conventional one can be selected.
Processing
Command bit
DIV4 = 0
Digital PLL master clock; conventional mode. (Preset)
DIV4 = 1
Digital PLL master clock; 2/3 mode.
Note) Do not set DIV4 to 1 when DSPB=0.
Processing
Command bit
DSP SLEEP = 0
Normal operation
DSP SLEEP = 1
Multiplier PLL VCO1, wide-band PLL VCO2 oscillation and the DSP block clock are halted.
Power consumption can be reduced.
Command bit
Processing
DSSP SLEEP = 0
Normal operation
DSSP SLEEP = 1
Servo block clock is halted and the MDP pin is high impedance.
Power consumption can be reduced
∗ Command writing related to the servo is invalid when DSSP SLEEP=1.
Processing
Command bit
DAC SLEEP = 0
Normal operation
DAC SLEEP = 1
DAC block clock is halted.
Power consumption can be reduced.
∗ Command writing related to the audio DAC is invalid when DAC SLEEP=1.
– 48 –
CXD3021R
$AX commands
Data 1
Command
Audio CTRL
Command bit
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
0
0
Mute
ATT
PCT1
PCT2
MCSL
SOC2
Command bit
Meaning
Mute = 0
Mute off if other mute
conditions are not set.
Mute = 1
Mute on. Peak register reset.
Meaning
ATT = 0
Attenuation off.
ATT = 1
–12dB
Mute conditions
(1) When register A mute = 1.
(2) When Mute pin = 1.
(3) When register 8 D.out Mute F = 1 and the Digital Out is on (MD2 pin = 1).
(4) When GFS stays low for over 35 ms (during normal speed).
(5) When register 9 BiliGL MAIN = Sub = 1.
(6) When register A PCT1 = 1 and PCT2 = 0.
(1) to (4) perform zero-cross muting with a 1ms time limit.
Command bit
Meaning
PCM Gain
ECC error correction ability
PCT1
PCT2
0
0
Normal mode
× 0dB
C1: double; C2: quadruple
0
1
Level meter mode
× 0dB
C1: double; C2: quadruple
1
0
Peak meter mode
Mute
C1: double; C2: double
1
1
Normal mode
× 0dB
C1: double; C2: double
Description of level meter mode (see Timing Chart 1-4.)
• When the LSI is set to this mode, it performs digital level meter functions.
• When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO.
The initial 80 bits are Sub-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are 15bit PCM data (absolute values) and an L/R flag.
The L/R flag is high when the 15-bit PCM data is from the left channel and low when the data is from the right
channel.
• The PCM data is reset and the L/R flag is reverted after one readout.
Then maximum value measuring continues until the next readout.
– 49 –
CXD3021R
$AX commands contin.
Description of peak meter mode (see Timing Chart 1-5.)
• When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the
left or right channel.
The 96-bit clock must be input to SQCK to read out this data.
• When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal
register again.
In other words, the PCM maximum value detection register is not reset by the readout.
• To reset the PCM maximum value register to zero, set PCT1 = PCT2 = 0 or set the $AX mute.
• The Sub-Q absolute time is automatically controlled in this mode.
In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in
the memory. Normal operation is conducted for the relative time.
• The final bit (L/R flag) of the 96-bit data is normally 0.
• The pre-value hold and average value interpolation data are fixed to level (– ∞) for this mode.
Command bit
Processing
MCSL = 1
DF/DAC block master clock is selected. Crystal = 768Fs (33.8688MHz)
MCSL = 0
DF/DAC block master clock is selected. Crystal = 384Fs (16.9344MHz)
Note) See "§ 4-9. DAC Block Playback Speed".
Command bit
Processing
SOC2 = 0
The SENS signal is output from the SENS pin as usual.
SOC2 = 1
The SQSO pin signal is output from the SENS pin.
SENS output switching
• This command enables the SQSO pin signal to be output from the SENS pin.
When SOC2 = 0, SENS output is performed as usual. See "§ 1-4. Description of SENS Signals".
When SOC2 = 1, the SQSO pin signal is output from the SENS pin.
At this time, the readout clock is input to the SCLK pin.
Note) SOC2 should be switched when SQCK = SCLK = high.
– 50 –
CXD3021R
$AX commands contin.
Data 3
Command
Audio CTRL
D3
D2
D1
D0
DCOF
FMUT
BSBST
BBSL
Processing
Command bit
DCOF = 1
DC offset is off.
DCOF = 0
DC offset is on.
∗ Set DC offset to off when zero detection mute is on.
Processing
Command bit
FMUT = 1
Forced mute is on.
FMUT = 0
Forced mute is off.
Command bit
Processing
BSBST = 1
Bass boost on.
BSBST = 0
Bass boost off.
Processing
Command bit
BBSL = 1
Bass boost MAX.
BBSL = 0
Bass boost MID.
– 51 –
CXD3021R
$AX commands contin.
Data 5
Data 4
Command
Audio CTRL
D3
D2
D1
D0
D3
D2
D1
Data 6
D0
D3
D2
D1
D0
ATTCH
ATD10 ATD9 ATD8 ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0
SEL
Command bit
Processing
ATTCH SEL = 1
Right channel attenuation data can be set.
ATTCH SEL = 0
Left channel attenuation data can be set.
Command bit
ATD10 to 0
Meaning
Attenuation data
The attenuation data consists of 11 bits each for the left and right channels; the DAC ATT bit can be used to
control the left and right channels with common attenuation data. When common attenuation data is specified,
the attenuation values for the left channel are used.
Attenuation data
Audio output
400H
0dB
3FFH
3FEH
:
001H
–0.0085dB
–0.017dB
:
–60.206dB
000H
–∞
The audio output, from 001H to 400H, is determined
according to the following equation:
Attenuation data
1024
Audio output = 20log
[dB]
$BX commands
This command sets the traverse monitor count.
Command
Data 1
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Traverse monitor count
setting
215 214 213 212 211 210
29
28
27
26
25
24
23
22
21
20
• When the set number of tracks are counted during fine search, the sled control for the traverse cycle control
goes off.
• The traverse monitor count is set to monitor the traverse status from the SENS output as COMP and COUT.
– 52 –
CXD3021R
$CX commands
Data 1
Command
D3
D1
D2
Data 2
D0
D3
Description
D1
D2
D0
Gain Gain Gain Gain Gain Gain
Spindle servo
PCC1 PCC0 Valid only when DCLV = 1.
coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0
Gain
CLVS
CLV CTRL ($DX)
Valid when DCLV = 1 or 0.
The spindle servo gain is externally set when DCLV = 1
• CLVS mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
Note) When DCLV = 0, the CLVS gain is as follows.
When Gain CLVS = 0, GCLVS = –12dB.
When Gain CLVS = 1, GCLVS = 0dB.
• CLVP mode gain setting: GMDP : GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
• DCLV overall gain setting: GDCLV
Gain
DCLV1
Gain
DCLV0
GDCLV
0
0
0dB
0
1
+6dB
1
0
+12dB
Command bit
Processing
PCC1
PCC0
0
0
The VPCO1 and 2 signals are output.
0
1
The VPCO1 and 2 pin outputs are high impedance.
1
0
The VPCO1 and 2 pin outputs are low.
1
1
The VPCO1 and 2 pin outputs are high.
• These command bits controls the VPCO1 and VPCO2 pin signals.
Identical control can be performed for both VPCO1 and VPCO2 outputs with this setting. However, VPCO2 can
also be set to high impedance with the $E command FCSW separately from this setting.
– 53 –
CXD3021R
$CX commands contin.
• Processing for the $CX commands PCC1 and PCC0 and the $EX command FCSW is shown below.
Command bit
Processing
FCSW
PCC1
PCC0
0
0
0
The VPCO1 pin signal is output and the VPCO2 pin is high impedance.
0
0
1
The VPCO1 and 2 pin outputs are high impedance.
0
1
0
The VPCO1 pin output is low and the VPCO2 pin is high impedance.
0
1
1
The VPCO1 pin output is high and the VPCO2 pin is high impedance.
1
0
0
The VPCO1 and 2 signals are output.
1
0
1
The VPCO1 and 2 pin outputs are high impedance.
1
1
0
The VPCO1 and 2 pin outputs are low.
1
1
1
The VPCO1 and 2 pin outputs are high.
Command
Data 4
Data 3
D3
D2
D1
D0
D3
D2
D1
D0
Spindle servo
SFP3 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0
coefficient setting
Command bit
SFP3 to 0
Processing
Sets the frame sync forward protection times. The setting range is 1 to F (Hex).
Command bit
SRP3 to 0
Processing
Sets the frame sync backward protection times. The setting range is 1 to F (Hex).
∗ See "§ 4-2. Frame Sync Protection" regarding frame sync protection.
– 54 –
CXD3021R
$CX commands contin.
• The CXD3021R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC0 to 7 from
the SQSO pin and monitor this data using a microcomputer.
In order to output error rate data, set $C commands for C1 and C2 individually, and set SOCT0 and SOCT1
= 0 of $8 command. Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses.
See Timing Chart 2-6.
Command
Data 5
D3
D2
D1
Data 6
D0
D3
D2
D1
D0
Spindle servo
EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0
coefficient setting
Error rate monitor commands
Command bit
EDC7 = 0 EDC6
Processing
The [No C1 errors, pointer set] count is output when 1.
EDC5
The [One C1 error corrected, pointer reset] count is output when 1.
EDC4
The [No C1 errors, pointer set] count is output when 1.
EDC3
The [One C1 error corrected, pointer set] count is output when 1.
EDC2
The [Two C1 errors corrected, pointer set] count is output when 1.
EDC1
The [C1 correction impossible, pointer set] count is output when 1.
7350-frame count cycle mode∗1 when 0.
73500-frame count cycle mode∗2 when 1.
EDC0
EDC7 = 1 EDC6
The [No C2 errors, pointer reset] count is output when 1.
EDC5
The [One C2 error corrected, pointer reset] count is output when 1.
EDC4
The [Two C2 errors corrected, pointer reset] count is output when 1.
EDC3
The [Three C2 errors corrected, pointer reset] count is output when 1.
EDC2
The [Four C2 errors corrected, pointer reset] count is output when 1.
EDC1
The [C2 correction impossible, pointer copy] count is output when 1.
EDC0
The [C2 correction impossible, pointer set] count is output when 1.
∗1 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every 7350
frames.
∗2 The number selected by C1 (EDC1 to 6) and C2 (EDC0 to 6) is added to C1 and C2 and output every
73500 frames.
– 55 –
CXD3021R
$DX commands
Data 1
Command
CLV CTRL
D3
D2
D1
D0
DCLV
PWM MD
TB
TP
Gain
CLVS
See "$CX commands".
Command bit
Description
DCLV PWM MD = 1
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes cannot be used.
DCLV PWM MD = 0
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Command bit
Description
TB = 0
Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes.
TB = 1
Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes.
TP = 0
Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1
Peak hold at a cycle of RFCK/2 in CLVS mode.
– 56 –
CXD3021R
$DX commands contin.
Data 2
Command
CLV CTRL
Data 3
Data 4
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
VP
CTL1
VP
CTL0
0
0
Command bit
Processing
VP0 to 7
The spindle rotational velocity is set.
Command bit
Processing
VPCTL1
VPCTL0
0
0
The setting of VP0 to 7 is multiplied by 1.
0
1
The setting of VP0 to 7 is multiplied by 2.
1
0
The setting of VP0 to 7 is multiplied by 3.
1
1
The setting of VP0 to 7 is multiplied by 4.
∗ The above setting should be 0, 0 except for the CAV-W operating mode.
The rotational velocity R of the spindle can be expressed with the following equation.
R=
256 – n
×l
32
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
1: Multiple set by VPCTL0, 1
– 57 –
CXD3021R
$DX commands contin.
Command bit
Description
VP0 to 7 = F0 (Hex)
Playback at 1/2 (1, 2) × speed
Playback at 3 (6, 12) × speed
…
…
VP0 to 7 = 80 (Hex)
Playback at 2 (4, 8) × speed
…
…
VP0 to 7 = A0 (Hex)
Playback at 1 (2, 4) × speed
…
…
VP0 to 7 = C0 (Hex)
…
…
VP0 to 7 = E0 (Hex)
Playback at 4 (8, 16) × speed
…
…
VP0 to 7 = 60 (Hex)
Playback at 5 (10, 20) × speed
…
…
VP0 to 7 = 40 (Hex)
Playback at 6 (12, 24) × speed
…
…
VP0 to 7 = 20 (Hex)
Playback at 7 (14, 28) × speed
…
…
VP0 to 7 = 00 (Hex)
Playback at 8 (16, 32) × speed
Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.
2. Regarding the values in parentheses, the former ones are for when DSPB is 1 and VPCTL0, 1 = 0,
and the latter ones are for when DSPB is 1, VPCTL0 = 1 and VPCTL1 = 0.
– 58 –
CXD3021R
$DX commands contin.
16
14
R – Relative velocity [Multiple]
12
10
8
DSPB = 1
6
4
DSPB0 = 0
2
E0
C0
A0
80
60
40
20
00
When VPCTL0 = VPCTL1 = 0
VP0 to 7 setting value [H]
32
28
R – Relative velocity [Multiple]
24
20
16
DSPB = 1
12
8
DSPB = 0
4
E0
C0
A0
80
VP0 to 7 setting value [H]
– 59 –
60
40
20
00
When VPCTL0 = 1, VPCTL1 = 0
CXD3021R
$EX commands
Data 1
Command
SPD mode
D3
D2
D1
CM3
CM2
CM1
Data 2
D0
D3
D2
Data 3
D1
D0
CM0 EPWM SPDC ICAP
Command bit
D3
SFSL VC2C
D2
D1
D0
HIFC LPWR VPON
Description
Mode
CM3
CM2
CM1
CM0
0
0
0
0
STOP
Spindle stop mode.∗1
1
0
0
0
KICK
Spindle forward rotation mode.∗1
1
0
1
0
BRAKE
Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.∗1
1
1
1
0
CLVS
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
1
1
1
1
CLVP
PLL servo mode.
0
1
1
0
CLVA
Automatic CLVS/CLVP switching mode.
Used for normal playback.
∗1 See Timing Charts 1-6 to 1-12.
Command bit
EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON
Mode
INV
VPCO
Description
0
0
0
0
0
0
0
0
0
CLV-N Crystal reference CLV servo.
0
0
0
0
1
1
0
0
0
CLV-W
0
1
1
0
0
1
0
1
0
CAV-W Spindle control with VP0 to 7.
1
0
1
0
0
1
0
1
0
CAV-W
0
0
0
0
0
1
0
1
1
Used for playback in CLV-W
mode.∗2
Spindle control with the external
PWM.
VCO-C VCO control∗3
∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
∗3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode.
– 60 –
CXD3021R
$EX commands contin.
Mode
DCLV
0
CLV-N
DCLV PWM MD
0
0
LPWR
0
0
1
1
0
0
CLV-W
1
0
1
0
CAV-W
1
0
1
Mode
DCLV
CLV-N
1
CLV-W
CAV-W
1
1
Command
Timing chart
KICK
1-6 (a)
BRAKE
1-6 (b)
STOP
1-6 (c)
KICK
1-7 (a)
BRAKE
1-7 (b)
STOP
1-7 (c)
KICK
1-8 (a)
BRAKE
1-8 (b)
STOP
1-8 (c)
KICK
1-9 (a)
BRAKE
1-9 (b)
STOP
1-9 (c)
KICK
1-10 (a)
BRAKE
1-10 (b)
STOP
1-10 (c)
KICK
1-11 (a)
BRAKE
1-11 (b)
STOP
1-11 (c)
KICK
1-12 (a)
BRAKE
1-12 (b)
STOP
1-12 (c)
DCLV PWM MD
LPWR
Timing chart
0
0
1-13
1
0
1-14
0
1-15
1
1-16
0
1-17 (EPWM = 0)
1
1-18 (EPWM = 0)
0
1-19 (EPWM = 1)
1
1-20 (EPWM = 1)
0
0
Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV to 1 and DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 61 –
CXD3021R
$EX commands contin.
Data 4
Command
SPD mode
D3
D2
D1
D0
Gain
CAV1
Gain
CAV0
FCSW
INV
VPCO
Gain
CAV1
Gain
CAV0
0
0
0dB
0
1
–6dB
1
0
–12dB
1
1
–18dB
Gain
• This sets the gain when controlling the spindle with VP7 to 0 in
CAV-W mode.
Note) Gain CAV1, 0 commands are invalid for spindle control
with the external PWM.
Processing
Command bit
FCSW = 0
The VPCO2 pin is not used and it is high impedance.
FCSW = 1
The VPCO2 pin is used and the pin signal is the same as VPCO1.
– 62 –
– 63 –
C2PO
CDROM = 1
C2PO
CDROM = 0
WDCK
LRCK
Timing Chart 1-3
C2 Pointer for lower 8 bits
Rch C2 Pointer
C2 Pointer for upper 8 bits
Rch 16-bit C2 Pointer
C2 Pointer for lower 8 bits
Lch C2 Pointer
C2 Pointer for upper 8 bits
Lch 16-bit C2 Pointer
If C2 Pointer = 1,
data is NG
48 bit slot
CXD3021R
– 64 –
SQSO
SQCK
WFCK
SQSO CRCF
SQCK
2
L/R
2
3
Sub Q Data
See "Sub Code Interface"
3
96-bit data
Hold section
1
96 clock pulses
1
Timing Chart 1-4
D0
CRCF
81
D2
1
Level Meter Timing
16 bits
96 clock pulses
D1
Peak data of this section
80
D4
D5
D6
R/L
2
3
CRCF
15-bit peak-data
Absolute value display, LSB first
D3
750ns to 120µs
D13
D14
L/R
Peak data
L/R flag
96
CXD3021R
SQCK
WFCK
– 65 –
96 clock pulses
Measurement
CRCF
Timing Chart 1-5
1
2
3
Peak Meter Timing
Measurement
CRCF
96 clock pulses
1
2
3
Measurement
CRCF
CXD3021R
CXD3021R
Timing Chart 1-6
CLV-N mode DCLV = DCLV PWM MD = LPWR = 0
KICK
Z
MDS
H
MDP
FSW
L
BRAKE
Z
MDS
MDP
L
FSW
L
MDS
MDP
FSW
Z
L
L
H
H
MON
STOP
MON
MON
(b) BRAKE
(a) KICK
L
(c) STOP
Timing Chart 1-7
CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
Z
MDS
MDP
FSW
MON
BRAKE
Z
MDS
STOP
MDS
Z
MDP
Z
Z
H
MDP
Z
L
H
(a) KICK
L
FSW
L
FSW
L
H
MON
MON
(b) BRAKE
– 66 –
L
(c) STOP
CXD3021R
Timing Chart 1-8
CLV-N mode DCLV = DCLV PWM MD = 1, LPWR = 0
KICK
BRAKE
STOP
H
MDS
MDS
H
L
MDS
H
MDP
MDP
MDP
L
FSW
L
L
H
MON
L
FSW
L
FSW
L
H
MON
MON
(a) KICK
(b) BRAKE
L
(c) STOP
Timing Chart 1-9
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
Z
MDS
BRAKE
Z
MDS
FSW
MON
MDS
Z
MDP
Z
Z
H
MDP
STOP
MDP
Z
L
H
L
FSW
L
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
L
H
MON
(a) KICK
FSW
MON
(b) BRAKE
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (b).
– 67 –
L
(c) STOP
CXD3021R
Timing Chart 1-10
CLV-W mode (when following the spindle rotational velocity) DCLV = 1, DCLV PWM MD = 0, LPWR = 1
KICK
Z
MDS
MDP
H
Z
FSW
L
BRAKE
MDS
Z
MDS
Z
MDP
Z
MDP
Z
FSW
L
FSW
L
H
H
MON
MON
STOP
MON
(c) STOP
(b) BRAKE
(a) KICK
L
Other than when following the velocity,
the timing is the same as Timing Chart 1-6 (a).
Timing Chart 1-11
CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0
KICK
MDS
MDP
FSW
Z
H
L
BRAKE
Z
MDS
MDP
L
FSW
L
H
MON
MDS
Z
MDP
Z
FSW
H
MON
(a) KICK
STOP
L
H
MON
(b) BRAKE
– 68 –
(c) STOP
CXD3021R
Timing Chart 1-12
CAV-W mode DCLV = 1, DCLV PWM MD = 0, LPWR = 1
KICK
Z
MDS
H
MDP
FSW
L
BRAKE
MDS
Z
MDS
Z
MDP
Z
MDP
Z
FSW
L
H
MON
STOP
FSW
L
H
MON
H
MON
(a) KICK
(b) BRAKE
(c) STOP
Timing Chart 1-13
CLV-N mode DCLV PWM MD = LPWR = 0
MDS
Z
n • 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
7.6µs
Deceleration
Timing Chart 1-14
CLV-N mode DCLV PWM MD = 1, LPWR = 0
MDS
Acceleration
Deceleration
MDP
132kHz
n • 236 (ns) n = 0 to 31
7.6µs
Output Waveforms with DCLV = 1
– 69 –
CXD3021R
Timing Chart 1-15
CLV-W mode DCLV PWM MD = LPWR = 0
Z
MDS
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Output Waveforms with DCLV = 1
Timing Chart 1-16
CLV-W mode DCLV PWM MD = 0, LPWR = 1
MDS
Z
Acceleration
MDP
Z
264kHz
3.8µs
Output Waveforms with DCLV = 1
The BRAKE pulse is maked when LPWR = 1.
Timing Chart 1-17
CAV-W mode EPWM = DCLV PWM MD = LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 1-18
CAV-W mode EPWM = DCLV PWM MD = 0, LPWR=1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is maked when LPWR = 1.
– 70 –
CXD3021R
Timing Chart 1-19
CAV-W mode EPWM = 1, DCLV PWM MD = LPWR = 0
H
PWMI
L
Acceleration
H
MDP
L
Deceleration
Timing Chart 1-20
CAV-W mode EPWM = 1, DCLV PWM MD = 0, LPWR = 1
H
PWMI
L
Acceleration
H
MDP
Z
The BRAKE pulse is masked when LPWR = 1.
Note)
CLV-W and CAV-W modes support control only by the ternary output of the MDP pin.
Therefore, set DCLV PWM MD to 0 in CLV-W and CAV-W modes.
– 71 –
CXD3021R
[2] Subcode Interface
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK.
Sub-Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§ 2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
§ 2-2. 80-bit Sub-Q Readout
Fig. 2-2 shows the peripheral block of the 80-bit Sub-Q register.
• First, Sub-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial
register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others.
• The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial
register.
For ring control 1, input and output are shorted during peak meter and level meter modes.
For ring control 2, input and output are shorted during peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
• The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 72 –
CXD3021R
Timing Chart 2-1
Internal
PLL clock
4.3218 ± ∆MHz
WFCK
SCOR
EXCK
750ns max
SBSO
S0 · S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0 · S1 Q R S T U V W S0 · S1
Same
P1
Q R S T
U V W
P1
Same
Subcode P.Q.R.S.T.U.V.W Read Timing
– 73 –
P2
P3
SUBQ
(AFRAM)
SI
8
(ASEC)
LD
Order
Inversion
8
(AMIN)
LD
SUBQ
LD
– 74 –
LD
LD
Peak detection
16
16-bit P/S register
Monostable
multivibrator
8
SI
8
8
Ring control 2
SHIFT
8
LD
SO
LOAD CONTROL
CRCC
80-bit P/S Register
8
80-bit S/P Register
SHIFT
8
CRCF
Mix
8
ADDRS CTRL
LD
Ring control 1
ABS time load control
for peak value
H G F E D C B A
A B C D E F G H
SIN
Block Diagram 2-2
SQCK
SO
SQSO
CXD3021R
LD
– 75 –
SQSO
SQCK
SQCK
SQSO
SCOR
WFCK
CRCF
Monostable
Multivibrator
(Internal)
Timing Chart 2-3
CRCF1
1
2
3
2
1
ADR1
ADR2
ADR3
CTL0
270 to 400µs when SQCK = high.
Register load forbidder
CRCF1
94
Determined by mode
93
92
91
80 or 96 Clocks
750ns to 120µs
300ns max
ADR0
3
95
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD3021R
PER0
750ns or more
GFS LOCK EMPH
Description
PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK
Internal signal latch
ALOCK
VF0
– 76 –
C1F1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C1F0
C1 correction impossible; C1 pointer set
Two C1 errors corrected; C1 pointer set
One C1 error corrected; C1 pointer set
No C1 errors; C1 pointer set
—
—
One C1 error corrected; C1 pointer reset
No C1 errors; C1 pointer reset
Description
C2F1
0
0
1
1
0
0
1
1
C2F2
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
C2F0
C2 correction impossible; C2 pointer set
C2 correction impossible; C1 pointer copy
—
Four C2 errors corrected; C2 pointer reset
Three C2 errors corrected; C2 pointer reset
Two C2 errors corrected; C2 pointer reset
One C2 error corrected; C2 pointer reset
No C2 errors; C2 pointer reset
Description
Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB.
VF0 to 9
C1F2
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive
samples, this pin outputs low.
VF9
ALOCK
VF8
High when the playback disc has emphasis.
VF7
EMPH
VF6
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low.
VF5
LOCK
VF4
High when the frame sync and the insertion protection timing match.
VF3
GFS
VF2
Focus OK.
VF1
FOK
PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Signal
SQSO
SQCK
XLAT
Set SQCK high during this interval.
Example: $802000 latch
Timing Chart 2-4
CXD3021R
CXD3021R
Timing Chart 2-5
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(V16M/2)
Measurement counter
Load
m
VF0 to 9
The relative velocity of the disc can be obtained with the following equation.
R=
(m + 1)
(R: Relative velocity, m: Measurement results)
32
VF0 to 9 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63
when it is rotating at double speed (when DSPB is low).
– 77 –
SQSO
SQCK
XLAT
C1 MSB 19
Timing Chart 2-6
– 78 –
0
7
3
C1 error rate
18 17 16 15 14 13 12 11 10 9
8
7
6
5
5
4
3
2
0
1
0
7
8
3
C2 error rate
0 19 18 17 16 15 14 13 12 11 10 9
7
6
5
5
4
3
2
0
1
0
CXD3021R
CXD3021R
[3] Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
§ 3-1. CLV-N Mode
This mode is compatible with the CXD2510Q, and operation is the same as for conventional control (however,
variable pitch cannot be used). The PLL capture range is ±150kHz.
§ 3-2. CLV-W Mode
This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is
the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.
(When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from
the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to
the VCKI pin.)
When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is
stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc,
then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin.
CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must
return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow
according to the microcomputer software in CLV-W mode is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set
high, deceleration pulses are not output, thereby achieving low power consumption mode.
CLV-W mode supports control only by the ternary output of the MDP pin. Therefore, when using CLV-W mode,
set DCLV PWM MD to low.
Note) The capture range for this mode is theoretically up to the signal processing limit.
§ 3-3. CAV-W Mode
This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the
desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the
external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command
and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed
to 32× speed. (See "$DX commands".) When controlling the spindle with the external PWM, CAV-W mode is
set with the $E6A5X command. Then, the PWMI pin is binary input which becomes KICK during high intervals
and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement
is a signal of 132.3kHz obtained by 1/128-frequency dividing the crystal (XTLI, XTLO) (384Fs). The velocity is
obtained by counting the half of V16M pulses while the reference is high, and the result is output from the new
CPU interface as 10 bits (VF0 to 9). These measurement results are 31 when the disc is rotating at normal
speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with
VP0 to VP7. (See Table 2-5 and Fig. 2-6.)
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc.
Note) The capture range for this mode is theoretically up to the signal processing limit.
Note) Set FLFC to 1 for this mode.
– 79 –
CXD3021R
§ 3-4. VCO-C Mode
This is VCO control mode. In this mode, the V16M oscillation frequency can be controlled by setting $D
commands VP0 to VP7 and VPCTL0, 1. The V16M oscillation frequency can be expressed by the following
equation.
V16M =
1 (256 – n)
32
n: VP0 to VP7 setting value
1: VPCTL0, 1 setting value
The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the
following equation.
• When DSPB = 0
VCO1 = V16M ×
49
24
• When DSPB = 1
VCO1 = V16M ×
49
16
– 80 –
CXD3021R
CAV-W
CLV-W
Operation mode
Rotational velocity
CLVS
CLVP
Spindle mode
Target speed
KICK
Time
LOCK
ALOCK
Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode
CLV-W Mode
CLV-W MODE
START
KICK
$E8000
Mute OFF $A00XXXX
CAV-W $E665X
(CLVA)
NO
ALOCK = H ?
YES
CLV-W $E6C00
(CLVA)
(WFCK PLL)
YES
ALOCK = L ?
NO
Fig. 3-2. CLV-W Mode Flow Chart
– 81 –
CXD3021R
VCO-C Mode
Access START
R?
(How many minutes
of absolute time?)
n?
(Calculate n)
Transfer
$E00510
Transfer
$DX ∆XX
What is the playback speed when access ends?
Calculate VP0 to VP7.
Switch to VCO control mode.
EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0
HIFC = VPON = 1
Transfer VP0 to VP7. (
∆ corresponds to VP0 to VP7.)
Track Jump
Subroutine
Transfer
$E66500
Switch to normal-speed playback mode.
EPWM = SFSL = VC2C = LPWR = 0
SPDC = ICAP = HIFC = VPON = 1
Access END
Fig. 3-3. Access Flow Chart Using VCO Control
– 82 –
CXD3021R
[4] Description of Other Functions
§ 4-1. Channel Clock Recovery by Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T.
In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that
is the channel clock, is necessary.
In an actual player, a PLL is necessary to recover the channel clock because the fluctuation in the spindle
rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD3021R has a built-in three-stage PLL.
• The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when
not using the internal VCO2, external LPF and VCO are necessary.
The output of first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that recovers the actual channel clock.
• The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the
secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency
components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields
better playability. However, in this case the capture range becomes ±50kHz.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
– 83 –
CXD3021R
Block Diagram 4-1
CLV-W
CAV-W
Selector
Spindle rotation information
Clock input
1/2
XTLI
XTSL
1/2
1/n
1/l
Phase comparator
1/32
VPCO1, 2
CLV-N
CLV-W
CAV-W /CLV-N
l = 1, 2, 3, 4
(VPCTL0, 1)
n = 1 to 256
(VP7 to VP0)
LPF
VCOSEL2
Microcomputer
control
1/K
(KSL1, 0)
VCTL
VCO2
V16M
VCKI
VPON
1/M
1/N
Phase comparator
2/1 MUX
PCO
FILI
FILO
1/K
(KSL3, 2)
CLTV
VCO1
VCOSEL1
Digital PLL
RFPLL
– 84 –
CXD3021R
§ 4-2. Frame sync protection
• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD3021R, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths; one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 12∗, and the
backward protection counter to 3∗. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches, a maximum of 12 frames are inserted. If the frame sync cannot be
detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
∗ Default values. These values can be set as desired by $C commands SFP0 to 3 and SRP0 to 3.
§ 4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD3021R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2.
• In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the
C1 error status, the playback status of the EFM signal, and the operating status of the player.
• The correction status can be monitored externally.
See Table 4-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT2
MNT1
MNT0
0
0
0
0
No C1 errors;
C1 pointer reset
0
0
0
1
One C1 error corrected;
C1 pointer reset
0
0
1
0
—
0
0
1
1
—
0
1
0
0
No C1 errors;
C1 pointer set
0
1
0
1
One C1 error corrected;
C1 pointer set
0
1
1
0
Two C1 errors corrected;
C1 pointer set
0
1
1
1
C1 correction impossible;
C1 pointer set
1
0
0
0
No C2 errors;
C2 pointer reset
1
0
0
1
One C2 error corrected;
C2 pointer reset
1
0
1
0
Two C2 errors corrected;
C2 pointer reset
1
0
1
1
Three C2 errors corrected;
C2 pointer reset
1
1
0
0
Four C2 errors corrected;
C2 pointer reset
1
1
0
1
1
1
1
0
C2 correction impossible;
C1 pointer copy
1
1
1
1
C2 correction impossible;
C2 pointer set
Description
—
Table 4-2.
– 85 –
CXD3021R
Timing Chart 4-3
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT2
MNT1
MNT0
Strobe
Strobe
§ 4-4. DA Interface Output
• The CXD3021R has two DA interface output modes.
1) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
2-a) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
2-b) 32-bit slot interface
This interface includes 32 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
Note) The 32-bit and 64-bit slot outputs can not be output simultaneously because the common pin is used by
switching with the command. (SLSB of $9X command)
– 86 –
R0
1
2
– 87 –
DA16
WDCK
DA15
(4.23M)
LRCK
(88.2K)
R0
1 2
3
4
5
Lch MSB (15)
Lch MSB (15)
48-bit Slot Double-Speed Playback
DA16
WDCK
DA15
(2.12M)
LRCK
(44.1K)
48-bit Slot Normal-Speed Playback PSSL = L
Timing Chart 4-4
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
Rch MSB
CXD3021R
1
2
3
4
– 88 –
DA14
DA13
(5.64M)
DA12
(88.2K)
L15
1
2
3
4
5
64-bit Slot Double-Speed Playback
DA14
DA13
(2.82M)
DA12
(44.1K)
5
6
64-bit Slot Normal-Speed Playback PSSL = L
Timing Chart 4-5
9
10
10
Rch LSB (0)
8
Rch LSB (0)
7
11
12
15
13
14
15
1
2
3
20
4
1
5
2
6
3
20
7
8
25
4
9
5
7
9
10
30 31 32
8
10 11 12 13 14 15
6
11
13
Lch LSB
12
30
32
14 R15
31
Lch LSB (0)
CXD3021R
L15
1
R0
2
R1
– 89 –
DA14
DA13
(4.23M)
LRCK
(88.2K)
L15 R0
1
R1 R2 R3 R4
5
32-bit Slot Double-Speed Playback
DA14
DA13
(2.12M)
LRCK
(44.1K)
32-bit Slot Normal-Speed Playback
Timing Chart 4-6
3
R5 R6
R2
4
R7 R8
R3
R4
6
R5
7
R6
15
R7
16
8
R9 R10 R11 R12 R13 R14 R15 L0
10
5
9
L1
R8
L2
L3
R9
10
R10
11
R11
12
R12
13
R13
14
R14
15
R15
16
L0
CXD3021R
CXD3021R
§ 4-5. Digital Out
There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,
and the type 2 form 2 format for the manufacture of software.
The CXD3021R supports type 2 form 1.
This LSI supports 2 kinds of Digital Out generation methods; one is to generate the Digital Out using the PCM
data read out from the disc and the other is to generate it using the DA interface input (PCMDI, LRCKI and
BCKI).
§ 4-5-1. Digital Out From PCM Data
The Digital Out is generated from the PCM data which is read out from the disc.
The clock accuracy of the channel status is automatically set to level II when the crystal clock is used and to
level III in CAV-W mode. In addition, the Sub-Q data matched twice continuously with CRC check are input to
the initial 4 bits (bits 0 to 3).
DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1.
Therefore, DOUT is set to off by making the MD2 pin to 0.
Digital Out C bit
0
2
3
From sub Q
0
ID0
16
1
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
ID1 COPY Emph
0
0
0
32
48
0
176
bits 0 to 3
bit 29
Sub-Q control bits that matched twice with CRCOK
VPON: 1 X'tal: 0
Table 4-6-1.
– 90 –
CXD3021R
§ 4-5-2. Digital Out From DA Interface Input
The Digital Out is generated from the DA interface.
Validity Flag and User Data
The Validity Flag and User Data are fixed to 0.
Channel Status Data
For the Channel Status Data, bits 0, 6 and 7 are fixed to 0. The following items can be set by bits 1, 2, 3 and 8.
a) Digital data/audio data
b) Digital copy enabled/ prohibited
c) With/without pre-emphasis
d) Category code (two types possible)
Digital Out C bit
0
0
0
16
0
1
2
3
A/D COPY EMPH
D
SEL En
0
0
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
CAT
b8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
32
48
0
176
Table 4-6-2.
Note) In this method, DOUT can be set to off by making the MD pin to 0 and $34A command DOUT EN to 0.
– 91 –
CXD3021R
Digital Audio Data Input
The input signal of the digital audio data is input from the DAC input pins PCMDI, LRCKI and BCKI. The input
format supports 48-bit slot/MSB first.
Mute Function
By setting the command bit DOUT_DMUT to 1, all the audio data portions in the Digital Out output can be
made to 0 with the Channel Status Data as it is.
Input/Output Synchronization Circuit
In the normal operation, the DAC automatically synchronizes with the input LRCK. However, when the input
data has much jitter or the power is turned on the synchronization may not be achieved. In such a case, the
internal operation should be forcibly synchronized by setting $34A DOUT WOD to 1. Also, the forcible
synchronization is required when the operating frequency is changed such as switching between CLV and
CAV, etc. Be sure to set DOUT WOD to 0 before performing forcible synchronization again.
∗ When the synchronization is performed, the internal counter which counts the frames is cleared so that the
frame is started from 0 after the synchronization processed. In case where the automatic processing of the
synchronization is not desirable or the user wants to do it manually, set the command $34A WIN EN to 0 to
invalidate the automatic synchronization circuit.
Clock System of DOUT Circuit
For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the
DAC block. Set MCSL to 1 for 768fs and to 0 for 384fs.
– 92 –
L0
– 93 –
2
PCMDI
BCKI
1
(3) 48-bit Slot MSB first
PCMDI
BCKI
1
(2) 64-bit Slot LSB first
PCMDI
BCKI
(1) 32-bit Slot LSB first
LRCKI
(44.1k)
2
3
4
3
L1
5
5
7
8
L ch MSB (15)
4
6
L2
DOUT Block Input Timing Chart
9
10
6
7
8
L4
L ch LSB (0)
L3
9
10
L14
L5
L13
L6
L12
L11
17
L7
L10
L1
18
L8
L9
L2
L3
L8
L4
L9
L7
L5
L6
L6
L10
L5
L7
L8
L11
L4
L9
L13
L14
L3
L2
L1
L0
R0
R ch LSB (0)
L15
R ch MSB (15)
L10 L11 L12 L13 L14 L15
L12
CXD3021R
CXD3021R
§ 4-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move
are executed automatically.
The servo block operates according to the built-in program during the auto sequence execution (when
XBUSY = low), so that does not accept commands from the CPU, that is $0, 1 and 2 commands. ($3 to E
commands are accepted.)
In addition, when using the auto sequence, turn the A.SEQ of register 9 on.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to
external disturbances, etc. When the auto sequence command is sent from the CPU, this command
assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer
range. If the executed auto sequence command does not terminate within the set timer value, the auto
sequence is interrupted (like $40). See [1] "$4X commands" concerning the timer value and range. Also, the
MAX timer is invalidated by inputting $4X0.
Although this command is explained in the format of $4X in the following command descriptions, the timer
value and timer range are actually sent together from the CPU.
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-8. The auto focus starts
with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In
addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on
at the falling edge of FZC after FZC has been continuously high for a longer time than E.
(b) Track jump
1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they
are not involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in
accordance with Fig. 4-9. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 4-10. The principal difference from the 1-track jump is to kick the sled. In addition,
after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the
actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT
cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.
– 94 –
CXD3021R
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 4-11. The track jump count N is set with register 7. Although N can be set to 216
tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of
jumps when N is less than 16, and MIRR is used when N is 16 or more.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• Fine search
When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed
in accordance with Fig. 4-12. The differences from a 2N-track jump are that a higher precision is achieved
by controlling the traverse speed, and a longer distance jump is achieved by controlling the sled. The track
jump count is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse
speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5.
Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of
tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake
is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and
by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking
and sled servos are turned on.
Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should
be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For
example, set the target track count N – α for the traverse monitor counter which is set with register B, and
COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be set again.
• M-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in
accordance with Fig. 4-13. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting
the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move
is executed by moving only the sled, and is therefore suited for moving across several thousand to several
ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted
through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator
has stabilized.
– 95 –
CXD3021R
Auto focus
Focus search up
FOK = H
NO
YES
FZC = H
NO
YES
FZC = L
Check whether FZC is
continuously high for
the period of time E set
with register 5.
NO
YES
Focus servo ON
END
Fig. 4-8-(a). Auto Focus Flow Chart
$47 Latch
XLAT
FOK
FZC
BUSY
Command for
SSP
Blind E
$03
Fig. 4-8-(b). Auto Focus Timing Chart
– 96 –
$08
CXD3021R
1 Track
Track FWD kick
sled servo OFF
(REV kick for REV jump)
WAIT
(Blind A)
COUT =
NO
YES
Track REV
kick
(FWD kick for REV jump)
WAIT
(Brake B)
Track, sled
servo ON
END
Fig. 4-9-(a). 1-Track Jump Flow Chart
$48 (REV = $49) Latch
XLAT
COUT
BUSY
Brake B
Blind A
Command for
SSP
$2C ($28)
$28 ($2C)
Fig. 4-9-(b). 1-Track Jump Timing Chart
– 97 –
$25
CXD3021R
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
(Counts COUT × 5)
COUT = 5 ?
NO
YES
Track, REV
kick
C = Overflow ?
Checks whether the
COUT cycle is longer
than overflow C.
NO
YES
Track, sled
servo ON
END
Fig. 4-10-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) Latch
XLAT
COUT
BUSY
Blind A
COUT 5 count
Overflow C
Command for
SSP
$2E ($2B)
$2A ($2F)
Fig. 4-10-(b). 10-Track Jump Timing Chart
– 98 –
$25
CXD3021R
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT (MIRR) = N
NO
Counts COUT for the first 16 times
and MIRR for more times.
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 4-11-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) Latch
XLAT
COUT
(MIRR)
BUSY
Blind A
Command
for SSP
$2A ($2F)
COUT (MIRR)
N count
Overflow C
$2E ($2B)
$26 ($27)
Fig. 4-11-(b). 2N-Track Jump Timing Chart
– 99 –
Kick D
$25
CXD3021R
Fine Search
Track Servo ON
Sled FWD Kick
WAIT
(Kick D)
Track Sled
FWD Kick
WAIT
(Kick F)
Traverse
Speed Ctrl
(Overflow G)
COUT = N?
NO
YES
Track Servo ON
Sled REV Kick
WAIT
(Kick D)
Track Sled
Servo ON
END
Fig. 4-12-(a). Fine Search Flow Chart
$44 (REV = $45) latch
XLAT
COUT
BUSY
Kick D
$26 ($27)
Kick F
Traverse Speed Control (Overflow G)
&
COUT N count
$2A ($2F)
Kick D
$27 ($26)
$25
Fig. 4-12-(b). Fine Search Timing Chart
– 100 –
CXD3021R
M Track Move
Track Servo OFF
Sled FWD Kick
WAIT
(Blind A)
Counts COUT for M < 16.
Counts MIRR for M ≥ 16.
COUT (MIRR) = M
NO
YES
Track, Sled
Servo OFF
END
Fig. 4-13-(a). M-Track Move Flow Chart
$4E (REV = $4F) Latch
XLAT
COUT
(MIRR)
BUSY
Blind A
Command for
servo
COUT (MIRR)
M count
$20
$22 ($23)
Fig. 4-13-(b). M-Track Move Timing Chart
– 101 –
CXD3021R
§ 4-7. Digital CLV
Fig. 4-14 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the
sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D
MDS Error
MDP Error
Measure
Measure
Oversampling
Filter-1
2/1 MUX
CLV P/S
Gain
MDS
Gain
MDP
1/2
Mux
Gain
DCLV
CLV P/S
Oversampling
Filter-2
Noise Shape
KICK, BRAKE, STOP
Modulation
PWMI
DCLVMD, LPWR
Mode Select
MDS
CLVS U/D:
MDS error:
MDP error:
PWMI:
MDP
Up/down signal from CLVS servo
Frequency error for CLVP servo
Phase error for CLVP servo
Spindle drive signal from the microcomputer for CAV servo
Fig. 4-14. Block Diagram
– 102 –
CXD3021R
§ 4-8. Playback Speed
In the CXD3021R, the following playback modes can be selected through different combinations of XTLI,
XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency
division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode.
Mode
XTLI
XTSL
DSPB
VCOSEL1∗1
ASHS
Playback
speed
1
768Fs
1
0
0/1
0
1×
C1: double; C2: quadruple
2
768Fs
1
1
0/1
0
2×
C1: double; C2: double
3
768Fs
0
0
1
1
2×
C1: double; C2: quadruple
4
768Fs
0
1
1
1
4×
C1: double; C2: double
5
384Fs
0
0
0/1
0
1×
C1: double; C2: quadruple
6
384Fs
0
1
0/1
0
2×
C1: double; C2: double
7
384Fs
1
1
0/1
0
1×
C1: double; C2: double
Error correction
∗1 Actually, the optimal value should be used together with KSL3 and KSL2.
The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for
details.
– 103 –
CXD3021R
§ 4-9. DAC Block Playback Speed
The operating speed of the DAC block is determined by the crystal and the $AX command MCSL regardless of
the operating conditions of the CD-DSP block. This allows the DAC block and DSP block playback modes to
be set independently.
1-bit DAC block playback speed
Crystal MCSL
DAC block playback speed
768Fs
1
1×
768Fs
0
2×
384Fs
0
1×
Fs = 44.1kHz
§ 4-10. DAC Block Input Timing
The DAC input timing chart is shown below.
Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3021R. This
enables to send data to the DAC block via the external audio DSP, etc.
When the data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, LRCK, BCK and PCMD can be connected directly with LRCKI, BCKI and PCMDI. (See the
Application Circuit.)
Nomal-speed Playback
LRCKI
(44.1k)
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15 16
17
18 19
20
21 22
23 24
BCKI
(2.12M)
PCMDI
Invalid
L15 L14 L13 L12 L11 L10
– 104 –
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
CXD3021R
Description of DAC Block Functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is
performed independently for the left and right channels.
Mute flag output
The LMUTO and RMUTO pins go active when any one of the following conditions is met.
The polarity can be selected by the $9X command ZDPL.
• When zero data is detected
• When the $9X commands DAC SMUTL and DAC SMUTR are set (The flags change independently for the
left and right channels.)
The mute flag output at initializing is as shown below. (This is in the case the zero data is input from LRCKI,
BCKI, PCMDI and the time address $9X command ZDPL and address $AX command MCSL stay in the
initial values.)
XRST
LMUTO
RMUTO
Approx. 370ms when crystal = 16.9344MHz
Approx. 185ms when crystal = 33.8688MHz
Attenuation operation
Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3 (Y1
> Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command
X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches
Y2. And, when the command X3 is sent before the audio output rteaches Y2 (B or C in the figure), the audio
output approaches Y3 from the value (B or C in the figure) at that point.
0dB
400(H)
A
Y1
B
Y3
C
Y2
23.2 [ms]
– 105 –
–∞
000(H)
CXD3021R
DAC block mute operation
Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
• When attenuation data of 000 (Hex) is set
• When the $9X commands DAC SMUTL and DAC SMUTR are set to 1
Soft mute off
Soft mute on
Soft mute off
0dB
– ∞dB
23.2 [ms]
23.2 [ms]
Forced mute
Forced mute results when the $AX command FMUT is set to 1.
Forced mute fixes the PWM output. (Low for left channel, high for right channel)
Zero detection mute
Setting $9X command ZMUT to 1 enables forced mute when zero data is detected for both the left and right
channels. (See "Zero data detection".)
LRCK Synchronization
Synchronization is performed at the first rising edge of the LRCK input when reset.
After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must
be performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
• When the XTSL pin switches between high and low
• When the $9X command DSPB setting changes
• When the $9X command MCSL setting changes
• When operation switches between CLV mode and CAV mode
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in these cases as well.
For resynchronization, set the $9X command XWOC to 0 or the external pin XWO to low, wait for one
LRCK cycle or more, and then set XWOC to 1 and XWO to high.
∗ When setting XWOC to 0 or the external pin XWO to low, be sure to set the $9X command SYCOF to 0
beforehand.
– 106 –
CXD3021R
SYCOF
When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback
can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1.
Normally, the memory proof, etc., is used for playback in CAV-W mode.
In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is
frequently lost.
Setting SYCOF of address 9 to 1 ignores the LRCKI's asynchronization, facilitating playback. However, the
playback is not perfect because pre-value hold or data skip occurs due to the wow and flutter in the LRCKI
input.
∗ Set SYCOF to 0 other than when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and
BCKI, respectively, and performing playback in CAV-W mode.
Digital Bass Boost
Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
MID and MAX.
The bass boost is set using BSBST and BBSL of address A.
See Graph 4-15 for the digital bass boost frequency response.
10.00
8.00
Normal
6.00
DBB MID
4.00
DBB MAX
2.00
[dB]
0.00
–2.00
–4.00
–6.00
–8.00
–10.00
–12.00
–14.00
10
30
100
300
1k
3k
Digital bass boost frequency response [Hz]
Graph 4-15.
– 107 –
10k
30k
CXD3021R
§ 4-11. Asymmetry Correction
Fig. 4-16 shows the block diagram and circuit example.
CXD3021R
ASYE
ASYO
R1
RFAC
+
–
R1
R2
R1
ASYI
+
–
R1
BIAS
R1
2
=
R2
5
Fig. 4-16. Asymmetry Correction Application Circuit
– 108 –
CXD3021R
§ 4-12. Clock System
The DAC, digital signal processor and digital servo blocks can be switched to each playback mode according
to how the crystal and clock circuit are connected. Each circuit is as shown in the diagram below. During
normal use, the servo block clock is internally connected and the FSTIO pin is the monitor output pin. The
command ($8 FSTIN) is used to input the clock externally. In this time, the FSTIO pin serves as the input pin.
XTLI
384fs or
768fs
XTLO
To DAC block
OSC
MCKO
To exterior
1/2
XTSL
To CD signal processor block
FSTIO
2/3
Selector
FSTIN = 0: Output pin
(Preset)
FSTIN = 1: Input pin
FSTIN (Command $8X.
"0" for preset;
internally connected)
To digital servo block
1/2
1/4
XT1D
XT2D
XT4D
(Commands $3E, $3F)
– 109 –
CXD3021R
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System (VDD: Supply voltage)
Focus servo
Sampling rate:
Input range:
Output format:
Other:
Tracking servo
Sampling rate:
Input range:
Output format:
Other:
Sled servo
Sampling rate:
Input range:
Output format:
Other:
88.2kHz (when MCK = 128Fs)
1/4VDD to 3/4VDD
8-bit DAC
Offset cancel
Focus bias adjustment
Focus search
Gain-down
Defect countermeasure
Auto gain control
88.2kHz (when MCK = 128Fs)
1/4VDD to 3/4VDD
8-bit DAC
Offset cancel
E:F balance adjustment
Track jump
Gain-up
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
345Hz (when MCK = 128Fs)
1/4VDD to 3/4VDD
8-bit DAC
Sled move
FOK, MIRR, DFCT signal generation
RF signal sampling rate: 1.4MHz (when MCK = 128Fs)
Input range:
1/4VDD to 3/4VDD
Other:
RF zero level automatic measurement
– 110 –
CXD3021R
§ 5-2. Digital Servo Block Master Clock (MCK)
The FSTIO pin is the clock input/output pin for the servo block. At preset, the clock with 2/3 frequency of the
crystal is internally supplied to the servo block and the FSTIO pin serves as the monitor output pin for it. To
make this pin act as the input pin, set the command $8X command FSTIN to 1.
The master clock (MCK) is generated by dividing the frequency of the FSTIO pin. The frequency division ratio
is 1, 1/2 or 1/4.
Table 5-1 below assumes the preset status (where the clock with 2/3 frequency of the crystal is internally
supplied to the servo).
XT4D and XT2D are for the $3F command and XT1D is for the $3E command. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
XTLI
FSTO
XTSL
XT4D
XT2D
XT1D
Frequency division ratio
MCK
1
384Fs
256Fs
∗
∗
∗
1
1
256Fs
2
384Fs
256Fs
∗
∗
1
0
1/2
128Fs
3
384Fs
256Fs
0
0
0
0
1/2
128Fs
4
768Fs
512Fs
∗
∗
∗
1
1
512Fs
5
768Fs
512Fs
∗
∗
1
0
1/2
256Fs
6
768Fs
512Fs
∗
1
0
0
1/4
128Fs
7
768Fs
512Fs
1
0
0
0
1/4
128Fs
Fs = 44.1kHz, ∗: Don't care
Table 5-1.
– 111 –
CXD3021R
§ 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)
The CXD3021R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the
measurement results to control the servo effectively. This AVRG measurement and compensation is
necessary to initialize the CXD3021R, and is able to cancel the DC offset.
AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values
of 256 samples, and then loads these values into each AVRG register.
The AVRG measurement commands are VCLM, FLM, RFLM and TLM of $38.
Measurement is on when the respective command is set to 1.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received.
The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.)
Monitoring requires that the upper 8 bits of the command register are 38 (H).
XLAT
2.9 to 5.8ms
SENS
(= XAVEBSY)
AVRG measurement completed
Max. 1µs
Timing Chart 5-2.
<Measurement>
VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to
compensate the FE, TE and SE signals.
FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals.
TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals.
RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.
<Compensation>
RFLC:
(RF signal – RF AVRG) is input to the RF In register.
"00" is input when the RF signal is lower than RF AVRG.
TLC0:
(TE signal – VC AVRG) is input to the TRK In register.
TLC1:
(TE signal – TE AVRG) is input to the TRK In register.
VCLC:
(FE signal – VC AVRG) is input to the FCS In register.
FLC1:
(FE signal – FE AVRG) is input to the FCS In register.
FLC0:
(FE signal – FE AVRG) is input to the FZC register.
Two methods of canceling the DC offset are assumed for the CXD3021R. These methods are shown in Figs.
5-3a and 5-3b.
An example of AVRG measurement and compensation commands is shown below.
$38 08 00 (RF AVRG measurement)
$38 20 00 (FE AVRG measurement)
$38 00 10 (TE AVRG measurement)
$38 14 0A (Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.)
See the description of $38 for these commands.
– 112 –
CXD3021R
§ 5-4. E:F Balance Adjustment Function (See Fig. 5-3.)
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates the values obtained from the TE and SE input pins with the
TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.)
§ 5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 5-3.)
When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9
to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the $8 commands SOCT1, SOCT0. (See "DSP Block
Timing Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to
FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this
time, SENS goes high and the counter stop can be monitored.
A
B
C
FBIAS setting value (FB9 to FB1)
LIMIT value (FBL9 to FBL1)
Here, assume the FBIAS setting value FB9 to FB1
and the FBIAS LIMIT value FBL9 to FBL1 are set
in status A. For example, if command registers
FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are
set from this status, down count starts from status
A and approaches the set LIMIT value. When the
LIMIT value is reached and the FCSBIAS value
matches FBL9 to FBL1, the counter stops and the
SENS pin goes high. Note that the up/down
counter counts at each sampling cycle of the focus
servo filter. The number of steps by which the
count value changes can be selected from 1, 2, 4
or 8 steps by FBV1 and FBV0. When converted to
FE input, 1 step corresponds to 1/512 × VDD/2.
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
SENS pin
– 113 –
CXD3021R
RFDC from A/D
to RF In register
–
RF AVRG
register
RFLC
SE from A/D
to SLD In register
–
–
TLC1 • TLD1
TLC2 • TLD2
to TRK In register
TE from A/D
–
–
TE AVRG
register
TRVSC
register
TLC1
TLC2
FE from A/D
to FCS In register
–
FE AVRG
register
FLC1
FBIAS
register
+
FBON
FLC0
to FZC register
–
Fig. 5-3a.
RFDC from A/D
to RF In register
–
RF AVRG
register
RFLC
SE from A/D
to SLD In register
–
–
TLC2 • TLD2
TLC0 • TLD0
to TRK In register
TE from A/D
–
–
TLC0
TRVSC
register
VC AVRG
register
TLC2
VCLC
FE from A/D
to FCS In register
–
+
FE AVRG
register
FBIAS
register
FLC0
–
Fig. 5-3b.
– 114 –
FBON
to FZC register
CXD3021R
§ 5-6. AGCNTL (Automatic Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop
gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also
obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed by monitoring the
SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
Max. 11.4µs
SENS
(= AGOK)
AGCNTL completion
Timing Chart 5-4
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related settings
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS;
Self-stop on/off
AGJ;
Convergence completion judgment time
AGGF;
Internally generated sine wave amplitude (AGF)
AGGT;
Internally generated sine wave amplitude (AGT)
AGV1;
AGCNTL sensitivity 1 (during rough adjustment)
AGV2;
AGCNTL sensitivity 2 (during fine adjustment)
AGHS;
Rough adjustment on/off
AGHT;
Fine adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0dB at
1kHz. However, since convergence values vary according to the characteristics of each constituent
element of the servo loop, FG and TG values should be set as necessary.
– 115 –
CXD3021R
AGCNTL and default operation have two stages.
In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach
the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD3021R confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5.
Initial value
Slope
AGV1
AGCNTL coefficient value
Slope
AGV2
Convergence value
AGHT
AGJ
AGCNTL
completion
AGCNTL
start
SENS
Fig. 5-5.
Note) Fig. 5-5 shows the case where the AGCNTL coefficient converges from the initial value to a smaller
value.
– 116 –
CXD3021R
§ 5-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)
Register
name
Command
FOCUS
CONTROL
0
D23 to D20
0 0 0 0
D19 to D16
1 0 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN NORMAL)
1 1 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN DOWN)
0 ∗ 0 ∗
FOCUS SERVO OFF, 0V OUT
0 ∗ 1 ∗
FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
0 ∗ 1 0
FOCUS SEARCH VOLTAGE DOWN
0 ∗ 1 1
FOCUS SEARCH VOLTAGE UP
∗: Don't care
Table 5-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation.
Fig. 5-8 shows the signals for sending $08 (FCS on) after that.
$00 $02 $03
$00 $02 $03
0
FCSDRV
FCSDRV
RF
RF
FOK
FOK
FZC comparator level
FE
FE
0
FZC
0
FZC
Fig. 5-7.
Fig. 5-8.
– 117 –
$08
CXD3021R
§ 5-8. TRK (Tracking) and SLD (Sled) Servo Control
The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)
When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.
Register
name
2
Command
TRACKING
MODE
D23 to D20
0 0 1 0
D19 to D16
0 0 ∗ ∗
TRACKING SERVO OFF
0 1 ∗ ∗
TRACKING SERVO ON
1 0 ∗ ∗
FORWARD TRACK JUMP
1 1 ∗ ∗
REVERSE TRACK JUMP
∗ ∗ 0 0
SLED SERVO OFF
∗ ∗ 0 1
SLED SERVO ON
∗ ∗ 1 0
FORWARD SLED MOVE
∗ ∗ 1 1
REVERSE SLED MOVE
Table 5-9.
∗: Don't care
TRK Servo
The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.
The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the
anti-shock circuit (described hereafter) enabled.
The CXD3021R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting
D16 of $1. (See Table 5-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1×, 2×, 3×, or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with
$3. (See Table 5-10.)
SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off.
These operations are disabled by setting D6 (LKSW) of $38 to 1.
Register
name
3
Command
SELECT
D23 to D20
0 0 1 1
D19 to D16
0 0 0 0
SLED KICK LEVEL (basic value × ±1)
0 0 0 1
SLED KICK LEVEL (basic value × ±2)
0 0 1 0
SLED KICK LEVEL (basic value × ±3)
0 0 1 1
SLED KICK LEVEL (basic value × ±4)
Table 5-10.
– 118 –
CXD3021R
§ 5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and D6, and D5 and D4,
respectively, of $3C.
RF
Peak Hold
Bottom Hold
Peak Hold
–Bottom Hold
MIRR Comp
(Mirror comparator level)
H
MIRR
L
Fig. 5-11.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
RF
Peak Hold1
Peak Hold2
Peak Hold2
–Peak Hold1
SDF
(Defect comparator level)
H
DFCT
L
Fig. 5-12.
– 119 –
CXD3021R
§ 5-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not
become easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by detecting scratches and defects with the DFCT signal
generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal
before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of
$38 to 1.
Hold Filter
Error signal
Input register
Hold register EN
DFCT
Servo Filter
Fig. 5-13.
§ 5-11. Anti-Shock Circuit
When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the
servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 5-14.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 5-17.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
mode by inputting high level to the ATSK pin.
When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin.
ATSK
TE
Anti Shock
Filter
SENS
Comparator
TRK Gain Up
Filter
TRK DAC
TRK Gain Normal
Filter
Fig. 5-14.
– 120 –
CXD3021R
§ 5-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the
180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses
the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)
In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1, 2 of $34B)
Outer track → Inner track
Inner track → Outer track
FWD REV Servo ON
JMP JMP
REV FWD Servo ON
JMP JMP
TRK
DRV
TRK
DRV
RF
Trace
RF
Trace
MIRR
MIRR
TE
0
TE
TZC
Edge
TZC
Edge
TRKCNCL
TRKCNCL
TRK DRV
(SFBK OFF)
0
TRK DRV
(SFBK ON)
0
0
TRK DRV
(SFBK OFF)
0
TRK DRV
(SFBK ON)
0
SENS
TZC out
SENS
TZC out
Fig. 5-15.
Register
name
1
Command
TRACKING
CONTROL
D23 to D20
0 0 0 1
Fig. 5-16.
D19 to D16
1 0 ∗ ∗
ANTI SHOCK ON
0 ∗ ∗ ∗
ANTI SHOCK OFF
∗ 1 ∗ ∗
BRAKE ON
∗ 0 ∗ ∗
BRAKE OFF
∗ ∗ 0 ∗
TRACKING GAIN NORMAL
∗ ∗ 1 ∗
TRACKING GAIN UP
∗ ∗ ∗ 1
TRACKING GAIN UP FILTER SELECT 1
∗ ∗ ∗ 0
TRACKING GAIN UP FILTER SELECT 2
∗: Don't care
Table 5-17.
– 121 –
CXD3021R
§ 5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among
three different phases according to the COUT signal application.
• HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced
by a cut-off 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation.
This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
• DTZC: For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and D14 of $3C.
When D15 = 1:
STZC
When D15 = 0 and D14 = 0: HPTZC
When D15 = 0 and D14 = 1: DTZC
When DTZC is selected, the delay can be selected from two values with D14 of $36.
§ 5-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by the serial command $39. (See Fig. 5-18, Table 5-19 and "Description of
SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
XLAT
tDLS
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
tSPW
…
SCLK
1/fSCLK
Serial Readout Data
(SENS pin)
…
MSB
LSB
Fig. 5-18.
Item
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
Min.
Typ.
Max.
Unit
16
MHz
31.3
ns
15
µs
Table 5-19.
During readout, the upper 8 bits of the command register must be 39 (H).
– 122 –
CXD3021R
§ 5-15. Writing to Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as the data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the
next rewrite command.
– 123 –
CXD3021R
§ 5-16. DAC Output
FCS, TRK and SLD DAC format outputs are described below.
See the "Servo Drive Analog Characteristics" of Electrical Characteristics for the output range.
In particular, FSC and TRK use a double oversampling noise shaper.
Timing Chart 5-22 and Fig. 5-23 show examples of output waveforms and drive circuits.
Output value +B
Output value –B
Output value 0
64MCK
64MCK
64MCK
SLD
VDD
0.9VDD
SAO
0.5VDD
0.1VDD
0
FCS/TRK
B
VDD
256
–B
VDD
128
32MCK
32MCK
32MCK
32MCK
–B
VDD
256
–B
VDD
256
VDD
0.9VDD
0.5VDD
FAO/TAO
B
VDD
256
B
VDD
256
0.1VDD
0
Timing Chart 5-22.
VCC
R
R
DRV
VDD/2
AO
R
R
Fig. 5-23. Drive Circuit
– 124 –
32MCK
32MCK
CXD3021R
§ 5-17. Servo Status Changes Produced by LOCK Signal
When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
– 125 –
CXD3021R
§ 5-18. Description of Commands and Data Sets
$34
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
When D15 = 0.
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
$348 (preset: $348 000)
D15
D14
D13
D12
1
0
0
0
D11
PGFS1 PGFS0 PFOK1 PFOK0
MRT2 MRT1
These commands set the GFS pin hold time. The hold time is inversely proportional to the playback speed.
PGFS1
PGFS0
Processing
0
0
High when the frame sync is of the correct timing,
low when not the correct timing.
0
1
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 2ms or longer.
1
0
High when the frame sync is of the correct timing,
low when continuously not the correct timing for 4ms or longer.
1
1
High when the frame sync is the correct timing,
low when continuously not the correct timing for 8ms or longer.
These commands set the FOK hold time. See $3B for the FOK slice level.
These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting.
PFOK1
PFOK0
Processing
0
0
High when the RFDC value is higher than the FOK slice level,
low when lower than the FOK slice level.
0
1
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 4.35ms or more.
1
0
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 10.16ms or more.
1
1
High when the RFDC value is higher than the FOK slice level,
low when continuously lower than the FOK slice level for 21.77ms or more.
These commands limit the time while Mirr = high. These are the values when MCK = 128Fs, and the time limit
is inversely proportional to the MCK setting.
MRT2
MRT1
Time limit
0
0
No time limit
0
1
1.1ms
1
0
2.2ms
1
1
4.0ms
– 126 –
CXD3021R
$34A (preset: $34A 150)
D15
D14
D13
D12
1
0
1
0
D11
D10
D9
D8
D7
A/DSEL = 1
D4
D3
D2
D1
D0
0
0
0
Processing
Channel status data. Bit 1 is output as the audio data.
Channel status data. Bit 1 is output as the data other than the audio data.
Command bit
∗
D5
A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT
SEL
EN
D
b8
EN DMUT WOD EN
EN2
Command bit
∗ A/DSEL = 0
D6
Processing
COPY EN = 0
Channel status data. Bit 2 is output as the digital copy prohibited.
COPY EN = 1
Channel status data. Bit 2 is output as the digital copy enabled.
Command bit
∗ EMPH D = 0
EMPH D = 1
Processing
Channel status data. Bit 3 is output without pre-emphasis.
Channel status data. Bit 3 is output with pre-emphasis.
Processing
Command bit
CAT b8 = 0
∗ CAT b8 = 1
Channel status data. Bit 8 is output as 0.
Channel status data. Bit 8 is output as 1.
∗ : Preset
Command bit
∗ DOUT EN = 0
DOUT EN = 1
Processing
DOUT signal, which is generated from PCM data read out from the disc, is output.
DOUT signal, which is generated from the DA interface input, is output.
Command bit
DOUT DMUT = 0
∗ DOUT DMUT = 1
Command bit
∗ DOUT WOD = 0
DOUT WOD = 1
Processing
Digital Out output is normally output.
All the audio data portions are output in 0, with Digital Out output as it is.
Processing
DOUT sync window is not open.
DOUT sync window is open.
– 127 –
CXD3021R
$34A commands contin.
Command bit
Processing
The operation is invalidated, where the input LRCK is automatically synchronized
with the internal processing to match the phase.
WIN EN = 0
∗ WIN EN = 1
The operation is validated, where the input LRCK is automatically synchronized with
the internal processing to match the phase.
Processing
Command bit
∗ DOUT EN2 = 0
DOUT EN2 = 1
Digital Out is not generated from the DA interface input.
Digital Out is generated from the DA interface input.
Note) In order to generate Digital Out from the DA interface input, set DOUT EN to 1 and DOUT EN2 to 1.
∗ : Preset
DOUT
EN
DOUT
DMUT
MD2 pin
Other mute
condition
DOUT
Mute
D. out
Mute F
DOUT output
0
—
0
—
—
—
OFF
0
—
1
0
0
0
0
—
1
0
0
1
0dB
The output from the PCM
data readout from a disc
0
—
1
0
1
0
0
—
1
0
1
1
0
—
1
1
0
0
0
—
1
1
0
1
0
—
1
1
1
0
0
—
1
1
1
1
1
0
—
—
—
—
0dB
The output from the
DA interface input
1
1
—
—
—
—
– ∞dB
The output from the
DA interface input
– ∞dB
The output from the PCM
data readout from a disc
—: don't care
∗ See the "Mute conditions" (1), (2) and (4) to (6) of $AX commands for the other mute conditions.
∗ See $8X commands for DOUT Mute and D. out Mute F.
– 128 –
CXD3021R
$34B (preset: $34B 000)
D15
D14
D13
D12
1
0
1
1
D11
D10
SFBK1 SFBK2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
The low frequency can be boosted for brake operation.
See § 5-12 for brake operation.
SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0.
This is valid only when TLB1ON = 1. The preset is 0.
SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0.
This is valid only when TLB2ON = 1. The preset is 0.
– 129 –
CXD3021R
$34C (preset: $34C 000)
D15
D14
D13
D12
D11
D10
1
1
0
0
THB
ON
FHB
ON
D9
D8
D7
TLB1 FLB1 TLB2
ON
ON
ON
D6
0
D5
D4
D3
D2
D1
D0
HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0
These commands turn on the boost function. (See "§ 5-20. Filter Composition".)
There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off
independently.
THBON: When 1, the high frequency is boosted for the TRK filter. Preset is 0.
FHBON: When 1, the high frequency is boosted for the FCS filter. Preset is 0.
TLB1ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0.
FLB1ON: When 1, the low frequency is boosted for the FCS filter. Preset is 0.
TLB2ON: When 1, the low frequency is boosted for the TRK filter. Preset is 0.
The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted.
For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump.
Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK jump operation.
The following commands set the boosters. (See "§ 5-20. Filter Composition".)
HBST1, HBST0: TRK and FCS HighBooster setting.
HighBooster has the configuration shown in Fig. 5-24a, and can select three different
combinations of coefficients BK1, BK2 and BK3. (See Table 5-25a.)
An example of characteristics is shown in Fig. 5-26a.
These characteristics are the same for both the TRK and FCS filters.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
LB1S1, LB1S0: TRK and FCS LowBooster-1 setting.
LowBooster-1 has the configuration shown in Fig. 5-24b, and can select three different
combinations of coefficients BK4, BK5 and BK6. (See Table 5-25b.)
An example of characteristics is shown in Fig. 5-26b.
These characteristics are the same for both the TRK and FCS filters.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
LB2S1, LB2S0: TRK LowBooster-2 setting.
LowBooster-2 has the configuration shown in Fig. 5-24c, and can select three different
combinations of coefficients BK7, BK8 and BK9. (See Table 5-25c.)
An example of characteristics is shown in Fig. 5-26c.
This booster is used exclusively for the TRK filter.
The sampling frequency is 88.2kHz (when MCK = 128Fs).
Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK
jump operation.
Note) Fs = 44.1kHz
– 130 –
CXD3021R
BK3
Z –1
HBST1
HBST0
0
1
1
—
0
1
Z –1
BK1
BK2
Fig. 5-24a.
Z –1
LB1S1
LB1S0
0
1
1
—
0
1
Z –1
BK5
BK9
LB2S1
LB2S0
0
1
1
—
0
1
Z –1
BK7
BK2
BK3
–120/128
–124/128
–126/128
96/128
112/128
120/128
2
2
2
LowBooster-1 setting
BK4
BK5
BK6
–255/256
–511/512
–1023/1024
1023/1024
2047/2048
4095/4096
1/4
1/4
1/4
Table 5-25b.
Fig. 5-24b.
Z –1
BK1
Table 5-25a.
BK6
BK4
HighBooster setting
BK8
Fig. 5-24c.
LowBooster-2 setting
BK7
BK8
BK9
–255/256
–511/512
–1023/1024
1023/1024
2047/2048
4095/4096
1/4
1/4
1/4
Table 5-25c.
– 131 –
CXD3021R
15
12
9
3
2
1
6
Gain [dB]
3
0
–3
–6
–9
–12
–15
1
10
100
1k
10k
1k
10k
Frequency [Hz]
+90
+72
3
2
1
Phase [degree]
+36
0
–36
–72
–90
1
10
100
Frequency [Hz]
Fig. 5-26a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs)
1
HBST1 = 0
2
HBST1 = 1, HBST0 = 0
– 132 –
3
HBST1 = 1, HBST0 = 1
CXD3021R
15
12
9
6
Gain [dB]
3
2
3
1
0
–3
–6
–9
–12
–15
1
10
100
1k
10k
1k
10k
Frequency [Hz]
+90
+72
Phase [degree]
+36
3
2
1
0
–36
–72
–90
1
10
100
Frequency [Hz]
Fig. 5-26b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs)
1
LB1S1 = 0
2
LB1S1 = 1, LB1S0 = 0
– 133 –
3
LB1S1 = 1, LB1S0 = 1
CXD3021R
15
12
9
6
Gain [dB]
3
2
3
1
0
–3
–6
–9
–12
–15
1
10
100
1k
10k
1k
10k
Frequency [Hz]
+90
+72
Phase [degree]
+36
3
2
1
0
–36
–72
–90
1
10
100
Frequency [Hz]
Fig. 5-26c. Servo LowBooster-2 characteristics [FCS, TRK] (MCK = 128Fs)
1
LB2S1 = 0
2
LB2S1 = 1, LB2S0 = 0
– 134 –
3
LB2S1 = 1, LB2S0 = 1
CXD3021R
$34D (preset: $34D 000)
D15
D14
D13
D12
1
1
0
1
D11
D10
D9
FAON TAON SAON
D8
0
D7
D6
D5
FAOZ TAOZ SAOZ
D4
D3
D2
D1
D0
0
0
0
0
0
The servo drive is output. DAC format.
FAON: When 0, the FCS servo drive is muted. (default)
When 1, the FCS servo drive is output.
TAON: When 0, the TRK servo drive is muted. (default)
When 1, the TRK servo drive is output.
SAON: When 0, the SLD servo drive is muted. (default)
When 1, the SLD servo drive is output.
These commands select the drive DAC output when the servo is off. Center potential or high impedance can
be selected.
FAOZ:
When 0, the FCS drive DAC output is the center potential when the FCS servo is off. (default)
When 1, the FCS drive DAC output is high impedance when the FCS servo is off.
TAOZ: When 0, the TRK drive DAC output is the center potential when the TRK servo is off. (default)
When 1, the TRK drive DAC output is high impedance when the TRK servo is off.
Set SFJP ($36) to 1 or TAOZ to 0 in order to boost the low frequency for the TRK Jump operation by
the $34C command TLB2ON.
SAOZ: When 0, the SLD drive DAC output is the center potential when the SLD servo is off. (default)
When 1, the SLD drive DAC output is high impedance when the SLD servo is off.
– 135 –
CXD3021R
$34F
D15
D14
D13
D12
D11
D10
1
1
1
1
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
D0
—
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to FB1 matches with FBL9 to FBL1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
—
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 1
FBIAS register write
two's complement data, FB9 = MSB.
FB9 to FB1: Data;
For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/4
and FB9 to FB1 = 100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data;
two's complement data, TV9 = MSB.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/4
and TV9 to TV0 = 1100000000 to –256/256 × VDD/4 respectively. (VDD: supply voltage)
Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each
bits TV8 to TV0 during external write are read out.
• When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
– 136 –
CXD3021R
$35 (preset: $35 58 2D)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FT1
FT0
FS5
FS4
FS3
FS2
FS1
FS0
FTZ
FG6
FG5
FG4
FG3
FG2
FG1
FG0
FT1, FT0, FTZ: Focus search-up speed
Default value: 010 (0.673 × VDD V/s)
∗
FT1
FT0
FTZ
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Focus search speed [V/s]
1.35 × VDD
0.673 × VDD
0.449 × VDD
0.336 × VDD
1.79 × VDD
1.08 × VDD
0.897 × VDD
0.769 × VDD
∗: preset, VDD: supply voltage
FS5 to Fs0:
Focus search limit voltage
Default value: 011000 ((1 ± 24/64) × VDD/2, VDD: supply voltage)
FG6 to FG0:
AGF convergence gain setting value
Default value: 0101101
$36 (preset: $36 0E 2E)
D15
D14
D13
D12
D11
D10
D9
D8
TDZC DTZC TJ5
TJ4
TJ3
TJ2
TJ1
TJ0 SFJP TG6
TDZC:
DTZC:
TJ5 to TJ0:
SFJP:
TG6 to TG0:
D7
D6
D5
D4
D3
D2
D1
D0
TG5
TG4
TG3
TG2
TG1
TG0
Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.
When TDZC = 0, the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.
When TDZC = 1, the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross,
whichever has the fastest phase, is used. (See § 5-12.)
DTZC delay (8.5/4.25µs, when MCK = 128Fs)
Default value: 0 (4.25µs)
Track jump voltage
Default value: 001110 ((1 ± 14/64) × VDD/2, VDD: supply voltage)
Surf jump mode on/off
The tracking drive output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0),
by setting SFJP to 1.
Set SFJP to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump
operation by the $34C command TLB2ON.
AGT convergence gain setting value
Default value: 0101110
– 137 –
CXD3021R
$37 (preset: $37 50 BA)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL:
FZC (Focus Zero Cross) slice level
Default value: 01 (1/8 × VDD/2, VDD: supply voltage); FE input conversion
∗
FZSH
FZSL
0
0
1
1
0
1
0
1
Slice level
1/4 × VDD/2
1/8 × VDD/2
1/16 × VDD/2
1/32 × VDD/2
∗: preset
SM5 to SM0:
AGS:
AGJ:
AGGF:
AGGT:
Sled move voltage
Default value: 010000 ((1 ± 16/64) × VDD/2, VDD: supply voltage)
AGCNTL self-stop on/off
Default value: 1 (on)
AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,
when MCK = 128Fs)
Default value: 0 (63ms)
Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
FE/TE input conversion
AGGF
0 (small) 1/32 × VDD/2
1 (large)∗ 1/16 × VDD/2
AGGT
0 (small) 1/16 × VDD/2
1 (large)∗ 1/8 × VDD/2
∗: preset
AGV1:
AGV2:
AGHS:
AGHT:
AGCNTL convergence sensitivity during high sensitivity adjustment; high/low
Default value: 1 (high)
AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)
Default value: 0 (256ms)
– 138 –
CXD3021R
$38 (preset: $38 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
∗VCLM: VC level measurement (on/off)
VCLC: VC level compensation for FCS In register (on/off)
∗FLM:
Focus zero level measurement (on/off)
FLC0: Focus zero level compensation for FZC register (on/off)
∗RFLM: RF zero level measurement (on/off)
RFLC: RF zero level compensation (on/off)
AGF:
Focus auto gain adjustment (on/off)
AGT:
Tracking auto gain adjustment (on/off)
DFSW: Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
LKSW: Lock switch (on/off)
Setting this switch to 1 (on) disables the sled free-running prevention circuit.
TBLM: Traverse center measurement (on/off)
∗TCLM: Tracking zero level measurement (on/off)
FLC1: Focus zero level compensation for FCS In register (on/off)
TLC2: Traverse center compensation (on/off)
TLC1: Tracking zero level compensation (on/off)
TLC0: VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with ∗ are accepted every 2.9ms. (when MCK = 128Fs)
All commands are on when 1.
– 139 –
CXD3021R
$39
D15
D14
D13
D12
D11
D10
D9
D8
DAC SD6
SD5
SD4
SD3
SD2
SD1
SD0
DAC:
SD6 to SD0:
SD6
1
0
Serial data readout DAC mode (on/off)
Serial readout data select
SD5
Readout data
Coefficient RAM data for address = SD5 to SD0
1
Data RAM data for address = SD4 to SD0
SD4
1
0
0
0
Readout data length
8 bits
16 bits
SD3 to SD0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
RFDC envelope
(peak) – (bottom)
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits
$399F
$399E
$399D
$399C
$3993
$3992
$3991
1
1
0
0
0
0
0
1
0
1
0
0
0
0
∗
∗
∗
1
1
0
0
∗
∗
∗
1
0
1
0
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
$398C
$3988
$3984
$3983
$3982
$3981
$3980
∗: Don't care
Note) Coefficients K40 to K4F cannot be read out.
See the description for SRO1 and SRO0 of $3F concerning readout methods for the above data.
– 140 –
CXD3021R
$3A (preset: $3A 00 00)
D15
0
D14
D13
D12
D11
D10
FBON FBSS FBUP FBV1 FBV0
FBON:
FBSS:
FBUP:
FBV1, FBV0:
∗
D9
0
D8
D7
D6
D5
TJD0 FPS1 FPS0 TPS1 TPS0
FPS1, FPS0:
TPS1, TPS0:
∗
D3
0
D2
D1
D0
SJHD INBK MTI0
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by setting
FBON = 1 (on).
FBIAS (focus bias) register/counter switching
FBSS = 0: register, FBSS = 1: counter
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1.
FBUP = 0: down counter
FBUP = 1: up counter
FBIAS (focus bias) counter voltage switching
The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.
FBV1
FBV0
Number of steps per cycle
0
0
1
0
1
2
1
0
4
1
1
8
∗: preset
TJD0:
D4
The counter changes once for each
sampling cycle of the focus servo
filter. When MCK is 128Fs, the
sampling frequency is 88.2kHz.
When converted to FE input, 1 step
is approximately 1/29 × VDD/2,
VDD = supply voltage.
This sets the tracking servo filter to 0 when switched from track jump to servo on even if SFJP
= 1 (during surf jump operation).
Gain setting for the whole focus filter.
Gain setting for the whole tracking filter.
These are effective for increasing the overall gain in order to widen the servo band.
(See "§ 5-20. Filter Composition".)
FPS1
FPS0
Relative gain
TPS1
TPS0
Relative gain
0
0
0dB
0
0
0dB
0
1
+6dB
0
1
+6dB
1
0
+12dB
1
0
+12dB
1
1
+18dB
1
1
+18dB
∗
∗: preset
SJHD:
INBK:
MTI0:
This holds the tracking filter output at the value when surf jump starts during surf jump.
The masking method for the brake circuit is selected. When INBK = 1, the tracking filter input
is masked instead of the drive output.
The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1.
– 141 –
CXD3021R
$3B (preset: $3B E0 50)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
D2
D1
D0
0
0
0
SFOX, SFO2, SFO1: FOK slice level
Default value: 011 (28/256 × VDD/2, VDD: supply voltage)
RFDC input conversion
∗
SFOX
SFO2
SFO1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Slice level
16/256 × VDD/2
20/256 × VDD/2
24/256 × VDD/2
28/256 × VDD/2
32/256 × VDD/2
40/256 × VDD/2
48/256 × VDD/2
56/256 × VDD/2
∗: preset
SDF2, SDF1:
DFCT slice level
Default value: 10 (0.0313 × VDD V)
RFDC input conversion
∗
SDF2
SDF1
0
0
1
1
0
1
0
1
Slice level
0.0156 × VDD
0.0234 × VDD
0.0313 × VDD
0.0391 × VDD
∗: preset, VDD: supply voltage
MAX2, MAX1:
DFCT maximum time
Default value: 00 (no timer limit)
∗
MAX2
MAX1
0
0
1
1
0
1
0
1
DFCT maximum time
No timer limit
2.00ms
2.36
2.72
∗: preset
BTF:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when 1.
– 142 –
CXD3021R
D2V2, D2V1:
Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.086 × VDD V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
D2V2
∗
0
0
1
1
D2V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
0.0431 × VDD
0.0861 × VDD
0.172 × VDD
0.344 × VDD
22.05
44.1
88.2
176.4
∗: preset, VDD: supply voltage
D1V2, D1V1:
Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.688 × VDD V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate
the operating frequency of the internal counter.
D1V2
∗
0
0
1
1
D1V1
0
1
0
1
Count-down speed
[V/ms]
[kHz]
0.344 × VDD
0.688 × VDD
1.38 × VDD
2.75 × VDD
176.4
352.8
705.6
1411.2
∗: preset, VDD: supply voltage
RINT:
This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK.
– 143 –
CXD3021R
$3C (preset: $3C 00 80)
D15
D14
D13
D12
D11
D10
D9
COSS COTS CETZ CETF COT2 COT1 MOT2
D8
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
BTS1 BTS0 MRC1 MRC0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
Preset = HPTZC.
COSS
COTS
1
0
0
—
0
1
∗
TZC
STZC
HPTZC
DTZC
∗: preset, —: don't care
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See § 5-13.
CETZ:
The input from the TE pin normally enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When 0, the TZC signal is generated by using the signal input to the TE pin.
When 1, the TZC signal is generated by using the signal input to the CE pin.
When 0, the signal input to the TE pin is input to the TRK servo filter.
When 1, the signal input to the CE pin is input to the TRK servo filter.
CETF:
These commands output the TZC signal.
COT2, COT1: This outputs the TZC signal from the COUT pin.
COT2
COT1
1
0
0
—
1
0
∗
COUT pin output
STZC
HPTZC
COUT
∗: preset, —: don't care
MOT2:
The STZC signal is output from the MIRR pin by setting MOT2 to 1.
These commands set the MIRR signal generation circuit.
BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0 like the CXD2586R. These commands are valid only when BTF of $3B is 0.
MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in § 5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. These commands set that time.
The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R.
BTS1 BTS0
∗
0
0
1
1
0
1
0
1
Number of count-up steps per cycle
1
2
4
8
MRC1 MRC0
0
0
1
1
0
1
0
1
Setting time [µs]
5.669∗
11.338
22.675
45.351
∗: preset (when MCK = 128Fs)
– 144 –
CXD3021R
$3D (preset: $3D 00 00)
D15
D14
D13
D12
SFID SFSK THID THSK
SFID:
D11
0
D10
D9
D8
TLD2 TLD1 TLD0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low-frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.
Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally,
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal
transmitted to M00 can be kept uniform by adjusting the K30 value even during the above
switching.
TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE
input pin, the signal transmitted from the TE pin can be obtained as the TRK hold filter input.
Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally,
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, creating a difference in the DC level at M0D. In this case, the DC level of the signal
transmitted to M18 can be kept uniform by adjusting the K46 value even during the above
switching.
SFSK:
THID:
THSK:
∗ See "§ 5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands.
TLD0 to 2:
These turn on and off SLD filter correction independently of the TRK filter.
See $38 (TLC0 to 2) and Fig. 5-3.
Traverse center correction
∗
TLC2
TLD2
0
—
OFF
OFF
0
ON
ON
1
ON
OFF
1
TLC1
TLD1
TRK filter
Tracking zero level correction
TRK filter
∗
0
1
TLC0
0
1
SLD filter
—
OFF
OFF
0
ON
ON
1
ON
OFF
TLD0
VC level correction
TRK filter
∗
SLD filter
SLD filter
—
OFF
OFF
0
ON
ON
1
ON
OFF
∗: preset, —: don't care
– 145 –
CXD3021R
• Input coefficient sign inversion when SFID = 1 and THID = 1
The preset coefficients for the TRK filter are negative for input and positive for output. With this, CXD3021R
outputs servo drives which have the reversed phase of input errors.
Negative input coefficient
Positive output coefficient
∗
TE
TRK Filter
K19
Negative input coefficient
SE
Positive output coefficient
SLD Filter
K00
Positive input coefficient
TRK Hold
K40
K22
K05
Positive output coefficient
TRK Hold Filter
K45
When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient
(K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0H results in 60H.)
For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted.
Negative input coefficient
Positive output coefficient
∗
TE
K19
TRK Filter
K22
MOD
Positive input coefficient
SE
K00
Positive output coefficient
SLD Filter
Negative input coefficient
TRK Hold
K40
K05
Positive output coefficient
TRK Hold Filter
∗ For TRK servo gain normal
See "§ 5-20. Filter Composition".
– 146 –
K45
CXD3021R
$3E (preset: $3E 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD
D5
0
D4
D3
D2
D1
D0
LKIN COIN MDFI MIRI XT1D
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
On when 1; default is 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
On when 1; default is 0.
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
On when 1; default is 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
On when 1; default is 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See "§ 5-20 Filter Composition" at the end of this specification concerning quasi double accuracy.
DFIS:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
TLCD:
This command masks the TLC2 command of $38 only when FOK is low.
On when 1; default is 0
LKIN:
When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.
COIN:
When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
The MIRR, DFCT and FOK signals can also be input from an external source.
MDFI:
When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.
MIRI:
When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.
∗
MDFI
MIRI
0
0
MIRR, DFCT and FOK are all generated internally.
0
1
MIRR only is input from an external source.
1
—
MIRR, DFCT and FOK are all input from an external source.
∗: preset, —: don't care
XT1D:
The clock of the FSTIO pin is used without being frequency-divided as the master clock for the
servo block by setting XT1D to 1. This command takes precedence over the XTSL pin, XT2D
and XT4D. See the description of $3F for XT2D and XT4D.
– 147 –
CXD3021R
$3F (preset: $3F 00 00)
D15
0
D14
D13
D12
D11
AGG4 XT4D XT2D
AGG4:
D10
0
D9
D8
D7
DRR2 DRR1 DRR0
0
D6
D5
D4
D3
D2
D1
ASFG FTQ LPAS SRO1 SRO0 AGHF
D0
0
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is
as shown in the table below.
Sine wave amplitude
AGG4 AGGF AGGT
0
1
XT4D, XT2D:
TE input
conversion
FE input
conversion
0
—
1
—
1/32 × VDD/2
1/16 × VDD/2∗
—
0
—
—
1
—
0
0
1/64 × VDD/2
0
1
1/32 × VDD/2
1
0
1/16 × VDD/2
1
1
1/8 × VDD/2
—
See $37 for AGGF and AGGT.
The presets are AGG4 = 0,
AGGF = 1 and AGGT = 1.
∗: preset, —: don't care
—
1/16 × VDD/2
1/8 × VDD/2∗
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the FSTIO pin clock. See the description of $3E for XT1D. And see "§ 4-12.
Clock System".
∗
XT1D
XT2D
XT4D
Frequency division ratio
0
0
0
According to XTSL
1
—
—
1/1
0
1
—
1/2
0
0
1
1/4
∗: preset, —: don't care
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 on for 50µs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, the FCS servo filter
is forcibly set to gain normal status.
On when 1; default is 0
FTQ:
The focus search-up speed is set to the 1/4 value of that determined by FT1, FT0 and FTZ ($35).
On when 1; default is 0
– 148 –
CXD3021R
LPAS:
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input analog buffers by using a single operational amplifier.
On when 1; default is 0
Note) When using this mode, first check whether each error signal is properly A/D converted
using the $3F commands SRO1 and SRO0.
SRO1, SRO0: These commands are used to continuously externally output various data inside the digital
servo block which have been specified with the $39 command. (However, D15 (DAC) of $39
must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0. (no readout)
The output pins for each case are shown below.
SOCK
XOLT
SOUT
SRO1 = 1
SRO0 = 1
DA13 pin
DA12 pin
DA14 pin
DA10 pin
DA09 pin
DA11 pin
(See "Description of Data Readout" on the following page.)
AGHF:
FTQ:
This halves the frequency of the internally generated sine wave during AGC.
The slope of the output during focus search is 1/4 of the conventional output slope.
On when 1; default is 0
– 149 –
CXD3021R
Description of Data Readout
SOCK
(5.6448MHz)
…
…
…
…
XOLT
(88.2kHz)
SOUT
MSB
…
LSB
MSB
16-bit register
for serial/parallel
conversion
SOUT
…
LSB
16-bit register
for latch
LSB
LSB
To the 7-segment LED
•
•
•
•
•
•
To the 7-segment LED
MSB
MSB
SOCK
CLK
CLK
Data is connected to the 7-segment LED
by 4 bits at a time. This enables Hex
display using four 7-segment LEDs.
XOLT
SOUT
Serial data input
D/A
SOCK
Clock input
XOLT
Latch enable input
Analog
output
To an oscilloscope, etc.
Offset adjustment,
gain adjustment
Waveforms can be monitored with an oscilloscope using a serial
input-type D/A converter as shown above.
– 150 –
CXD3021R
§ 5-19. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 151 –
CXD3021R
<Coefficient Preset Value Table (2)>
ADDRESS
DATA
K30
80
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
K40
K41
K42
K43
K44
K45
K46
04
7F
7F
79
17
6D
00
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
00
02
7F
7F
79
17
54
00
00
CONTENTS
SLED INPUT GAIN
(Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN
(Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
– 152 –
AGFON
2–1
DFCT
K06
K06
Z–1
K08
M03
FCS
In Reg
FCS
Hold Reg2
2–1
DFCT
K06
Z–1
K24
M03
FCS Servo Gain Down fs = 88.2kHz
Sin ROM
FCS
In Reg
FCS
Hold Reg2
FCS Servo Gain Normal fs = 88.2kHz
§ 5-20. Filter Composition
The internal filter composition is shown below.
K∗∗: Coefficient RAM address, M∗∗: Data RAM address
– 153 –
2–7
K0D
K0C
K0E
K27
K26
2–7
2–7
K29
K28
K2A
Z–1
M05
K28
FCS
Hold Reg 1
Z–1
FPS1, 0
BK1
BK2
Z–1
BK3
BK6
M06
Z–1
K10
Z–1
M06
K2C
BK4
Z–1
Note) Set the MSB bit of the K27 and K29 coefficients to 0.
Z–1
K25
2–7
Z–1
M05
FCS
Hold Reg 1
Note) Set the MSB bit of the K0B and K0D coefficients to 0.
K0B
K0A
M04
K09
Z–1
M04
K0F
K13
K13
FCS SRCH
M07
FSC
AUTO Gain
M07
Z–1
BK5
K2D
K11
FCS
AUTO Gain
27
DAC
CXD3021R
AGTON
2–1
DFCT
K19
K19
K1A
Z–1
M0B
2–1
DFCT
K19
K1A
Z–1
M0B
– 154 –
TRK
In Reg
TRK
Hold Reg
2–1
K19
DFCT
Z–1
Z
BK1
–1
TPS1, 0
K36
M0B
TRK Servo Gain Up2 fs = 88.2kHz
TRK
In Reg
TRK
Hold Reg
TRK Servo Gain Up1 fs = 88.2kHz
Sin ROM
TRK
In Reg
TRK
Hold Reg
TRK Servo Gain Normal fs = 88.2kHz
2
–7
K1F
K1E
K20
2
–7
2
–7
K3B
K3A
K3C
Z–1
M0D
K3D
Z–1
M0E
K3E
BK6
BK4
Z–1
BK5
Z–1
TRK JMP
BK9
K3D
Z–1
M0E
K21
Z–1
M0E
Z
BK7
–1
K3E
K22
K23
K23
M0F
Z–1
BK8
K23
TRK
AUTO Gain
M0F
TRK
AUTO Gain
M0F
TRK
AUTO Gain
27
DAC
Note) Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump operation.
BK3
Note) Set the MSB bit of the K39 and K3B coefficients to 0.
K39
K38
M0C
K3C
Z–1
K37
BK2
M0C
Z–1
K1B
2–7
M0D
Z–1
Note) Set the MSB bit of the K1D and K1F coefficients to 0.
K1D
K1C
Z–1
K1B
Z
–1
M0C
To SLD Servo
TRK Hold
CXD3021R
AGFON
2–1
DFCT
K06
K06
2–7
2–7
K09
∗
7FH
K0B
K0A
Z–1
M04
2–7
2
–7
K0D
K0C
K0E
∗
80H
Z–1
M05
2–7
FCS
Hold Reg 1
K10
– 155 –
2–1
DFCT
K06
K11
M07
K13
2–7
2–7
K25
∗
7FH
K27
K26
Z–1
M04
2–7
2–7
K29
K28
K2A
∗
80H
Z–1
M05
K2B
2–7
FCS
Hold Reg 1
K2C
Z–1
M06
K2D
M07
K13
FCS
AUTO Gain
when set to quasi double accuracy.
BK1
Z–1
FPS1, 0
BK2
Z–1
BK3
BK6
BK4
Z–1
BK5
Z–1
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to 0.
K24
∗
81H
Z–1
M03
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values
FCS
In Reg
FCS
Hold Reg 2
Z–1
M06
FCS
AUTO Gain
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to 0.
K08
∗
81H
Z–1
M03
K0F
FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3E5XX0)
Sin ROM
FCS
In Reg
FCS
Hold Reg 2
FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3EAXX0)
27
DAC
CXD3021R
AGTON
2–1
DFCT
K19
K19
2–7
2–7
K1B
∗
7FH
K1D
K1C
Z–1
M0C
2–7
2–7
K1F
K1E
K20
∗
80H
Z–1
M0D
2–7
2–1
DFCT
K19
2–7
2–7
K1B
∗
7FH
Z–1
K3C
∗
80H
M0C
2–7
K3D
Z–1
M0E
Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.
K1A
∗
81H
Z–1
M0B
– 156 –
2–1
DFCT
K19
K36
∗
81H
when set to quasi double accuracy.
2–7
2–7
K37
∗
7FH
Z–1
K39
K38
M0C
2–7
2–7
K3B
K3A
K3C
∗
80H
Z–1
M0D
2–7
BK2
Z–1
BK3
BK6
K3E
K3E
K22
K23
K23
K23
BK4
Z–1
M0F
TRK
AUTO Gain
M0F
TRK
AUTO Gain
M0F
TRK
AUTO Gain
BK5
Z–1
27
TRK JMP
Note) Set SFJP ($36) to 1 or TAOZ ($34D) to 0 in order to boost the low frequency for the TRK Jump operation.
BK1
Z–1
TPS1, 0
Z–1
M0E
K3D
Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37
and K3C coefficients during quasi double accuracy to 0.
Z–1
M0B
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values
TRK
In Reg
TRK
Hold Reg
TRK Servo Gain Up2; fs = 88.2kHz, during quasi double accuracy (Ex. $3EX5X0)
TRK
In Reg
TRK
Hold Reg
K21
Z–1
M0E
Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B
and K20 coefficients during quasi double accuracy to 0.
K1A
∗
81H
Z–1
M0B
TRK Servo Gain Up1; fs = 88.2kHz, during quasi double accuracy (Ex. $3EX5X0)
Sin ROM
TRK
In Reg
TRK
Hold Reg
TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex. $3EXAX0)
BK9
BK7
Z–1
BK8
Z–1
DAC
CXD3021R
CXD3021R
SLD Servo fs = 345Hz
TRK SERVO FILTER
Second-stage output
K30
M0D
2–1
SLD
In Reg
TRK
AUTO Gain
SFSK (only when TGUP2 is used)
SFID
M00
M01
Z–1
Z–1
K00
K05
M02
2–7
K07
DAC
SLD MOV
K01
K03
2–7
2–7
K02
K04
Note) Set the MSB bit of the K02 and K04 coefficients to 0.
HPTZC/Auto Gain fs = 88.2kHz
FCS
In Reg
TRK
In Reg
Sin ROM
2–1
Slice
TZC Reg
AGFON
2–1
AGTON
AGFON
M08
M09
Z–1
K14
Z–1
K15
– 157 –
M0A
Z–1
K17
Slice
AUTO Gain
Reg
CXD3021R
Anti Shock fs = 88.2kHz
2–1
TRK
In Reg
M08
M09
M0A
Z–1
Z–1
Z–1
K12
K31
K16
K35
Comp
Anti Shock
Reg
K33
2–7
K34
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator level is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
2–1
2–7
M08
VC, TE, FE,
RFDC
AVRG Reg
Z–1
TRK Hold fs = 345Hz
TRK SERVO FILTER
Second-stage output
K46
M0D
THID
2–1
THSK (only when TGUP2 is used.)
M18
M19
Z–1
Z–1
K40
SLD
In Reg
K41
K45
TRK
Hold Reg
K43
2–7
2–7
K42
K44
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold fs = 345Hz
FCS
Hold Reg 1
K48
M10
M11
Z–1
Z–1
K49
K4D
FCS
Hold Reg 2
K4B
2–7
2–7
K4A
K4C
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 158 –
CXD3021R
§ 5-21. TRACKING and FOCUS Frequency Response
TRACKING frequency response
40
180°
NORMAL
GAIN UP
30
G
20
0°
φ
10
φ – Phase [degree]
G – Gain [dB]
90°
–90°
0
–10
2.1
10
100
–180°
20k
1k
f – Frequency [Hz]
When using the preset coefficients with the boost function off.
FOCUS frequency response
40
180°
NORMAL
GAINDOWN
30
20
G
0°
10
φ
–90°
0
–10
2.1
10
100
1k
–180°
20k
f – Frequency [Hz]
When using the preset coefficients with the boost function off.
– 159 –
φ – Phase [degree]
G – Gain [dB]
90°
FSW
XTLI
PSSL
AVSS5
ASYE
AVSS3
DVSS1
PWMLN
AVDD1
PWMLP
DVDD1
DVDD4
ASYI
AVDD3
ASYO
SENS
BIAS
SCLK
RFAC
ATSK
AVSS1
DATA
CLTV
XLAT
PCO
CLOK
FILI
MIRR
MIRR
DFCT
DFCT
VPCO1
FOK
VC
XRST 60
SCSY 59
116 AVSS2
120 TE
119 CE
118 RFDC
117 ADIO
2
ADIO
115 IGEN
114 AVDD2
113 V16M
112 VCKI
111 PDO
110 TEST
109 VCOI
108 VCOO
107 DVDD5
106 PWMI
105 TES3
104 TES2
103 DTS0
3
4
7
6
5
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MD2 50
PDO
DOUT 51
100 LOCK
101 SSTP
LOCK
XUGF
GTOP
DA10 32
DA11 31
SCOR
SQCK
GND
MNT3
MNT2
MNT1
MNT0
SCSY
LDON
XWO
SENS
FOK
DATA
XRST
CLOK
XLAT
SQSO
GFS
MUTE
SCLK
Application circuits shown are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any
infringement of third party patent and other right due to same.
XPLCK
DA09 33
DA08 34
DA07 35
RFCK
C2PO
DA06 37
DVDD2 36
XRAOF
DA05 38
DA04 39
DA03 40
DA02 41
DA01 42
DVSS2 43
XTSL 44
MCKO 45
MCKO
C4M
FSTIO 46
C16M
C4M 47
DOUT
C16M 48
DVDD3 49
MUTE 52
102 DVSS5
WFCK 53
98 MDP
99 MDS
MDS
WFCK
SBSO
SCOR 54
97 MON
EXCK
EXCK 56
SBSO 55
1
RFO
AVDD5
LRCK
95 BSSD
CE
FE
AVDD4
LRCKI
96 AVDD6
GND
VC
PWMRP
DA16
SQCK 58
FSW
SE
TE
PWMRN
PCMDI
SQSO 57
TESO
FE
VCC
LDON
FD
TD
FG
COUT
COUT
VPCO2
SPDL
MON
AVSS4
DA15
93 TAO
DVSS4
FILO
VCTL
SLED
XTLO
WDCK
WDCK
SSTP
DVSS3
BCKI
94 FAO
DA13
91 AVSS6
92 SAO
RMUTO
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LPF Circuit
LMUTO
DA14
SOUT
Driver Circuit
Driver Circuit
LPF Circuit
XWO
DA12
XOLT
– 160 –
SOCK
[6] Application Circuit
CXD3021R
CXD3021R
Unit: mm
120PIN LQFP (PLASTIC)
18.0 ± 0.2
1.7 MAX
1.4 ± 0.1
16.0 ± 0.1
90
S
61
0.1
91
S
60
B
A
120
31
1
30
0.5
0.22 ± 0.05
0.1
S
M
0.6 ± 0.15
0.22 ± 0.05
(0.125)
0° to 10°
0.145 ± 0.03
(0.2)
(0.5)
0.25
(17.0)
0.1 ± 0.05
DETAIL A
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-120P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP120-P-1616
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.8g
JEDEC CODE
120PIN LQFP(PLASTIC)
18.0 ± 0.2
1.7MAX
16.0 ± 0.1
1.4 ± 0.1
90
61
60
91
B
A
31
120
1
30
0.5
b
0.10
0.25
M
0.10
S
0.1 ± 0.05
S
(0.15)
1.0 ± 0.2
0.6 ± 0.15
0° to 10°
(0.2)
DETAIL A
+ 0.08
0.17 - 0.05
(17.0)
b=0.22 ± 0.05
(0.5)
Package Outline
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-120P-L051
LEAD TREATMENT
SOLDER
EIAJ CODE
P-LQFP120-16x16-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
0.8g
JEDEC CODE
– 161 –
S