a 2 ADC, 6 DAC, 96 kHz, 24-Bit - Codec AD1838A FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-, 20-, 24-Bit Word Lengths Multibit - Modulators with Perfect Differential Linearity Restoration for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs—Least Sensitive to Jitter Differential Output for Optimum Performance ADCs: –95 dB THD + N, 105 dB SNR and Dynamic Range DACs: –95 dB THD + N, 108 dB SNR and Dynamic Range On-Chip Volume Controls per Channel with 1024 Step Linear Scale DAC and ADC Software Controllable Clickless Mutes Digital De-emphasis Processing Supports 256 fS, 512 fS, and 768 fS Master Mode Clocks Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, I2S Compatible, and DSP Serial Port Modes TDM Interface Mode Supports 8 In/8 Out Using a Single SHARC ® SPORT 52-Lead MQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theater Systems Automotive Audio Systems Audio/Visual Receivers Digital Audio Effects Processors GENERAL DESCRIPTION The AD1838A is a high performance single-chip codec featuring three stereo DACs and one stereo ADC. Each DAC comprises a high performance digital interpolation filter, a multibit - modulator featuring Analog Devices’ patented technology, and a continuous-time voltage out analog section. Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit - modulators and decimation filters. The AD1838A also contains an on-chip reference with a nominal value of 2.25 V. The AD1838A contains a flexible serial interface that allows glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1838A can be configured in left-justified, right-justified, I2S, or DSP compatible serial modes. Control of the AD1838A is achieved by means of an SPI® compatible serial port. While the AD1838A can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1838A is available in a 52-lead MQFP package and is specified for the industrial temperature range of –40ºC to +85ºC. FUNCTIONAL BLOCK DIAGRAM DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT AAUXDATA3 CONTROL PORT MCLK PD/RST M/S AVDD AVDD CLOCK DLRCLK SERIAL DATA I/O PORT DBCLK DSDATA1 VOLUME VOLUME DIGITAL FILTER - DAC OUTLP1 OUTLN1 OUTRP1 OUTRN1 DIGITAL FILTER - DAC OUTLP2 OUTLN2 OUTRP2 OUTRN2 DIGITAL FILTER - DAC OUTLP3 OUTLN3 OUTRP3 OUTRN3 DSDATA2 VOLUME DSDATA3 VOLUME DAUXDATA VOLUME ADCLP ADCLN ADCRP ADCRN −∆ ADC DIGITAL FILTER −∆ ADC DIGITAL FILTER VOLUME VREF FILTD FILTR AD1838A DGND DGND AGND AGND AGND AGND REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD1838A–SPECIFICATIONS TEST CONDITIONS Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock DAC Input Signal ADC Input Signal Input Sample Rate (fS) Measurement Bandwidth Word Width Load Capacitance Load Impedance 5.0 V 25°C 12.288 MHz (256 fS Mode) 1.0078125 kHz, 0 dBFS (Full Scale) 1.0078125 kHz, –1 dBFS 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 47 kΩ Performance of all channels is identical (except for the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter Min ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise (THD + N) 48 kHz 96 kHz Interchannel Isolation Interchannel Gain Mismatch Analog Inputs Differential Input Range (± Full Scale) Common-Mode Input Voltage Input Impedance Input Capacitance VREF DC Accuracy Gain Error Gain Drift 100 Typ Bits 103 105 dB dB –88.5 –87.5 dB dB dB dB +2.828 2.25 4 15 2.25 V V kΩ pF V ±5 35 % ppm/ºC 24 Bits 105 108 –95 110 dB dB dB dB –2.828 103 105 ADC DECIMATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay –2– Unit 24 –95 –95 100 0.025 DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input) No Filter With A-Weighted Filter (48 kHz and 96 kHz) Total Harmonic Distortion + Noise (48 kHz and 96 kHz) Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Maximum Attenuation) Mute Attenuation De-emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance at Each Pin Common-Mode Output Voltage Max –90 ± 4.0 0.025 200 ± 0.1 0.098 60 –100 ± 0.1 1.0 (2.8) 180 2.25 % dB ppm/°C Degrees % dB dB dB V rms (V p-p) Ω V 21.77 ± 0.01 26.23 120 910 kHz dB kHz dB µs REV. A AD1838A Parameter Min ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay Max 43.54 ± 0.01 52.46 120 460 DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay 21.77 kHz dB kHz dB µs 43.54 kHz dB kHz dB µs 81 kHz dB kHz dB µs 28 55 340 ± 0.06 52 55 160 DAC INTERPOLATION FILTER, 192 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay ± 0.06 97 80 110 DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current 2.4 0.4 ± 10 V V V V µA 5.5 DVDD 95 67 74 4.5 V V mA mA mA mA 0.8 ODVDD – 0.4 POWER SUPPLIES Supply Voltage (AVDD and DVDD) Supply Voltage (ODVDD) Supply Current IANALOG Supply Current IANALOG, Power-Down Supply Current IDIGITAL Supply Current IDIGITAL, Power-Down Dissipation Operation, Both Supplies Operation, Analog Supply Operation, Digital Supply Power-Down, Both Supplies Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 20 kHz, 300 mV p-p Signal at Analog Supply Pins 4.5 3.0 5.0 84 55 64 1 *Guaranteed by design. Specifications subject to change without notice. –3– Unit kHz dB kHz dB µs ± 0.06 DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay REV. A Typ 740 420 320 280 mW mW mW mW –70 –75 dB dB AD1838A TIMING SPECIFICATIONS Parameter Min MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low tPDR PD/RST Low 15 15 20 ns ns ns 40 40 80 10 10 10 10 ns ns ns ns ns ns ns ns ns ns SPI PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH tCOE tCOD tCOTS CCLK High CCLK Low CCLK Period CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold COUT Enable COUT Delay COUT Three-State DAC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Slave) tDBH DBCLK High DBCLK Low tDBL fDB DBCLK Frequency tDLS DLRCLK Setup DLRCLK Hold tDLH tDDS DSDATA Setup tDDH DSDATA Hold Packed 128/256 Modes (Slave) DBCLK High tDBH tDBL DBCLK Low DBCLK Frequency fDB tDLS DLRCLK Setup tDLH DLRCLK Hold DSDATA Setup tDDS tDDH DSDATA Hold ADC SERIAL PORT (48 kHz and 96 kHz) Normal Mode (Master) tABD ABCLK Delay ALRCLK Delay tALD tABDD ASDATA Delay Normal Mode (Slave) ABCLK High tABH tABL ABCLK Low fAB ABCLK Frequency tALS ALRCLK Setup tALH ALRCLK Hold tABDD ASDATA Delay Packed 128/256 Mode (Master) ABCLK Delay tPABD tPALD LRCLK Delay tPABDD ASDATA Delay Max 15 20 25 Unit 60 60 64 fS 10 10 10 10 ns ns 15 15 256 fS 10 10 10 10 ns ns ns ns ns ns 25 5 10 60 60 64 fS 5 15 Comments To CCLK Rising Edge From CCLK Rising Edge To CCLK Rising Edge From CCLK Rising Edge From CLATCH Falling Edge From CCLK Falling Edge From CLATCH Rising Edge To DBCLK Rising Edge From DBCLK Rising Edge To DBCLK Rising Edge From DBCLK Rising Edge ns ns ns ns To DBCLK Rising Edge From DBCLK Rising Edge To DBCLK Rising Edge From DBCLK Rising Edge ns ns ns From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge ns ns –4– 15 ns ns ns To ABCLK Rising Edge From ABCLK Rising Edge From ABCLK Falling Edge 40 5 10 ns ns ns From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge REV. A AD1838A Parameter Min TDM256 MODE (Master, 48 kHz and 96 kHz) tTBD BCLK Delay FSTDM Delay tFSD tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM256 MODE (Slave, 48 kHz and 96 kHz) fAB BCLK Frequency tTBCH BCLK High BCLK Low tTBCL FSTDM Setup tTFS tTFH FSTDM Hold ASDATA Delay tTBDD DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold Max Unit Comments 40 5 10 ns ns ns ns ns From MCLK Rising Edge From BCLK Rising Edge From BCLK Rising Edge To BCLK Falling Edge From BCLK Falling Edge ns ns ns ns ns ns ns To BCLK Falling Edge From BCLK Falling Edge From BCLK Rising Edge To BCLK Falling Edge From BCLK Falling Edge ns ns ns ns ns From MCLK Rising Edge From BCLK Rising Edge From BCLK Rising Edge To BCLK Falling Edge From BCLK Falling Edge ns ns ns ns ns ns ns To BCLK Falling Edge From BCLK Falling Edge From BCLK Rising Edge To BCLK Falling Edge From BCLK Falling Edge 10 10 20 64 fS ns ns ns To AUXBCLK Rising Edge From AUXBCLK Rising Edge From AUXBCLK Falling Edge 15 15 10 10 ns ns ns ns To AUXBCLK Rising Edge From AUXBCLK Rising Edge 20 15 ns ns From MCLK Rising Edge From AUXBCLK Falling Edge 15 15 256 fS 17 17 10 10 15 15 15 TDM512 MODE (Master, 48 kHz) tTBD BCLK Delay FSTDM Delay tFSD tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold 40 5 10 15 15 TDM512 MODE (Slave, 48 kHz ) BCLK Frequency fAB tTBCH BCLK High tTBCL BCLK Low FSTDM Setup tTFS tTFH FSTDM Hold tTBDD ASDATA Delay DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold 512 fS 17 17 10 10 15 15 15 AUXILIARY INTERFACE (48 kHz and 96 kHz) tAXDS AAUXDATA Setup tAXDH AAUXDATA Hold DAUXDATA Delay tDXD fABP AUXBCLK Frequency Slave Mode AUXBCLK High tAXBH tAXBL AUXBCLK Low tAXLS AUXLRCLK Setup AUXLRCLK Hold tAXLH Master Mode tAUXBCLK AUXBCLK Delay tAUXLRCLK AUXLRCLK Delay Specifications subject to change without notice. tMH tMCLK MCLK tML PD/RST tPDR Figure 1. MCLK and PD/RST Timing REV. A –5– AD1838A TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) AVDD, DVDD, ODVDD to AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . –0.3 V to ODVDD + 0.3 V Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C Parameter Min Specifications Guaranteed Functionality Guaranteed Storage –40 –65 Typ Max Unit +85 +150 °C °C °C 25 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option AD1838AAS AD1838AAS-REEL AD1838AASZ* AD1838AASZ-REEL* EVAL-AD1838AEB –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP 52-Lead MQFP S-52-1 S-52-1 S-52-1 S-52-1 S-52-1 *Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1838A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– REV. A AD1838A DGND CCLK COUT ASDATA ODVDD MCLK ALRCLK ABCLK AAUXDATA3 DSDATA3 DSDATA2 DSDATA1 DGND PIN CONFIGURATION 52 51 50 49 48 47 46 45 44 43 42 41 40 DVDD 1 39 DVDD CLATCH 2 38 DBCLK CIN 3 37 DLRCLK PD/RST 4 36 DAUXDATA AGND 5 35 M/S OUTLN1 6 AD1838A OUTLP1 7 OUTRN1 TOP VIEW (Not to Scale) 8 32 N/C OUTRP1 9 31 N/C 34 AGND 33 N/C AGND 10 30 AGND AVDD 11 29 AVDD 19 20 21 22 23 24 25 26 ADCRN ADCRP AGND OUTLN3 OUTLP3 18 ADCLP 17 ADCLN 16 AVDD 15 FILTR OUTRN2 14 FILTD 27 OUTRN3 AGND 28 OUTRP3 OUTLP2 13 OUTRP2 OUTLN2 12 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic 1, 39 2 3 4 5, 10, 16, 24, 30, 34 6, 12, 25 7, 13, 26 8, 14, 27 9, 15, 28 11, 19, 29 17 18 20 21 22 23 31 to 33 35 36 37 38 40, 52 41 to 43 44 45 46 47 48 49 50 51 DVDD CLATCH CIN PD/RST AGND OUTLNx OUTLPx OUTRNx OUTRPx AVDD FILTD FILTR ADCLN ADCLP ADCRN ADCRP N/C M/S DAUXDATA DLRCLK DBCLK DGND DSDATAx AAUXDATA3 ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK REV. A Input/ Output I I I O O O O I I I I I O I/O I/O I I I/O I/O I O O I Description Digital Power Supply. Connect to digital 5 V supply. Latch Input for Control Data. Serial Control Input. Power-Down/Reset. Analog Ground. DACx Left Channel Negative Output. DACx Left Channel Positive Output. DACx Right Channel Negative Output. DACx Right Channel Positive Output. Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor Connection. Recommended 10 µF/100 nF. Reference Filter Capacitor Connection. Recommended 10 µF/100 nF. ADC Left Channel Negative Input. ADC Left Channel Positive Input. ADC Right Channel Negative Input. ADC Right Channel Positive Input. Not Connected. ADC Master/Slave Select. Auxiliary DAC Output Data. DAC LR Clock. DAC Bit Clock. Digital Ground. DACx Input Data (Left and Right Channels). Auxiliary ADC3 Digital Input. ADC Bit Clock. ADC LR Clock. Master Clock Input. Digital Output Driver Power Supply. ADC Serial Data Output. Output for Control Data. Control Clock Input for Control Data. –7– AD1838A–Typical Performance Characteristics 5 0 0 –5 MAGNITUDE – dB MAGNITUDE – dB –50 –100 –10 –15 –20 –150 –25 0 5 10 –30 15 0 5 FREQUENCY – Normalized to fS TPC 1. ADC Composite Filter Response 10 FREQUENCY – Hz 15 20 TPC 4. ADC High-Pass Filter Response, fS = 96 kHz 0 5 0 MAGNITUDE – dB MAGNITUDE – dB –5 –10 –15 –50 –100 –20 –25 –30 –150 0 5 10 FREQUENCY – Hz 15 20 TPC 2. ADC High-Pass Filter Response, fS = 48 kHz 50 100 FREQUENCY – kHz 150 200 TPC 5. DAC Composite Filter Response, fS = 48 kHz 0 MAGNITUDE – dB 0 MAGNITUDE – dB 0 –50 –100 –150 0 0.5 1.0 1.5 –50 –100 –150 2.0 FREQUENCY – Normalized to fS 0 50 100 150 200 FREQUENCY – kHz TPC 3. ADC Composite Filter Response (Pass-Band Section) TPC 6. DAC Composite Filter Response, fS = 96 kHz –8– REV. A AD1838A 0.2 0 0.1 MAGNITUDE – dB MAGNITUDE – dB –50 –100 0 –0.1 –150 –0.2 0 50 100 FREQUENCY – kHz 150 200 0.05 0.05 MAGNITUDE – dB 0.10 MAGNITUDE – dB 0.10 0 20 30 FREQUENCY – kHz 40 50 0 –0.05 –0.05 –0.10 0 5 10 FREQUENCY – kHz 15 20 TPC 8. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section) REV. A 10 TPC 9. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section) TPC 7. DAC Composite Filter Response, fS = 192 kHz –0.10 0 0 20 40 60 FREQUENCY – kHz 80 100 TPC 10. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section) –9– AD1838A TERMINOLOGY Dynamic Range Gain Drift The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic range is measured with a –60 dB input signal and is equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics are below the noise with a –60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-weight filter applied. Signal-to-(Total Harmonic Distortion + Noise) [S/(THD + N)] The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. Pass Band The region of the frequency spectrum unaffected by the attenuation of the digital decimator’s filter. Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per °C. Crosstalk (EIAJ Method) Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels. Power Supply Rejection With no analog input, signal present at the output when a 300 mV p-p signal is applied to the power supply pins, expressed in decibels of full scale. Group Delay Intuitively, the time interval required for an input pulse to appear at the converter’s output, expressed in microseconds. More precisely, the derivative of radian phase with respect to the radian frequency at a given frequency. Group Delay Variation Pass-Band Ripple The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels. The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds. Stop Band ACRONYMS The region of the frequency spectrum attenuated by the digital decimator’s filter to the degree specified by stop-band attenuation. ADC—Analog-to-Digital Converter. Gain Error DAC—Digital-to-Analog Converter. DSP—Digital Signal Processor. With identical near full-scale inputs, the ratio of actual output to expected output, expressed as a percentage. IMCLK—Internal Master Clock Signal Used to Clock the ADC and DAC Engines. Interchannel Gain Mismatch MCLK—External Master Clock Signal Applied to the AD1838A. With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. –10– REV. A AD1838A FUNCTIONAL OVERVIEW ADCs Table I. Coding Scheme There are two ADC channels in the AD1838A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation). ADC peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to –63 dB and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. Refer to the register description for details of the format. The two ADC channels have a common serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. Code Level 0111 . . . . 11111 0000 . . . . 00000 1000 . . . . 00000 +FS 0 (Ref Level) –FS AD1838A CLOCKING SCHEME By default, the AD1838A requires an MCLK signal that is 256 times the required sample frequency up to a maximum of 12.288 MHz. The AD1838A uses a clock scaler to double the clock frequency for use internally. The default setting of the clock scaler is Multiply by 2. The clock scaler can also be set Multiply by 1 (bypass) or by 2/3. The clock scaler is controlled by programming the bits in the ADC Control 3 register. The internal MCLK signal, IMCLK, should not exceed 24.576 MHz to ensure correct operation. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1838A will generate the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller. The MCLK of the AD1838A should remain constant during normal operation of the DAC and ADC. If it is required to change the MCLK rate, then the AD1838A should be reset. Additionally, if MCLK scaler needs to be modified so that the IMCLK does not exceed 24.576 MHz, this should be done during the internal reset phase of the AD1838A by programming the bits in the first 3072 MCLK periods following the reset. DACs Selecting DAC Sampling Rate The AD1838A has six DAC channels arranged as three independent stereo pairs, with six fully differential analog outputs for improved noise and distortion performance. Each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. Digital inputs are supplied through three serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the packed data modes may be used to access all six channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1838A can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate feature can then be used to copy the audio data to the other DACs. The AD1838A DAC engine has a programmable interpolator that allows the user to select different interpolation rates based on the required sample rate and MCLK value available. Table II shows the settings required for sample rates based on a fixed MCLK of 12.288 MHz. Each set of differential output pins sits at a dc level of VREF and swings ± 1.4 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. In some cases, this capacitor may be eliminated with little effect on performance. DAC and ADC Coding The DAC and ADC output data stream is in a twos complement encoded format. The word width can be selected from 16 bit, 20 bit, or 24 bit. The coding scheme is detailed in Table I. REV. A Table II. DAC Sample Rate Settings Sample Rate Interpolator Rate DAC Control 1 Register 48 kHz 96 kHz 192 kHz 8 4 2 000000xxxxxxxx00 000000xxxxxxxx01 000000xxxxxxxx10 Selecting an ADC Sample Rate The AD1838A ADC engine has a programmable decimator that allows the user to select the sample rate based on the MCLK value. By default, the output sample rate is IMCLK/512. To achieve a sample rate of IMCLK/256, the sample rate bit in the ADC Control 1 register should be set as shown in Table III. Table III. ADC Sample Rate Settings Sample Rate ADC Control 1 Register IMCLK/512 IMCLK/256 1100000xx0xxxxxx (48 kHz) 1100000xx1xxxxxx (96 kHz) To maintain the highest performance possible, it is recommended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. It is highly recommended that the master clock be generated by an independent crystal oscillator. In addition, it is especially important that the clock signal should not be passed through an FPGA or other large digital chip before being applied to the AD1838A. In most cases, this will induce clock jitter because the clock signal is sharing common power and ground connections with other unrelated digital output signals. –11– AD1838A DAC ENGINE DAC INPUT 48kHz/96kHz/192kHz INTERPOLATION FILTER - MODULATOR DAC ANALOG OUTPUT - MODULATOR ANALOG INPUT CLOCK SCALING 1 MCLK IMCLK = 24.576MHz 2 12.288MHz 2/3 ADC ENGINE ADC OUTPUT 48kHz/96kHz OPTIONAL HPF DECIMATOR/ FILTER Figure 2. Modulator Clocking Scheme tCLS CLATCH tCLH tCCH tCCL tCCP tCOTS CCLK tCDS tCDH D15 CIN COUT D14 tCOE D9 D8 D0 D9 D8 D0 tCOD Figure 3. Format of SPI Timing RESET and Power-Down PD/RST powers down the chip and sets the control registers to their default settings. After PD/RST is de-asserted, an initialization routine runs inside the AD1838A to clear all memories to zero. This initialization lasts for approximately 20 LRCLK intervals. During this time, it is recommended that no SPI writes occur. Power Supply and Voltage Reference The AD1838A is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 µF should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by two ferrite beads in series with the bypass capacitor of each supply. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on the FILTR pin and should be bypassed as close as possible to the chip, with a parallel combination of 10 µF and 100 nF. The reference volt- age may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. The current drawn from the FILTR pin should be limited to less than 50 µA. Serial Control Port The AD1838A has an SPI compatible control port to permit programming the internal control registers for the ADCs and DACs and to read the ADC signal levels from the internal peak detectors. The SPI control port is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 16 bits wide. The maximum serial bit clock frequency is 12.5 MHz and may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 3 shows the format of the SPI signal. Serial Data Ports—Data Format The ADC serial data output mode defaults to the popular I2S format, where the data is delayed by one BCLK interval from the edge of the LRCLK. By changing Bits 6 to 8 in ADC Control Register 2, the serial mode can be changed to right-justified (RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ mode, it is necessary to set Bits 4 and 5 to define the width of the data-word. –12– REV. A AD1838A The DAC serial data input mode defaults to I2S. By changing Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, or Packed Mode 256. The word width defaults to 24 bits but can be changed by reprogramming Bits 3 and 4 in DAC Control Register 1. Auxiliary (TDM) Mode A special auxiliary mode is provided to allow three external stereo ADCs and one external stereo DAC to be interfaced to the AD1838A to provide 8-in/8-out operation. In addition, this mode supports glueless interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined; see Table IV for a list of redefined pins. The auxiliary and the TDM interfaces are independently configurable to operate as masters or slaves. When the auxiliary interface is set as a master, by programming the Auxiliary Mode Bit in ADC Control Register 2, the AUXLRCLK and AUXBCLK are generated by the AD1838A. When the auxiliary interface is set as a slave, the AUXLRCLK and AUXBCLK need to be generated by an external ADC, as shown in Figure 13. The TDM interface can be set to operate as a master or slave by connecting the M/S pin to DGND or ODVDD, respectively. In master mode, the FSTDM and BCLK signals are outputs generated by the AD1838A. In slave mode, the FSTDM and BCLK are inputs and should be generated by the SHARC. Both 48 kHz and 96 kHz operations are available (based on a 12.288 MHz or 24.576 MHz MCLK) in this mode. Packed Modes The AD1838A has a packed mode that allows a DSP or other controller to write to all DACs and read all ADCs using one input data pin and one output data pin. Packed Mode 256 refers to the number of BCLKs in each frame. The LRCLK is low while data from a left channel DAC or ADC is on the data pin, and high while data from a right channel DAC or ADC is on the data pin. DAC data is applied on the DSDATA1 pin, and ADC data is available on the ASDATA pin. Figures 7 to 10 show the timing for the packed mode. Packed mode is available for 48 kHz and 96 kHz. LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB I2S LSB MSB MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK LSB MSB SDATA LSB MSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/ fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 4. Stereo Serial Modes REV. A –13– LSB AD1838A tABH ABCLK tABL tABDD tALS tALH ALRCLK ASDATA LEFT-JUSTIFIED MODE MSB ASDATA I2S COMPATIBLE MODE MSB-1 MSB ASDATA RIGHT-JUSTIFIED MODE MSB LSB Figure 5. ADC Serial Mode Timing tDBH DBCLK tDBL tDLS tDLH DLRCLK DSDATA LEFT-JUSTIFIED MODE tDDS MSB MSB-1 tDDH DSDATA I2S COMPATIBLE MODE tDDS MSB tDDH tDDS tDDS DSDATA RIGHT-JUSTIFIED MODE MSB tDDH LSB tDDH Figure 6. DAC Serial Mode Timing –14– REV. A AD1838A LRCLK 128 BCLKs BCLK 16 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 MSB SLOT 3 SLOT 4 MSB – 1 SLOT 5 RIGHT SLOT 6 SLOT 7 SLOT 8 SLOT 7 SLOT 8 MSB – 2 Figure 7a. ADC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 MSB SLOT 3 SLOT 4 MSB – 1 SLOT 5 RIGHT SLOT 6 MSB – 2 Figure 7b. ADC Packed Mode 256 LRCLK 128 BCLKs BCLK 16 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 MSB – 2 Figure 8a. DAC Packed Mode 128 LRCLK 256 BCLKs BCLK 32 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 MSB SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4 MSB – 1 MSB – 2 Figure 8b. DAC Packed Mode 256 REV. A –15– AD1838A tABH tDBH ABCLK DBCLK tABL tDBL tALS tDLS ALRCLK DLRCLK tALH ASDATA tDLH tABDD MSB tDDS DSDATA MSB – 1 MSB MSB – 1 tDDH Figure 9. ADC Packed Mode Timing Figure 10. DAC Packed Mode Timing –16– REV. A AD1838A Table IV. Pin Function Changes in Auxiliary Mode I2S Mode Pin Name Auxiliary Mode 2 ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK (I/O) I S Data Out, Internal ADC I2S Data In, Internal DAC1 I2S Data In, Internal DAC2 I2S Data In, Internal DAC3 Not Connected LRCLK for ADC BCLK for ADC LRCLK In/Out Internal DACs DBCLK (I)/AUXBCLK (I/O) BCLK In/Out Internal DACs DAUXDATA (O) Not Connected TDM Data Out to SHARC. TDM Data In from SHARC. AUX-I2S Data In 1 (from External ADC). AUX-I2S Data In 2 (from External ADC). AUX-I2S Data In 3 (from External ADC). TDM Frame Sync Out to SHARC (FSTDM). TDM BCLK Out to SHARC. AUX LRCLK In/Out. Driven by external LRCLK from ADC in slave mode. In master mode, driven by MCLK/512. AUX BCLK In/Out. Driven by external BCLK from ADC in slave mode. In master mode, driven by MCLK/8. AUX-I2S Data Out (to External DAC). FSTDM BCLK TDM TDM INTERFACE ASDATA1 TDM (OUT) ASDATA MSB TDM MSB TDM 1ST CH 8TH CH INTERNAL ADC L1 AUX_ADC L2 AUX_ADC L3 AUX_ADC L4 INTERNAL ADC R1 AUX_ADC R2 AUX_ADC R3 AUX_ADC R4 32 DSDATA1 TDM (IN) DSDATA1 MSB TDM MSB TDM 1ST CH 8TH CH INTERNAL DAC L1 INTERNAL DAC L2 INTERNAL DAC L3 INTERNAL DAC L4 INTERNAL DAC R1 INTERNAL DAC R2 INTERNAL DAC R3 INTERNAL DAC R4 32 AUX – I2S INTERFACE AUX LRCLK I2S (FROM AUX ADC NO. 1) RIGHT LEFT AUX BCLK I2S (FROM AUX ADC NO. 1) AAUXDATA1 (IN) (FROM AUX ADC NO. 1) I2S – MSB LEFT I2S – MSB RIGHT AAUXDATA2 (IN) (FROM AUX ADC NO. 2) I2S – MSB LEFT I2S – MSB RIGHT AAUXDATA3 (IN) (FROM AUX ADC NO. 3) I2S – MSB LEFT I2S – MSB RIGHT AUXBCLK FREQUENCY IS 64 FRAME RATE; TDM BCLK FREQUENCY IS 256 FRAME RATE. Figure 11. Auxiliary Mode Timing REV. A –17– AD1838A TxDATA TxCLK TFS (NC) RxDATA LRCLK SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT DRIVEN). SHARC RxCLK 12.288MHz FSYNC-TDM (RFS) 30MHz ADC NO. 1 BCLK SLAVE DATA MCLK LRCLK ADC NO. 2 BCLK SLAVE DATA ASDATA FSTDM BCLK DSDATA1 MCLK LRCLK DBCLK/AUXBCLK DLRCLK/AUXLRCLK LRCLK DSDATA2/AAUXDATA1 ADC NO. 3 BCLK SLAVE DATA DSDATA3/AAUXDATA2 AAUXDATA3 DAUXDATA BCLK DAC NO. 1 SLAVE DATA MCLK AD1838A MASTER MCLK MCLK Figure 12. Auxiliary Mode Connection (Master Mode) to SHARC TxDATA TxCLK TFS (NC) RxDATA LRCLK SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT DRIVEN). SHARC RxCLK 12.288MHz FSYNC-TDM (RFS) 30MHz ADC NO. 1 BCLK MASTER DATA MCLK LRCLK ADC NO. 2 BCLK SLAVE DATA ASDATA FSTDM BCLK DSDATA1 MCLK LRCLK DBCLK/AUXBCLK DLRCLK/AUXLRCLK LRCLK DSDATA2/AAUXDATA1 ADC NO. 3 BCLK SLAVE DATA DSDATA3/AAUXDATA2 AAUXDATA3 MCLK DAUXDATA BCLK DAC NO. 1 SLAVE DATA MCLK AD1838A SLAVE MCLK Figure 13. Auxiliary Mode Connection (Slave Mode) to SHARC –18– REV. A AD1838A CONTROL/STATUS REGISTERS DAC Volume Control The AD1838A has 13 control registers, 11 of which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each of the registers is 10 bits wide with the exception of the ADC peak reading registers, which are 6 bits wide. Writing to a control register requires a 16-bit data frame to be transmitted. Bits 15 to 12 are the address bits of the required register. Bit 11 is a read/write bit. Bit 10 is reserved and should always be programmed to 0. Bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. Figure 3 shows the format of the SPI read and write operation. Each DAC in the AD1838A has its own independent volume control. The volume of each DAC can be adjusted in 1024 linear steps by programming the appropriate register. The default value for this register is 1023, which provides no attenuation, i.e., full volume. DAC Control Registers The AD1838A register map has eight registers that are used to control the functionality of the DAC section of the part. The function of the bits in these registers is discussed below. Sample Rate These bits control the sample rate of the DACs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and 192 kHz are available. The MCLK scaling bits in ADC Control Register 3 should be programmed appropriately, based on the master clock frequency. Power-Down/Reset This bit controls the power-down status of the DAC section. By default, normal mode is selected. But by setting this bit, the digital section of the DAC stage can be put into a low power mode, thus reducing the digital current. The analog output section of the DAC stage is not powered down. DAC Data-Word Width These two bits set the word width of the DAC data. Compact disk (CD) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution. DAC Data Format ADC Control Registers The AD1838A register map has five registers that are used to control the functionality and to read the status of the ADCs. The function of the bits in each of these registers is discussed below. ADC Peak Level These two registers store the peak ADC result from each channel when the ADC peak readback function is enabled. The peak result is stored as a 6-bit number from 0 dB to –63 dB in 1 dB steps. The value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. Note that the ADC peak level registers use the 6 MSB in the register to store the results. Sample Rate This bit controls the sample rate of the ADCs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are available. The MCLK scaling bits in ADC Control Register 3 should be programmed appropriately based on the master clock frequency. ADC Power-Down This bit controls the power-down status of the ADC section and operates in a similar manner to the DAC power-down. High-Pass Filter The ADC signal path has a digital high-pass filter. Enabling this filter removes the effect of any dc offset in the analog input signal from the digital output codes. ADC Data-Word Width These two bits set the word width of the ADC data. The AD1838A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Details of these interface modes are given in the Serial Data Port section. ADC Data Format De-emphasis Master/Slave Auxiliary Mode The AD1838A provides built-in de-emphasis filtering for the three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz. Mute DAC Each of the six DACs in the AD1838A has its own independent mute control. Setting the appropriate bit mutes the DAC output. The AD1838A uses a clickless mute function that attenuates the output to approximately –100 dB over a number of cycles. Stereo Replicate The AD1838A serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. When the AD1838A is operating in the auxiliary mode, the auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which connect to the external ADCs, can be set to operate as a master or slave. If the pins are set in slave mode, one of the external ADCs should provide the LRCLK and BCLK signals. ADC Peak Readback Setting this bit enables ADC peak reading. See the ADCs section for more information. Setting this bit copies the digital data sent to the stereo pair DAC1 to the three other stereo DACs in the system. This allows all three stereo DACs to be driven by one digital data stream. Note that in this mode, DAC data sent to the other DACs is ignored. REV. A –19– AD1838A Table V. Control Register Map Register Address Register Name Description Type Width Reset Setting (Hex) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DACCTRL1 DACCTRL2 DACVOL1 DACVOL2 DACVOL3 DACVOL4 DACVOL5 DACVOL6 Reserved Reserved ADCPeak0 ADCPeak1 ADCCTRL1 ADCCTRL2 ADCCTRL3 Reserved DAC Control 1 DAC Control 2 DAC Volume—Left 1 DAC Volume—Right 1 DAC Volume—Left 2 DAC Volume—Right 2 DAC Volume—Left 3 DAC Volume—Right 3 Reserved Reserved ADC Left Peak ADC Right Peak ADC Control 1 ADC Control 2 ADC Control 3 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W 10 10 10 10 10 10 10 10 10 10 6 6 10 10 10 10 000 000 3FF 3FF 3FF 3FF 3FF 3FF Reserved Reserved 000 000 000 000 000 Reserved Table VI. DAC Control 1 Address R/W RES De-emphasis DAC Data Format DAC DataWord Width Function Power-Down Reset Sample Rate 15, 14, 13, 12 11 10 9, 8 7, 6, 5 4, 3 2 1, 0 0000 0 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed 128 110 = Reserved 111 = Reserved 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved 0 = Normal 1 = Power-Down 00 = 48 kHz 01 = 96 kHz 10 = 192 kHz 11 = 48 kHz 0 Table VII. DAC Control 2 Function MUTE DAC Stereo Address R/W W RES Reserved Replicate Reserved Reserved OUTR3 OUTL3 OUTR2 15, 14, 13, 12 11 10 9 8 7 6 5 4 3 0001 0 0 0 0 = Off 0 1 = Replicate 0 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute –20– OUTL2 2 OUTR1 OUTL1 1 0 REV. A AD1838A Table IX. ADC Peak Table VIII. DAC Volume Control Function Function Address R/W RES DAC Volume 15, 14, 13, 12 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0010 = DACL1 0011 = DACR1 0100 = DACL2 0101 = DACR2 0110 = DACL3 0111 = DACR3 0 0 0000000000 = Mute 0000000001 = 1/1023 0000000010 = 2/1023 1111111110 = 1022/1023 1111111111 = 1023/1023 Address R/W RES Six Data Bits Four Fixed Bits 15, 14, 13, 12 11 1010 = Left ADC 1 1011 = Right ADC 10 9, 8, 7, 6, 5, 4 3, 2, 1, 0 0 000000 = 0 dBFS 000001 = –1 dBFS 000010 = –2 dBFS 0000 These four bits are always zero. 111111 = –63 dBFS Table X. ADC Control 1 Function Address R/W RES Reserved Filter ADC Power-Down Sample Rate Reserved 15, 14, 13, 12 11 10 9 8 7 6 5, 4, 3, 2, 1, 0 1100 0 0 0 0 = All Pass 1 = High-Pass 0 = Normal 1 = Power-Down 0 = 48 kHz 1 = 96 kHz 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0 Table XI. ADC Control 2 Function Address R/W RES Master/Slave ADC Aux Mode Data Format ADC DataWord Width ADC MUTE AUXDATA RES Right Left 15, 14, 13, 12 11 10 9 8, 7, 6 5, 4 3 2 1 1101 0 0 = Slave 1 = Master 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Packed 128 110 = Auxiliary 256 111 = Auxiliary 512 101 = Packed 128 110 = Auxiliary 256 111 = Auxiliary 512 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved 0 = Off 1 = On 0 0 = On 0 = On 1 = Mute 1 = Mute 0 0 Table XII. ADC Control 3 Address 15, 14, 13, 12 1110 REV. A R/W RES RES Reserved 11 10 9, 8 0 0 0, 0 IMCLK Clocking Scaling 7, 6 00 = MCLK 2 01 = MCLK 10 = MCLK 2/3 11 = MCLK 2 Function ADC Peak Readback 5 0 = Disabled Peak Readback 1 = Enabled Peak Readback –21– DAC Test Mode 4, 3, 2 000 = Normal Mode All Others Reserved ADC Test Mode 1, 0 00 = Normal Mode All Others Reserved AD1838A With Device 1 set as a master, it will generate the frame-sync and bit clock signals. These signals are sent to the SHARC and Device 2 ensuring that both know when to send and receive data. CASCADE MODE Dual AD1838A Cascade SHARC (SLAVE) DSDATA ASDATA ALRCLK ABCLK DIN BCLK LRCLK BCLK AUX DAC (SLAVE) DOUT BCLK LRCLK AUXBCLK AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3 DAUXDATA AUX ADC (SLAVE) LRCLK LRCLK DIN AD1838A NO. 1 (MASTER) DOUT LRCLK DOUT DOUT AUX ADC (SLAVE) BCLK AUX ADC (SLAVE) BCLK AUX DAC (SLAVE) LRCLK The cascade can be thought of as two 256-bit shift registers, one for each device. At the beginning of a sample interval, the shift registers contain the ADC results from the previous sample interval. The first shift register (Device 1) clocks data into the SHARC and also clocks in data from the second shift register (Device 2). While this is happening, the SHARC is sending DAC data to the second shift register. By the end of the sample interval, all 512 bits of ADC data in the shift registers will have been clocked into the SHARC and been replaced by DAC data, which is subsequently written to the DACs. Figure 15 shows the timing diagram for the cascade operation. AUX ADC (SLAVE) BCLK DOUT BCLK LRCLK AUXBCLK AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3 DRx RFSx RCLKx DOUT AUX ADC (SLAVE) BCLK AUX ADC (SLAVE) LRCLK The AD1838A can be cascaded to an additional AD1838A, which, in addition to six external stereo ADCs and one external stereo DAC, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade is designed to connect to a SHARC DSP and operates in a time division multiplexing (TDM) format. Figure 14 shows the connection diagram for cascade operation. The digital interface for both parts must be set to operate in Auxiliary 512 mode by programming ADC Control Register 2. AD1838A No. 1 is set as a master device by connecting the M/S pin to DGND and AD1838A No. 2 is set as a slave device by connecting the M/S to ODVDD. Both devices should be run from the same MCLK and PD/RST signals to ensure that they are synchronized. AD1838A NO. 2 (SLAVE) ASDATA ALRCLK ABCLK DAUXDATA DSDATA TCLKx DTx Figure 14. Dual AD1838A Cascade 256 BCLKs 256 BCLKs RFSx AD1838A NO. 1 DACs DTx L1 L2 DRx L1 L2 L3 L4 R1 R2 AD1838A NO. 2 DACs R3 R4 L1 L2 R3 R4 L1 L2 AD1838A NO. 1 ADCs L3 L4 R1 R2 L3 L4 R1 R2 R3 R4 R3 R4 AD1838A NO. 2 ADCs L3 L4 R1 R2 BCLK DTx MSB MSB – 1 LSB DRx MSB MSB – 1 LSB DON’ T CARE 32 ABCLKs Figure 15. Dual AD1838A Cascade Timing –22– REV. A AD1838A AUDIO INPUT 600Z 47F 5.76k + 5.76k 120pF NPO 100pF NPO 11k 3.01k OUTNx 237 11k ADCxN OP275 VREF 68pF NPO 1nF NPO 270pF NPO OP275 604 5.76k 100pF NPO 5.76k AUDIO OUTPUT 2.2nF NPO 560pF NPO OUTPx 5.62k 1nF NPO 237 OP275 1.5k 5.62k 750k 150pF NPO ADCxP VREF Figure 17. Typical DAC Output Filter Circuit Figure 16. Typical ADC Input Filter Circuit REV. A –23– AD1838A OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52-1) 1.03 0.88 0.73 13.45 13.20 SQ 12.95 2.45 MAX 39 2.20 2.00 1.80 0.25 MAX 10 6 2 27 40 SEATING PLANE 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.23 0.11 VIEW A 7 0 0.13 MIN COPLANARITY C03626–0–2/04(A) Dimensions shown in millimeters PIN 1 52 14 1 0.65 BSC 13 0.40 0.22 COMPLIANT TO JEDEC STANDARDS MS-022-AC. Revision History Location Page 2/04—Data Sheet changed from REV. 0 to REV. A. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Deleted Clock Signals section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Added AD1835A CLOCKING SCHEME section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Added Table II and Table III and renumbered following tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Changes to Auxiliary (TDM Mode) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Added Figures 7a and 8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Changes to Table VIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 –24– REV. A