Melexis EVB71122C-433-ASK-A 300 to 930mhz receiver evaluation board description Datasheet

EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Features
!
!
!
!
!
!
!
!
!
!
!
!
!
Programmable PLL synthesizer
8-channel preconfigured or fully programmable SPI mode
Double super-heterodyne receiver architecture with 2nd mixer as image rejection mixer
Reception of FSK, FM and ASK modulated signals
Low shut-down and operating currents
Build-in acceptance of input frequency variations
On-chip IF filter
Fully integrated FSK/FM demodulator
RSSI for level indication and ASK detection
2nd order low-pass data filter
Positive and negative peak detectors
Data slicer (with averaging or peak-detector adaptive threshold)
EVB programming software is available on Melexis web site
Ordering Information
Part No. (see paragraph 6)
EVB71122C-315-C
EVB71122C-433-C
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EVB71122C-868-C
EVB71122C-915-C
Note: SPI mode is default population, ABC mode according to paragraph 4.2
Application Examples
Evaluation Board Example
! General digital and analog RF receivers
at 300 to 930MHz
! Tire pressure monitoring systems (TPMS)
! Remote keyless entry (RKE)
! Low power telemetry systems
! Alarm and security systems
! Active RFID tags
! Remote controls
! Garage door openers
! Home and building automation
General Description
The MLX71122 is a multi-channel RF receiver IC based on a double-conversion super-heterodyne architecture. It is designed to receive FSK and ASK modulated RF signals either in 8 predefined frequency channels
or frequency programmable via a 3-wire serial programming interface (SPI).
The IC is designed for a variety of applications, for example in the European bands at 433MHz and 868MHz
or for the use in North America or Asia, e.g. at 315MHz, 447MHz or 915MHz.
39012 71122 01
Rev. 001
Page 1 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Document Content
1
2
Theory of Operation ...................................................................................................4
1.1
General............................................................................................................................. 4
1.2
EVB Data Overview .......................................................................................................... 4
1.3
Block Diagram .................................................................................................................. 5
1.4
Enable/Disable in ABC Mode ........................................................................................... 6
1.5
Demodulation Selection in ABC Mode.............................................................................. 6
1.6
Programming Modes ........................................................................................................ 6
1.7
Preconfigured Frequencies in ABC Mode ........................................................................ 6
Functional Description ..............................................................................................7
2.1
Frequency Planning.......................................................................................................... 7
2.2
Calculation of Counter Settings ........................................................................................ 8
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.2
2.3.3
3
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SPI Description............................................................................................................... 11
General ...................................................................................................................................... 11
Read / Write Sequences............................................................................................................ 12
Serial Programming Interface Timing ........................................................................................ 12
Register Description ................................................................................................13
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
4
Calculation of LO1 and IF1 frequency for Low Frequency Bands............................................... 8
Calculation of LO1 and IF1 frequency for High Frequency Bands.............................................. 9
Counter Setting Examples for SPI Mode ..................................................................................... 9
Counter Settings in ABC Mode – 8 Preconfigured Channels.................................................... 10
PLL Counter Ranges ................................................................................................................. 11
Register Overview .......................................................................................................... 13
Control Word R0 ........................................................................................................................ 15
Control Word R1 ........................................................................................................................ 16
Control Word R2 ........................................................................................................................ 17
Control Word R3 ........................................................................................................................ 17
Control Word R4 ........................................................................................................................ 18
Control Word R5 ........................................................................................................................ 18
Control Word R6 ........................................................................................................................ 18
Control Word R7 (Read-only Register)...................................................................................... 19
Application Circuits .................................................................................................20
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Standard FSK & ASK Circuit in SPI Mode...................................................................... 20
Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 20
Component Arrangement Top Side for SPI Mode (Averaging Data Slicer) .............................. 21
Peak Detector Data Slicer Configured for NRZ Codes ............................................................. 22
Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)........................ 23
Board Component Values List (SPI mode)................................................................................ 24
39012 71122 01
Rev. 001
Page 2 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2
4.2.1
4.2.2
4.2.3
Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode.......................... 25
Averaging Data Slicer Configured for Bi-Phase Codes............................................................. 25
Component Arrangement Top Side for ABC Mode (averaging data slicer) .............................. 26
Board Component Values List (ABC mode) .............................................................................. 27
5
Evaluation Board Layouts .......................................................................................28
6
Board Variants..........................................................................................................28
7
Package Description ................................................................................................29
7.1
Soldering Information ..................................................................................................... 29
8
Reliability Information .............................................................................................30
9
ESD Precautions ......................................................................................................30
10
Disclaimer .................................................................................................................32
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39012 71122 01
Rev. 001
Page 3 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1
Theory of Operation
1.1
General
The MLX71122 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). The PLL synthesizer consists of an integrated voltage-controlled oscillator
with external inductor, a programmable feedback divider chain, a programmable reference divider, a phasefrequency detector with a charge pump and an external loop filter.
In the receiver’s down-conversion chain, two mixers MIX1 and MIX2 are driven by the internal local oscillator
signals LO1 and LO2, respectively. The second mixer MIX2 is an image-reject mixer. As the first intermediate frequency (IF1) is very high (typically above 100 MHz), a reasonably high degree of image rejection is
provided even without using an RF front-end filter. At applications asking for very high image rejections,
cost-efficient RF front-end filtering can be realized by using a SAW filter in front of the LNA.
The receiver signal chain is setup by a low noise amplifier (LNA), two down-conversion mixers (MIX1 and
MIX2), an on-chip IF filter (IFF) as well as an IF amplifier (IFA). By choosing the required modulation via an
FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the RSSI-based
ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the demodulator.
The data slicer threshold can be generated from the mean-value of the data stream or by means of the positive and negative peak detectors (PKDET+/-).
In general the MLX71122 can be set to shut-down mode, where all receiver functions are completely turned
off, and to several other operating modes. There are two global operating modes that are selectable via the
logic level at pin SPISEL:
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8-channel preconfigured mode (ABC mode)
fully programmable mode (SPI mode).
In ABC mode the number of frequency channels is limited to eight but no microcontroller programming is
required. In this case the three lines of the serial programming interface (SPI) are used to select one of the
eight predefined frequency channels via simple 3-bit parallel programming. Pins ENRX and MODSEL are
used to enable/disable the receiver and to select FSK or ASK demodulation, respectively.
SPI mode is recommended for full programming flexibility. In this case the three lines of the SPI are configured as a standard 3-wire bus (SDEN, SDTA and SCLK). This allows changing many parameters of the
receiver, for example more operating modes, channels, frequency resolutions, gains, demodulation types,
data slicer settings and more. The pin MODSEL has no effect in this mode.
1.2
EVB Data Overview
!
!
!
!
!
!
!
! Total image rejection: > 65dB (with external
RF front-end filter)
! FSK/FM deviation range: ±10 to ±50kHz
! Spurious emission: < -70dBm
! Linear RSSI range: > 70dB
! FSK input frequency acceptance range:
170kHz (3dB)
! Crystal reference frequency: 10MHz
Input frequency ranges: 300 to 930MHz
Power supply range: 3.0 to 5.5V
Temperature range: -40 to +105°C
Shutdown current: 50nA
Operating current: 11mA (typ.)
Internal IF2: 2MHz with 230kHz 3dB bandwidth
Maximum data rate: 100kbps NRZ code,
50kbps bi-phase code
! Minimum frequency resolution: 10kHz
! Input Sensitivity: at 4 kbps NRZ, BER = 3·10
-3
Frequency
315 MHZ
433 MHz
868 MHz
915 MHz
FSK: ±20 kHz deviation
-106dBm
-104dBm
-101dBm
-101dBm
ASK
-108dBm
-108dBm
-106dBm
-106dBm
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Rev. 001
Page 4 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
28
200k
DF2
9
DF1
8
MODSEL
6
RSSI
5
MIXP
4
MIXN
3
VEEIF
2
LNAO
1
VEELNA
Block Diagram
VCCANA
1.3
OA1
ASK
LO1
IF2
FSK
IFF
LO2
SLCSEL
Fig. 1:
PKDET_
OA2
DTAO
22
10
16
20
21
30
VEEANA
19
VEEDIG
18
SW2
SLC
ENRX
17
PDN
26
BIAS
A/SCLK
7
B/SDTA
24
SPISEL
23
RO
ROI
TNK1 12 13 TNK2 15
CP
MFO
14
LF
11
VCCVCO
VEEVCO
LF
Control
Logic
RBIAS
VCO
25
PDP
1M
R
counter
C/SDEN
PFD
27
PKDET+
FSK
DEMOD
LO2DIV
N/A
counter
DFO
SW1
IFA
1M
LNA
MIX2
VCCDIG
31
IF1
200k
MIX1
LNAI
29
200k
32
MLX71122 block diagram
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The MLX71122 receiver IC consists of the following building blocks:
•
•
•
•
•
•
•
•
•
•
•
•
PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2,
parts of the PLL SYNTH are the voltage-controlled oscillator (VCO), the feedback dividers N/A and R,
the phase-frequency detector (PFD), the charge pump (CP) and the crystal-based reference oscillator
(RO)
Low-noise amplifier (LNA) for high-sensitivity RF signal reception
First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
IF Filter (IFF) with a 2MHz center frequency and a 230kHz 3dB bandwidth
IF amplifier (IFA) to provide a large amount of voltage gain and an RSSI signal output
FSK demodulator (FSK DEMOD)
Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
Positive (PKDET+) and negative (PKDET-) peak detectors
Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detector data slicer
Control logic with 3-wire bus serial programming interface (SPI)
Biasing circuit with modes control
For more detailed information, please refer to the latest MLX71122 data sheet revision.
39012 71122 01
Rev. 001
Page 5 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
1.4
Enable/Disable in ABC Mode
ENRX
Description
0
Shutdown mode
1
Receive mode
Pin ENRX is pulled down internally. Device is in shutdown by default, after power supply on.
If ENRX = 0 and SPISEL = 1 then operating modes according to OPMODE bit (refer to control word R0).
If ENRX = 1 then OPMODE bit has no effect (hardwired receive mode).
1.5
Demodulation Selection in ABC Mode
MODSEL
Description
0
FSK demodulation
1
ASK demodulation
Pin MODSEL has no effect in SPI mode (SPISEL = 1). We recommend connecting it to ground to avoid a
floating CMOS gate.
1.6
SPISEL
0
1
1.7
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Programming Modes
Description
ABC mode (8 channels preconfigured)
SPI mode (programming via 3-wire bus)
Preconfigured Frequencies in ABC Mode
A
B
C
Receive Frequency
0
0
FSK1: 369.5 MHz
0
1
0
FSK5: 388.3 MHz
1
0
0
FSK2: 371.1 MHz
1
1
0
FSK4: 376.9 MHz
0
0
1
FSK3: 375.3 MHz
0
1
1
FSK7: 394.3 MHz
1
0
1
FSK6: 391.5 MHz
1
1
1
FSK8: 395.9 MHz
0
As all pins, pins A, B, and C are equipped with ESD protection diodes that are tied to VCC and to VEE.
Therefore these pins should not be directly connected to positive supply (a logic “1”) before the supply voltage is applied to the IC. Otherwise the IC will be supplied through these control lines and it may enter into an
unpredictable mode. In case the user wants to apply a positive supply voltage to these pins before the supply voltage is applied to the IC, a protection resistor should be inserted in each control line.
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Rev. 001
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EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2
Functional Description
2.1
Frequency Planning
Because of the double conversion architecture that employs two mixers and two IF signals, there are four
different combinations for injecting the LO1 and LO2 signals:
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•
•
•
receiving at fRF(high-high)
receiving at fRF(high-low)
receiving at fRF(low-high)
receiving at fRF(low-low)
LO1 high side and LO2 high side:
LO1 high side and LO2 low side:
LO1 low side and LO2 high side:
LO1 low side and LO2 low side:
As a result, four different radio frequencies (RFs) could yield one and the same second IF (IF2). Fig. 2
shows this for the case of receiving at fRF(high-high). In the example of Fig. 2, the image signals at fRF(lowhigh) and fRF(low-low) are suppressed by the bandpass characteristic provided by the RF front-end. The
bandpass shape can be achieved either with a SAW filter (featuring just a couple of MHz bandwidth), or by
the tank circuits at the LNA input and output (this typically yields 30 to 60MHz bandwidth). In any case, the
high value of the first IF (IF1) helps to suppress the image signals at fRF(low-high) and fRF(low-low).
The two remaining signals at IF1 resulting from fRF(high-high) and fRF(high-low) are entering the second
mixer MIX2. This mixer features image rejection with so-called single-sideband (SSB) selection. This means
either the upper or lower sideband of IF1 can be selected. In the example of Fig. 2, LO2 high-side injection
has been chosen to select the IF2 signal resulting from fRF(high-high).
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f LO2
f RF
Fig. 2:
f LO2
f RF
f LO1
f RF
f RF
The four receiving frequencies in a double conversion superhet receiver
It can be seen from the block diagram of Fig. 1 that there is a fixed relationship between the LO1 signal frequency fLO1 and the LO2 signal frequency fLO2.
LO2DIV = N LO2 =
f LO1
f LO2
(1)
The LO1 signal frequency fLO1 is directly synthesized from the crystal reference oscillator frequency fRO by
means of an integer-N PLL synthesizer. The PLL consists of a dual-modulus prescaler (P/P+1), a program
counter N and a swallow counter A.
f LO1 =
39012 71122 01
Rev. 001
f RO
(N ⋅ P + A) = f PFD (N ⋅ P + A) = f PFD ⋅ N tot
R
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(2)
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Due to the double superhet receiver architecture, the channel frequency step size fCH is not equal to the
phase-frequency detector (PFD) frequency fPFD. For high-side injection, the channel step size fCH is given by:
f CH =
f RO N LO2 − 1
N −1
= f PFD LO2
R N LO2
N LO2
(3)
While the following equation is valid for low-side injection:
f CH =
2.2
f RO N LO2 + 1
N +1
= f PFD LO2
R N LO2
N LO2
(4)
Calculation of Counter Settings
Frequency planning and the selection of the MLX71122’s PLL counter settings are straightforward and can
be laid out on the following procedure.
Usually the receive frequency fRF and the channel step size fCH are given by system requirements. The N
and A counter settings can be derived from Ntot or fLO1 and fPFD by using the following equations.
N = floor(
2.2.1
N tot
N
) = floor( tot ) ; A = N tot − N ⋅ P = N tot − N ⋅ 32
P
32
(5)
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Calculation of LO1 and IF1 frequency for Low Frequency Bands
High-high injection must be used for the low frequency bands. First of all choose a PFD frequency fPFD
according to below table. The R counter values are valid for a 10MHz crystal reference frequency fRO. The
PFD frequency is given by fPFD = fRO /R.
Injection Type
fCH [kHz]
fPFD [kHz]
R
10
13.3
750
12.5
16.7
600
20
26.7
375
25
33.3
300
50
66.7
150
h-h
100
133.3
75
h-h
250
333.3
30
h-h
h-h
h-h
h-h
h-h
The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the
NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLO2 = 4 (or 8) and P =32.
f LO1 =
f IF1 =
N LO2
(f RF − f IF2 )
N LO2 − 1
f RF − N LO2 f IF2
N LO2 − 1
f LO1 =
4
(f RF − 2MHz)
3
f IF1 =
f RF − 8MHz
3
(6)
(7)
Finally N and A can be calculated with formula (5).
39012 71122 01
Rev. 001
Page 8 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.2
Calculation of LO1 and IF1 frequency for High Frequency Bands
Typical ISM band operating frequencies like 868.3 and 915MHz can be covered without changing the crystal
nor the VCO inductor.
Low-low injection should be used for the high frequency bands. First of all choose a PFD frequency fPFD
according to below table. The R counter values are valid for a 10MHz crystal reference. The PFD frequency
is given by fPFD = fRO /R.
Injection Type
fCH [kHz]
fPFD [kHz]
R
l-l
20
16
625
l-l
25
20
500
l-l
50
40
250
l-l
100
80
125
l-l
250
200
50
l-l
500
400
25
The second step is to calculate the missing parameters fLO1, fIF1, Ntot, N and A. While the second IF (fIF2), the
NLO2 divider ratio and the prescaler divider ratio P are bound to fIF2 = 2MHz, NLo2 = 4 (or 8) and P =32.
f LO1 =
N LO2
(f RF − f IF2 )
N LO2 + 1
f LO1 =
4
(f RF − 2MHz)
5
f IF1 =
f RF + 8MHz
5
(8)
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f IF1 =
f RF + N LO2f IF2
N LO2 + 1
(9)
Finally N and A can be calculated with formula (5).
2.2.3
Counter Setting Examples for SPI Mode
To provide some examples, the following table shows some counter settings for the reception of the wellknown ISM and SRD frequency bands. The channel spacing is assumed to be fCH = 100kHz. In below table
all frequency units are in MHz.
Inj
fRF
fIF1
fLO1
Ntot
N
P
A
fPFD
R
fREF
fLO2
fIF2
h-h
300
97.3
397.3
2980
93
32
4
0.133
75
10
99.3
2
h-h
315
102.3
417.3
3130
97
32
26
0.133
75
10
104.3
2
h-h
434
142
576
4320
135
32
0
0.133
75
10
144
2
h-h
470
154
624
4680
146
32
8
0.133
75
10
156
2
l-l
850
171.6
678.4
8480
256
32
0
0.08
125
10
169.6
2
l-l
868
175.2
692.8
8660
270
32
20
0.08
125
10
173.2
2
l-l
915
184.6
730.4
9130
285
32
10
0.08
125
10
182.6
2
l-l
930
187.6
742.4
9280
290
32
0
0.08
125
10
185.6
2
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Rev. 001
Page 9 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.4
Counter Settings in ABC Mode – 8 Preconfigured Channels
In ABC mode (SPISEL=0), the counter settings are hard-wired. In below table all frequency units are in MHz.
FSK
fRF
fIF1
fLO1
Ntot
N
P
A
fPFD
R
fREF
fLO2
fIF2
1
369.5
120.5
490.0
3675
114
32
27
0.133
75
10
122.5
2
2
371.1
121.0
492.0
3691
115
32
11
0.133
75
10
123.0
2
3
375.3
122.4
497.7
3733
116
32
21
0.133
75
10
124.4
2
4
376.9
123.0
499.9
3749
117
32
5
0.133
75
10
125.0
2
5
388.3
126.8
515.1
3863
120
32
23
0.133
75
10
128.8
2
6
391.5
127.8
519.3
3895
121
32
23
0.133
75
10
129.8
2
7
394.3
128.8
523.1
3923
122
32
19
0.133
75
10
130.8
2
8
395.9
129.3
525.2
3939
123
32
3
0.133
75
10
131.3
2
List of Mathematical Acronyms
A
f FB
floor (x)
f PFD
f RO
= fR
R
f RO
f VCO
N tot = N ⋅ P + A
N
N LO2
P
R
39012 71122 01
Rev. 001
divider ratio of the swallow counter (part of feedback divider)
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frequency at the feedback divider output
The floor function gives the largest integer less than or equal to x.
For example, floor(5.4) gives 5, floor(-6.3) gives -7.
PFD frequency in locked state
reference frequency of the PLL
frequency of the crystal reference oscillator
frequency of the VCO (equals the LO1 signal of the first mixer)
total divider ratio of the PLL feedback path
divider ratio of the program counter (part of feedback divider)
LO2DIV divider ratio, to derive the LO2 signal from LO1 (N1 = 4 or 8)
divider ratio of the prescaler (part of feedback divider)
divider ratio of the reference divider R
Page 10 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.2.5
PLL Counter Ranges
In order to cover the frequency range of about 300 to 930MHz the following counter values are implemented
in the receiver:
PLL Counter Ranges
A
N
R
P
0 to 31 (5bit)
3 to 2047 (11bit)
3 to 2047 (11bit)
32
Therefore the minimum and maximum divider ratios of the PLL feedback divider are given by:
N totmin = 32 ⋅ 32 = 1024
2.3
2.3.1
N totmax = 2047 ⋅ 32 + 31 = 65535
SPI Description
General
Serial programming interface (SPI) mode can be activated by choosing SPISEL = 1 (e.g. at positive supply
voltage VCC). In this mode, the input pins 17, 18 and 19 are used as a 3-wire unidirectional serial bus interface (SDEN, SDTA, SCLK). The internal latches contain all user programmable variables including counter
settings, mode bits etc.
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In addition the MFO pin can be programmed as an output (see section 4.1.4) in order to read data from the
internal latches and it can be used as an output for different test modes as well.
At each rising edge of the SCLK signal, the logic value at the SDTA terminal is written into a shift register.
The programming information is taken over into internal latches with the rising edge of SDEN. Additional
leading bits are ignored, only the last bits are serially clocked into the shift register. A normal write operation
shifts 16 bits into the SPI, a normal read operation shifts 4 bits into the SPI and reads additional 12 bits from
the MFO pin. If less than 12 data bits are shifted into SDTA during the write operation then the control register may contain invalid information.
In general a control word has the following format. Bit 0 is the Read/Write bit that determines whether it is a
read (R/W = 1) or a write (R/W = 0) sequence. The R/W bit is preceding the latch address and the
corresponding data bits.
Control Word Format
MSB
LSB
Data
D11
D10
D9
D8
D7
D6
MSB
LSB
Latch Address
D5
D4
D3
D2
D1
D0
A2
A2
A0
Bit 0
Mode
R/W
There are two control word formats for read and for write operation. Data bits are only needed in write mode.
Read operations require only a latch address and a R/W bit.
Due to the static CMOS design, the serial interface consumes virtually no current. The SPI is a fully separate
building block and can therefore be programmed in every operational mode.
39012 71122 01
Rev. 001
Page 11 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
2.3.2
Read / Write Sequences
Fig. 6
Y
R
A
N
I
M
I
L
E
R
P
Fig. 7
2.3.3
Typical write sequence diagram
Typical read sequence diagram
Serial Programming Interface Timing
SDEN
t CWH
t CR
tEW
tEH
t CWL
t CF
SCLK
t CS t CH
t ES
t DES
t DSO
SDTA
MFO
Fig. 8
39012 71122 01
Rev. 001
SPI timing diagram
Page 12 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3
Register Description
The following tables are to describe the functionality of the registers.
Sec. 4.1 provides a register overview with all the control words R0 to R7. The subsequent sections. 4.1.1 to
4.1.8 show the content of the control words in more detail.
Programming the registers requires SPI mode (SPISEL = 1). Default settings are for ABC mode.
3.1
Register Overview
DATA
CONTROL
WORD
MSB
10
9
8
7
6
5
4
3
2
1
0
MSB
default
1
0
1
1
1
0
0
0
1
0
0
0
0
R0
DTAPOL
SLCSEL
SSBSEL
DEMGAIN
MIX2GAIN
MIX1GAIN
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
default
1
0
0
0
1
0
1
1
0
1
0
0
R1
PRESCUR
VCOBUF
VCOCUR
VCORANGE
LDMODE
LDERR
PFDPOL
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
default
1
1
1
0
1
1
1
0
1
1
0
0
0
OPMODE
[1:0]
LNAGAIN
[1 : 0 ]
11
IFFGAIN
[ 1 :0 ]
Bit No.
SHOWLD
LSB
LATCH
ADDRESS
CPCUR
[1:0]
0
8
7
6
5
4
3
2
1
0
MSB
default
0
1
0
0
0
0
0
0
0
0
0
0
0
AGCEN
LO2DIV
N
[ 10 : 7 ]
9
AGCDEL
[1:0]
1
1
LSB
0
read/
write
10
MFO
[3:0]
0
LSB
read/
write
A
[4:0]
LDTIME
[ 1 :0 ]
N
[6:0]
MSB
11
Page 13 of 32
0
read/
write
Bit No.
39012 71122 01
Rev. 001
0
Y
R
A
N
I
M
I
L
E
R
P
R2
R3
LSB
LSB
1
1
read/
write
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
DATA
CONTROL
WORD
MSB
11
10
9
8
7
6
5
4
3
2
1
0
MSB
default
0
0
0
0
0
1
0
0
1
0
1
1
1
R4
AGCMODE
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
default
0
0
1
0
1
0
0
1
1
0
1
1
1
R5
Bit No.
11
10
9
8
7
6
5
4
3
2
1
0
MSB
default
1
0
1
0
0
1
1
0
1
1
0
0
1
IFFTUNE
IFFHLT
9
8
11
∗
RIFF
[ 10 : 0 ]
6
5
0
LSB
0
1
read/
write
IFFPRES
[7:0]
7
4
LSB
1
0
read/
write
3
IFFVAL
[7:0]
IFFSTATE
[ 1 :0 ]
R7
0
read/
write
2
1
0
MSB
1
RSSIH
default
10
LDRSSIL∗
Bit No.
LSB
Y
R
A
N
I
M
I
L
E
R
P
ROCUR
[ 1 :0 ]
R6
Note:
R
[ 10 : 0 ]
Bit No.
MODSEL
LSB
LATCH
ADDRESS
1
LSB
1
readonly
depends on bit 11 in R4, 0 = RSSIL, 1 = LD
39012 71122 01
Rev. 001
Page 14 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.1
Control Word R0
Name
Bits
Description
operation mode
OPMODE
LNAGAIN
[1:0]
[3:2]
00
01
10
11
00
01
10
11
#default
shutdown
receive mode
reference oscillator & BIAS only
synthesizer only
LNA gain
(-18dB)
(-4dB)
(0dB)
(+2dB)
lowest gain
low gain
high gain
highest gain
#default
gain values are relative to gain at default
1st Mixer gain
MIX1GAIN
[4]
0
1
high gain
low gain
#default
(14dB)
(0dB)
2nd Mixer gain
MIX2GAIN
[5]
0
1
high gain
low gain
#default
(9dB)
(-2dB)
Y
R
A
N
I
M
I
L
E
R
P
intermediate frequency filter gain
IFFGAIN
[7:6]
00
01
10
11
lowest gain
low gain
high gain
highest gain
(-14dB)
(-6dB)
(0dB)
(+6dB)
#default
demodulator gain
DEMGAIN
[8]
0
1
low gain
high gain
(~ 4mV/kHz)
(~ 15mV/kHz)
#default
single side band selection
SSBSEL
[9]
0
1
upper side band
lower side band
LO2 low-side inj. (IF1 = LO2 + IF2)
LO2 high-side inj. (IF1 = LO2 – IF2)
#default
Internal IF2 = 2MHz
slicer mode select
SLCSEL
[9]
0
1
averaging Data Slicer mode
peak detector Data Slicer mode
#default
data output polarity OA2
0
DTAPOL
[11]
inverted
‘1’ for space at ASK or fmin at FSK, ‘0’ for mark at ASK or fmax at FSK
1
#default
normal
‘0’ for space at ASK or fmin at FSK, ‘1’ for mark at ASK or fmax at FSK
39012 71122 01
Rev. 001
Page 15 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.2
Control Word R1
Name
Bits
Description
charge pump current setting
CPCUR
[1:0]
PFDPOL
[2]
00
01
10
11
#default
100µA
400µA
400µA static down
400µA static up
PFD output polarity
0
1
negative
positive
#default
lock detector time error
LDERR
[3]
0
1
#default
15ns
30ns
lock detection time
LDTIME
[5:4]
00
01
10
11
2/fR
4/fR
8/fR
16/fR
#default
minimum time span before lock in
fR is the reference oscillator frequency fRO divided by R, see section 4.1.5 (R4)
Y
R
A
N
I
M
I
L
E
R
P
lock detector mode
LDMODE
[6]
0
1
check lock condition permanently
check lock condition until 1st lock in
#default
VCO range
VCORANGE
[7]
0
1
3V supply
5V supply
#default
VCO range setting for different VCCs.
VCO core current
VCOCUR
[8]
0
1
#default
450µA
520µA
VCO buffer current
VCOBUF
[9]
0
1
#default
900µA
1040µA
prescaler 32/33 reference current
PRESCUR
[10]
0
1
#default
20µA
30µA
30µA may be used for fRF = 868/915MHz
function of LDRSSIL bit
SHOWLD
[11]
0
1
RSSIL (RSSI low flag)
LD (lock detection flag)
#default
select output data of LDRSSIL, see section 4.1.8 (R7)
39012 71122 01
Rev. 001
Page 16 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.3
Control Word R2
Name
Bits
Description
swallow counter value
A
[4:0]
01100
#default
value is 12
swallow counter range: 0 to 31
program counter value (bits 0 – 6)
N
[11:5]
000 0111 0111 N value is 119
#default
N counter range: 3 to 2047
3.1.4
Control Word R3
program counter range (bits 7 – 10)
N
[3:0]
000 0111 0111 N value is 119
#default
N counter range: 3 to 2047
LO2 divider ratio
LO2DIV
[4]
AGCEN
[5]
0
1
#default
divide by 4
divide by 8
Y
R
A
N
I
M
I
L
E
R
P
AGC enable mode
0
1
#default
disabled
enabled
AGC delay settings
AGCDEL
[7:6]
00
01
10
11
#default
no delay
3/fIFF
15/fIFF
31/fIFF
fIFF is the reference oscillator frequency fRO divided by RIFF, see section 4.1.6 (R6)
multi functional output
MFO
39012 71122 01
Rev. 001
[11:8]
0000
0001
0010
0011
0100
0101
1000
MFO is in Z state
MFO is SPI read-out
MFO = 0
MFO = 1
MFO is analog RO output
MFO is IFF output
MFO is lock detector output
Page 17 of 32
#default
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.5
Control Word R4
Name
Bits
Description
reference divider range
R
[10:0]
#default
000 0100 1011 value is 75
R counter range: 3 to 2047
AGC delay mode
AGCMODE
0
1
[11]
gain decrease and increase with delay
gain decrease without delay, gain increase with delay
#default
selects AGC delay mode in combination with AGCDEL bits, see section 4.1.4 (R3)
3.1.6
Control Word R5
Name
Bits
Description
reference divider value for IFF adjustment
RIFF
[10:0]
#default
010 1001 1011 value is 667
IFF counter range: 4 to 2047
Y
R
A
N
I
M
I
L
E
R
P
demodulation selection
MODSEL
[11]
0
1
#default
FSK demodulation
ASK demodulation
selects modulation type when chip is controlled via SPI mode
3.1.7
Control Word R6
Name
Bits
IFFPRES
[7:0]
Description
IFF preset value
0110 1100
#default
value is 108
IFF DAC preset at start of automatic tuning
IFF halt
IFFHLT
[8]
0
1
#default
auto tuning running
auto tuning halted
suspends IFF automatic tuning
IFF tuning
IFFTUNE
[9]
0
1
disable and load DAC with IFFPRES
enable
00
01
10
11
85µA
170µA
270µA
355µA
#default
reference Oscillator core current
ROCUR
39012 71122 01
Rev. 001
[11:10]
#default
Page 18 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
3.1.8
Control Word R7 (Read-only Register)
Name
Bits
Description
IFF adjustment value
IFFVAL
[7:0]
see also IFFPRES in section 4.1.7 (R6)
IFF automatic tuning state
IFFSTATE
[9:8]
00
01
10
11
filter tuned or auto-tuning disabled
tuning up the filter frequency
tuning down the filter frequency
master oscillator of filter deactivated
lock detector or RSSI low flag
LDRSSIL
[10]
0
1
PLL not locked or RSSI value in lower region
PLL locked or RSSI value above lower region
depends on SHOWLD in section 4.1.2 (R1)
RSSI high flag
RSSIH
[11]
0
1
RSSI value below upper region
RSSI value in upper region
Y
R
A
N
I
M
I
L
E
R
P
39012 71122 01
Rev. 001
Page 19 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4
Application Circuits
4.1
Standard FSK & ASK Circuit in SPI Mode
DTAO
RS1
VCC
1 2
MFO
GND
SCLK
SDTA
SDEN
RS2
1 2 3
1 2 3 4 5
MFO
Averaging Data Slicer Configured for Bi-Phase Codes
RB0
CB3
XTAL
RS3
DFO
4.1.1
C/SDEN 17
B/SDTA 18
A/SCLK 19
LF 15
27 DFO
VCCVCO 14
28 DF1
TNK2 13
MLX71122
29 DF2
TNK1 12
30 VEEANA
SPISEL
1
MIXP
C10
MIXN
32 SLC
CF2
RF
L0
CF1
CB2
RBS
RBIAS 10
VEEIF
C2
VEEVCO 11
31 LNAI
VCCANA
L2
LNAO
1
3
SAWFIL
4
6
VEELNA
50
26 PDN
2
3
4
5
6
7
MODSEL
9
RSSI
GND VCC
VCC
C9
ENRX 16
RSSI
C8
C1
VEEDIG 20
Y
R
A
N
I
M
I
L
E
R
P
25 PDP
L1
VCCDIG 21
MFO 23
DTAO 22
ROI 24
CX
8
12
1 2
L3
C5
C4
C6
C7
CB0
CB1
Fig. 6:
Application circuit for SPI Mode (averaging data slicer option)
Note
•
EVB71122 default population is SPI mode
39012 71122 01
Rev. 001
Page 20 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.2
Component Arrangement Top Side for SPI Mode (Averaging Data Slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
1
GND
1
VCC
MFO
1
A
GND
RS1
SCLK
XTAL
3
Melexis
RS2
SDTA
C
SDEN
RS3
Y
R
A
N
I
M
I
L
E
R
P
ENRX
RF
CB2
L0
C8
CF2
L1
CF1
RF_input
CB3
C1
RF_input
CX
1
RB0
B
MODSEL
0
RBS
C7
C6
C5
C10
C2
FSK/ASK
L2
EVB71122_002
CB1
1
VCC
1
CB0
0
L3
C4
GND
GND RSSI
SPI mode selected
39012 71122 01
Rev. 001
Page 21 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
DTAO
RS1
VCC
1 2
MFO
GND
SCLK
SDTA
SDEN
RS2
1 2 3
1 2 3 4 5
MFO
Peak Detector Data Slicer Configured for NRZ Codes
RB0
CB3
XTAL
RS3
DFO
4.1.3
C/SDEN 17
B/SDTA 18
A/SCLK 19
VEEDIG 20
VCCDIG 21
MFO 23
LF 15
CF2
27 DFO
VCCVCO 14
28 DF1
TNK2 13
MLX71122
29 DF2
TNK1 12
30 VEEANA
MIXN
MIXP
SPISEL
1
VEEIF
SLC
VCCANA
C2
L0
CF1
CB2
RBS
RBIAS 10
31 LNAI
LNAO
L2
VEELNA
1
3
SAWFIL
4
6
VEEVCO 11
RF
2
3
4
5
6
7
MODSEL
9
RSSI
GND VCC
VCC
C9
50
ENRX 16
26 PDN
RSSI
C8
C1
25 PDP
Y
R
A
N
I
M
I
L
E
R
P
C12
L1
DTAO 22
C11
ROI 24
CX
8
12
1 2
L3
C5
C4
C6
C7
CB0
CB1
Fig. 7:
Application circuit for SPI Mode (peak detector option)
Note
•
EVB71122 default population is SPI mode
39012 71122 01
Rev. 001
Page 22 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.4
Component Arrangement Top Side for SPI Mode (Peak Detector Data Slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
1
GND
1
VCC
MFO
1
A
GND
RS1
SCLK
XTAL
3
Melexis
RF_input
CX
1
RB0
B
CB3
RS2
SDTA
C
SDEN
RS3
Y
R
A
N
I
M
I
L
E
R
P
ENRX
RF
C12
CB2
L0
C8
CF2
L1
CF1
C1
C11
RF_input
MODSEL
0
RBS
C7
C6
C5
C2
FSK/ASK
L2
EVB71122_002
CB1
1
VCC
1
CB0
0
L3
C4
GND
GND RSSI
SPI mode selected
39012 71122 01
Rev. 001
Page 23 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.1.5
Board Component Values List (SPI mode)
Below table is for all application circuits show in Figures 6 and 7
Part
Size
Value @
315 MHz
Value @
433.9 MHz
Value @
868.3 MHz
Value @
915 MHz
Tol.
C1
0603
NIP
NIP
3.3 pF
NIP
±5%
matching capacitor
C2
0603
NIP
NIP
NIP
NIP
±5%
matching capacitor
C4
0603
4.7 pF
3.3 pF
2.7 pF
2.2 pF
±5%
LNA output tank capacitor
C5
0603
100 pF
100 pF
100 pF
100 pF
±5%
MIX1 negative input matching
capacitor
C6
0603
100 pF
100 pF
100 pF
100 pF
±5%
MIX1 negative input matching
capacitor
C7
0603
1 nF
1 nF
1 nF
1 nF
±10%
RSSI output low pass capacitor,
this value for data rates 4 kbps
NRZ
C8
0603
330 pF
330 pF
330 pF
330 pF
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps
NRZ
C9
0603
150 pF
150 pF
150 pF
150 pF
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps
NRZ
C10
0603
33 nF
33 nF
33 nF
±10%
data slicer capacitor
C11
0603
C12
0603
CB0
1210
10 μF
10 μF
CB1
0603
470 pF
CB2
0603
33 nF
CB3
0603
CF1
33 nF
not required in Figure 7
Description
Y
R
A
N
I
M
I
L
E
R
P
33 nF
±10%
peak detector positive filtering
capacitor
33 nF
±10%
peak detector negative filtering
capacitor
10 μF
10 μF
±10%
decoupling capacitor,
low-noise power supply recommended
470 pF
470 pF
470 pF
±10%
decoupling capacitor
33 nF
33 nF
33 nF
±10%
decoupling capacitor
33 nF
33 nF
33 nF
33 nF
±10%
decoupling capacitor
0603
2.2 nF
2.2 nF
2.2 nF
2.2 nF
±5%
loop filter capacitor
CF2
0603
220 pF
220 pF
220 pF
220 pF
±5%
loop filter capacitor
CX
0603
27 pF
27 pF
27 pF
27 pF
±5%
crystal series capacitor
RB0
0603
10 Ω
10 Ω
10 Ω
10 Ω
±5%
protection resistor
RF
0603
27 kΩ
27 kΩ
47 kΩ
47 kΩ
±5%
loop filter resistor
RBS
0603
RS1…RS3
L0
0603
33 nF
33 nF
33 nF
not required in Figures 6
33 nF
33 nF
33 nF
not required in Figures 6
30 kΩ
30 kΩ
30 kΩ
30 kΩ
±2%
reference bias resistor
10 kΩ
10 kΩ
10 kΩ
10 kΩ
±5%
protection resistor
33 nH
15 nH
8.2 nH
8.2 nH
±5%
VCO tank inductor
L1
0603
0Ω
56 nH
22 nH
0Ω
±5%
matching inductor
L2
0603
82 nH
82 nH
22 nH
8.2 nH
±5%
matching inductor
L3
0603
33 nH
22 nH
5.6 nH
5.6 nH
±5%
LNA output tank inductor
XTAL
SMD
5x3.2
SAW
FIL
SMD
3x3
Note:
10.00000 MHz / ±20ppm cal., ±30ppm temp.
SAFDC315MS
M0T00
(315 MHz)
SAFCC433MB
L0X00
(433.92 MHz)
SAFCC868MS SAFCH915MA
L0N00
L0X00
(915 MHz)
(868.3 MHz)
fundamental-mode crystal
low-loss SAW filter from Murata
or equivalent part
- NIP – not in place, may be used optionally
39012 71122 01
Rev. 001
Page 24 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Standard FSK & ASK circuit in 8-Channel Preconfigured (ABC) Mode
Averaging Data Slicer Configured for Bi-Phase Codes
DFO
DTAO
1 2
1 2
A
12 3
B
12 3
VCC
4.2.1
VCC
4.2
RB0
CB3
XTAL
ENRX
C
12 3
CX
B/SDTA 18
C/SDEN 17
A/SCLK 19
VEEDIG 20
26 PDN
LF 15
27 DFO
VCCVCO 14
28 DF1
TNK2 13
MLX71122
29 DF2
TNK1 12
30 VEEANA
3
SPISEL
2
MIXP
1
VEEIF
C10
MIXN
32 SLC
LNAO
C2
RF
L0
CF1
12 3
CB2
RBS
RBIAS 10
31 LNAI
VCCANA
C3
VEELNA
L1
VEEVCO 11
CF2
4
5
6
7
MODSEL
9
GND VCC
RSSI
VCC
C9
ENRX 16
RSSI
C8
50
MODSEL
Y
R
A
N
I
M
I
L
E
R
P
25 PDP
C1
VCCDIG 21
DTAO 22
ROI 24
MFO 23
12 3
8
1 2
1 2
L3
C5
C6
C4
C7
CB0
CB1
Fig. 8:
Application circuit for ABC Mode
Note
•
ABC mode population can be easily modified from default SPI mode population by changing the connection at SPISEL from VCC to ground.
39012 71122 01
Rev. 001
Page 25 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2.2
Component Arrangement Top Side for ABC Mode (averaging data slicer)
Board size is 49mm x 35.6mm
DFO GND MFO GND DTAO
Melexis
1
GND
1
VCC
MFO
1
1
A
1
B
GND
XTAL
3
SCLK
SDEN
C
1
CB3
Y
R
A
N
I
M
I
L
E
R
P
RF
C2
RBS
0
1
ENRX
1
MODSEL
CB2
L0
C8
CF2
L1
CF1
RF_input
C1
RF_input
CX
1
RB0
SDTA
0
C7
C6
C5
C10
FSK/ASK
C3
EVB71122_002
CB1
1
VCC
1
CB0
L3
C4
GND
GND RSSI
ABC mode selected
39012 71122 01
Rev. 001
Page 26 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
4.2.3
Board Component Values List (ABC mode)
Below table is for all application circuits show in Figures 8
Part
Size
Value @
369 MHz to 396 MHz
Tol.
C1
0603
NIP
±5%
matching capacitor
C2
0603
NIP
±5%
matching capacitor
C3
0603
100 pF
±5%
LNA input filtering capacitor
C4
0603
3.3 pF
±5%
LNA output tank capacitor
C5
0603
100 pF
±5%
MIX1 negative input matching capacitor
C6
0603
100 pF
±5%
MIX1 negative input matching capacitor
C7
0603
1 nF
±10%
RSSI output low pass capacitor,
this value for data rates 4 kbps NRZ
C8
0603
330 pF
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps NRZ
C9
0603
150 pF
±10%
data low-pass filter capacitor,
this value for data rates 4 kbps NRZ
C10
0603
33 nF
±10%
data slicer capacitor
Description
CB0
1210
10 μF
±10%
decoupling capacitor,
low-noise power supply recommended
CB1
0603
470 pF
±10%
decoupling capacitor
CB2
0603
33 nF
±10%
decoupling capacitor
CB3
0603
CF1
0603
CF2
0603
CX
0603
RB0
0603
RF
0603
RBS
0603
RS1…RS3
0603
L0
0603
L1
0603
L3
0603
XTAL
SMD
5x3.2
Note:
Y
R
A
N
I
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L
E
R
P
33 nF
±10%
decoupling capacitor
2.2 nF
±5%
loop filter capacitor
220 pF
±5%
loop filter capacitor
27 pF
±5%
crystal series capacitor
10 Ω
±5%
protection resistor
27 kΩ
±5%
loop filter resistor
30 kΩ
±2%
reference bias resistor
10 kΩ
±5%
protection resistor
18 nH
±5%
VCO tank inductor
39 nH
±5%
matching inductor
27 nH
±5%
LNA output tank inductor
10.00000 MHz / ±20ppm cal., ±30ppm temp.
fundamental-mode crystal
- NIP – not in place, may be used optionally
39012 71122 01
Rev. 001
Page 27 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Evaluation Board Layouts
VCC
C
B
Melexis
PCB top view
6
Y
R
A
N
I
M
I
L
E
R
P
EVB71122_002
DFO GND MFO GND DTAO
GND
GND RSSI
VCC
A
FSK/ASK
GND
MODSEL
ENRX
SDEN
Board layout data in Gerber format is available, board size is 35.6mm x 49mm.
SCLK
GND
MFO
•
SDTA
5
PCB bottom view
Board Variants
Type
EVB71122
Regional Code
Frequency/MHz
Modulation
Board Execution
C
world wide
–315
–FSK
–A
antenna version
A
Europe, Asia
–433
–ASK
–C
connector version
B
USA, Canada –868
–FM
–915
Note:
39012 71122 01
Rev. 001
possible combinations
Page 28 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
7
Package Description
•
The device MLX71122 is RoHS compliant.
D
A3
24
17
25
16
32
9
E
A1
8
b
1
e
A
Y
R
A
N
I
M
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L
E
R
P
exp osed pad
E2
L
D2
The “exposed pad” is not connected to internal ground,
it should not be connected to the PCB.
Fig 12:
32L QFN 5x5 Quad
all Dimension in mm
min
max
D
E
D2
E2
A
A1
A3
L
e
b
4.75
5.25
4.75
5.25
3.00
3.25
3.00
3.25
0.80
1.00
0
0.05
0.20
0.3
0.5
0.50
0.18
0.30
0.118
0.128
0.118
0.128
0.0315
0.0393
0
0.002
0.0079
0.0118
0.0197
0.0197
0.0071
0.0118
all Dimension in inch
min
max
7.1
0.187
0.207
0.187
0.207
Soldering Information
•
The device MLX71122 is qualified for MSL3 with soldering peak temperature 260 deg C
according to JEDEC J-STD-20
39012 71122 01
Rev. 001
Page 29 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
8
Reliability Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture
sensitivity level, as defined in this specification, according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices (classification
reflow profiles according to table 5-2)”
EIA/JEDEC JESD22-A113
“Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according
to table 2)”
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EN60749-20
“Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering heat”
EIA/JEDEC JESD22-B106 and EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Iron Soldering THD’s (Through Hole Devices)
Y
R
A
N
I
M
I
L
E
R
P
EN60749-15
“Resistance to soldering temperature for through-hole mounted devices”
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21
“Solderability”
For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be
agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more information on qualification of RoHS compliant products (RoHS = European directive on the Restriction Of the
Use of Certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality_leadfree.aspx
9
ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
39012 71122 01
Rev. 001
Page 30 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
Your Notes
Y
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39012 71122 01
Rev. 001
Page 31 of 32
EVB Description
Sept/06
EVB71122
300 to 930MHz Receiver
Evaluation Board Description
10
Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis
reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product
is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or
life-sustaining equipment are specifically not recommended without additional processing by Melexis for
each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data
herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of
technical or other services.
© 2006 Melexis NV. All rights reserved.
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For the latest version of this document, go to our website at:
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1367 0495
E-mail: [email protected]
All other locations:
Phone: +1 603 223 2362
E-mail: [email protected]
ISO/TS 16949 and ISO14001 Certified
39012 71122 01
Rev. 001
Page 32 of 32
EVB Description
Sept/06