LM1291 Video PLL System for Continuous-Sync Monitors General Description Features The LM1291 is an integrated horizontal time base solution specifically designed to operate in continuous-sync video monitors. It automatically synchronizes to any H frequency from 22 kHz to 125 kHz and provides the drive pulse to the high power deflection circuit. Available sync processing includes a vertical sync separator and a composite video sync stripper. An internal sync selection scheme gives highest priority to separate H and V sync, then composite sync, and finally sync on video; no external switching between sync sources is necessary. The LM1291 provides polarity-normalized H/HV and V sync outputs, along with logic flags which show the respective input polarities. The design uses an on-chip FVC (Frequency-to-Voltage Converter) to set the center frequency of the VCO (VoltageControlled Oscillator). This technique allows autosync operation over the entire frequency range using just one optimized set of external components. The system includes a second phase detector which compensates for storage time variation in the horizontal output transistor; the picture’s horizontal position is thus independent of temperature and component variance. The LM1291 provides DC control pins for H Drive duty cycle and flyback phase. Y Y Y Y Y Y Y Y Y Y Y Y Y Y Wide continuous autosync rangeÐ22 kHz to 125 kHz (1 : 5.7) with no component switching or external adjustments No manufacturing trims requiredÐinternal VCO capacitor trimmed on chip No costly high-precision components needed Low phase jitter (1.3 ns at 100 kHz) DC controlled H phase and duty cycle Video mute pulse for blanking during H frequency transitions Input sync prioritization Clamp pulse position and width control Continuous clamp pulse output, even with no sync input Resistor-programmable minimum and maximum VCO frequency X-ray input disables H drive and mutes video until VCC powered down H drive disabled for VCC k 9.5V Horizontal output transistor protected against accidental turn-on during flyback Capacitor-programmable frequency ramping, dfVCO/dt, protects H output transistor during scanning mode changes Connection Diagram TL/H/12323 – 1 FIGURE 1 Order Number LM1291N See NS Package Number N28B C1995 National Semiconductor Corporation TL/H/12323 RRD-B30M115/Printed in U. S. A. LM1291 Video PLL System for Continuous-Sync Monitors June 1995 Absolute Maximum Ratings (Notes 1 & 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage, VDC Pins 15, 23 Pins 4, 5 Pins 8, 28 Pins 1, 9, 12, 14, 16, 18 Power Dissipation (PD) (Above 25§ C Derate Based on iJA and TJ) Thermal Resistance (iJA) Junction Temperature (TJ) 150§ C ESD Susceptibility (Note 5) 2 kV 14V Storage Temperature Lead Temperature (Soldering, 10 sec.) 5V 8V 10V VCC Operating Temperature Range b 65§ C to a 150§ C 265§ C Operating Ratings (Note 2) Supply Voltage (VCC) b 20§ C to a 80§ C 10.8V s VCC s 13.2V 2.5W 50§ C/W Electrical Characteristics See Test Circuit (Figure 2); TA e 25§ C; VCC e 12V Parameter Conditions Supply Current Jitter H Sync frequency e 100 kHz (Note 8) Minimum composite video input voltage Pin 9, cap coupled (0.01 mF), sync tip to black level DC clamp level, composite video input Clamp charging current, composite video input H/HV sync input amplitude (Pin 12) Typical (Note 6) Limit (Note 7) Units 30 40 mA (max) 1.3 ns p-p 0.14 VPP (min) 2.0 VDC 1 mA Cap coupled, 10% duty cycle 1.0 VPP (min) V sync input amplitude (Pin 8) Cap coupled, 1% duty cycle 1.0 VPP (min) High level output voltage VOH, (Pins 2, 11, 13, 17, 19) IOH e b100 mA 4.3 4.0 VDC (min) Low level output voltage VOL, (Pins 2, 11, 13, 17, 19) IOL e 1.6 mA 0.25 0.4 VDC (max) Video Mute low level output voltage (Pin 3) IOL e 2 mA 0.4 VDC (max) Mute detection voltage threshold DV, lFVC Cap 1 b FVC Cap 2l for Mute Output low 100 mV Flyback input threshold (Pin 18) Positive-going flyback pulse 1.4 V Under-voltage lockout (Pin 7) VCC below threshold: H Drive Output open (unlatched) 9.5 V Frequency to voltage gain 22 kHz s fH s 125 kHz 0.047 V/kHz VCO gain constant fVCO e 100 kHz 1.34 c 105 Rad/s/V PD1 Phase Detector gain constant fVCO e 100 kHz 130 fVCO e 60 kHz 78.1 fVCO e 22 kHz 28.6 Frequency to voltage linearity 22 kHz s fH s 125 kHz 1.0 % VCO linearity 22 kHz s fVCO s 125 kHz 1.0 % 2 mA/Radian Electrical Characteristics See Test Circuit (Figure 2); TA e 25§ C; VCC e 12V (Continued) Parameter Conditions Typical (Note 6) Limit (Note 7) Units H Drive duty cycle control gain DC input 0V – 4V; 30% – 70% allowed 0.1 TH/V H Drive Phase control gain (Note 9) 47 § /V PD1 Phase detector leakage current a VCO input bias current (Pin 28) H Drive low level output voltage (Pin 20) IOL e 100 mA H Drive EN low level input voltage (Pin 15) H Drive output active H Drive EN high level input voltage (Pin 15) H Drive output open (unlatched) X-ray Shutdown threshold voltage (Pin 16) Above threshold H Drive Output Open (Latched) H/HV Sync out propagation delay change H/HV in vs. Comp Video in Clamp Pulse width Clamp Pulse Delay mA (max) 0.8 V (max) 0.8 V (max) 2.0 V (min) 1.65 1.8 V (min) V(max) 32 ns (back porch) RSET e 15k; VSET e 0V 0.4 ms (back porch) RSET e 15k; VSET e 1.5V 1.4 ms (sync tip) RSET e 15k; VSET e 4V 0.6 ms (back porch) Trailing edge H/HV Sync In to leading edge clamp pulse 0.1 ms 0.025 TH s 8.2 V (sync tip) Leading edge H/HV Sync In to leading edge clamp pulse Internal Ref voltage at pin 6 1.72 1 No load Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: All voltages are measured with respect to GND, unless otherwise specified. Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, iJA and the ambient temperature, TA. The maximum allowable power dissipation at any elevated temperature is PD e (TJmax b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax e 150§ C. The typical thermal resistance (iJA) of these parts when board mounted follow: LM1291N 50§ C/W. Note 5: Human Body model, 100 pF capacitor discharged through a 1.5 kX resistor. Note 6: Typicals are at TA e TJ e 25§ C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Measured with HP 53310A Modulation Domain Analyzer, 50 ms sample window. # J tDFB 0.35 b , expressed as a fraction of the horizontal period TH, where tDFB is the horizontal output transistor turn-off TH delay from the rising edge of H Drive to the FBP peak. A positive phase value represents a phase lead of the FBP peak with reference to the leading edge of H sync. Note 9: Phase limits: b 0.15 k w k 3 FIGURE 2 TL/H/12323 – 2 Test Circuit 4 Block Diagram TL/H/12323 – 3 FIGURE 3 Pin Descriptions See Figures 4 through 15 for input and output schematics. Pin 5 - fMIN: A resistor from this pin to ground sets the lower frequency limit of the VCO. fMIN is approximately: Pin 1 - CLAMP CNTL: This low-impedance current-mode input pin is internally biased to 2V. The direction of current sets the pulse position (back porch or sync-tip), while the current magnitude sets the pulse width. In a typical application, a control voltage of 0V–4V is applied to this pin through a 15 kX resistor. A voltage below 2V positions the pulse on the back porch of the horizontal sync pulse and decreasing voltage narrows the pulse. A voltage above 2V sets the pulse on the H sync-tip (slightly delayed from the leading edge) and increasing voltage narrows the pulse. At the boundary of the switchover between the two modes, there is a narrow region of uncertainty resulting in oscillation, which should be no problem in most applications. When there is no H sync in sync-tip mode, the clamp pulse is generated by the VCO at the frequency preset by pin 5 (fMIN). This feature is intended for use in On Screen Display systems. 7.5 c 103 a 5.6 c 108 Hz (RMIN a 500) Pin 6 - VREF CAP: This is the decoupling pin for the internal 8.2V reference. It should be decoupled to pin 21 (GND) via a short path with a cap of at least 470 mF. Pin 7 - VCC: 12V nominal power supply pin. This pin should be decoupled to pin 21 (GND) via a short path with a cap of at least 47 mF. Pin 8 - V SYNC IN: This pin accepts AC-coupled V sync of either polarity. The pin is internally biased at 5.2V; its input resistance is approximately 50 kX. For best noise immunity, a resistor of 2 kX or less should be connected from the input side of the coupling cap to ground. See Figure 6 for the input schematic. Pin 2 - CLAMP PULSE: Active-low clamp pulse output. See Figure 4 for the output schematic. Pin 9 - COMP VIDEO IN: The composite video sync stripper is active only when no signal is present at pin 12 (H/HV IN). The signal to pin 9 must have negative-going sync tips which are at least 0.14V below black level. For best noise immunity, a resistor of 2 kX or less should be connected from the input side of the coupling cap to ground. See Figure 7 for the input schematic. Pin 3 - VIDEO MUTE: This NPN open-collector output produces an active-low pulse when triggered by a step change of H sync frequency. See Figure 5 for the output schematic. Pin 4 - fMAX: A resistor from this pin to ground sets the upper frequency limit of the VCO. fMAX is approximately: Pin 10 - H/HV CAP: A capacitor is connected from this pin to ground for detecting the polarity and existence of H/HV sync at pin 12. 1.8 c 109 Hz (RMAX a 500) 5 Pin Descriptions (Continued) Pin 24 - V CAP: A capacitor is connected from this pin to ground for detecting the polarity and existence of V sync at pin 8. Pin 11 - H/HV SYNC OUT: The sync processor outputs active-low H/HV sync derived from the active sync input (pin 9 or pin 12). Pin 11 stays low in the absence of sync input. See Figure 4 for the output schematic. Pin 25 - FVC CAP 2: Secondary FVC filter pin. CFVC2 is connected from this pin to ground. The width of the VIDEO MUTE (pin 3) pulse is controlled by the time constant difference between the filters at pins 25 and 26. Pin 12 - H/HV SYNC IN: This pin accepts AC-coupled H or composite sync of either polarity. For best noise immunity, a resistor of 2 kX or less should be connected from the input side of the coupling cap to ground. See Figure 8 for the input schematic. Pin 26 - FVC CAP 1: Primary FVC filter pin. CFVC1 is connected from this pin to pin 21 (GND) via a short path. The voltage at this pin is buffered to pin 27 (FVC OUT). Pin 13 - H/HV POL OUT: A low logic level indicates activehigh H/HV sync to pin 12, a high level indicates active-low. Pin 13 stays low in the absence of H/HV sync. See Figure 9 for the output schematic. Pin 27 - FVC OUT: Buffered output of the Frequency-toVoltage Converter, which sets the VCO center frequency through an external resistor to pin 28. Care should be taken when further loading this pin, since during the vertical interval it presents a high output impedance. Excessive loading can cause top-of-screen phase recovery problems. Pin 14 - H DR DUTY CNTL: A DC voltage applied to this pin sets the duty cycle of the horizontal drive output (pin 20), with a range of approximately 30%–70%. 2V sets the duty cycle to 50%. See Figure 10 for the input schematic. Pin 28 - PD1 OUT/VCO IN: Phase detector 1 has a gated charge pump output which requires an external low-pass filter. For best jitter performance, the filter should be grounded to pin 21 (GND) via a short path. If a voltage source is applied to this pin, the phase detector is disabled and the VCO can be controlled directly. Pin 15 - H DRIVE EN: A low logic level input enables H DRIVE OUT (pin 20). See Figure 11 for the input schematic. Pin 16 - X-RAY SHUTDOWN: This pin is for monitoring CRT anode voltage. If the input voltage exceeds an internal threshold, H DRIVE OUT (pin 20) is latched high and VIDEO MUTE (pin 3) is latched low. VCC has to be reduced to below approximately 2V to clear the latched condition, i.e., power must be turned off. See Figure 12 for the input schematic. Application Hints 1. Phase control for geometry correction: Pin 23 (H DRlVE PHASE) is designed to control static phase (picture horizontal position), while pin 22 (PHASE DET 2 CAP) controls dynamic phase for geometry correction. With the use of both pins 22 and 23, complete control of static and dynamic phase can be achieved. To accomplish this, the low-pass filter cap at pin 22 is not grounded, but is connected instead to a modulating AC voltage source. The cap then functions both as a low-pass filter (for phase detector 2) and as an input coupling cap (for the AC source). Pin 17 - V SYNC OUT: The sync processor outputs activelow V sync derived from the active sync input (pin 8, pin 9 or pin 12). Pin 17 stays low in the absence of sync input. See Figure 4 for the output schematic. Pin 18 - FLYBACK IN: Input pin for phase detector 2. For best operation, the flyback peak should be at least 5V but not greater than VCC. Any pulse width greater than 1.5 ms is acceptable. See Figure 13 for the input schematic. 2. Programmable frequency ramping: H frequency transitions from high to low present a special problem for deflection output stages without current limiting. lf, during such a transition, the output transistor on-time increases excessively before the B a voltage has decreased to its final level, then the deflection inductor current ramps too high and the induced flyback pulse can exceed the breakdown voltage, BVCEX, of the output transistor. To prevent this, the rate of change of the VCO frequency must be limited. Consider a scanning mode transition at t e 0 from f1 to f2. The VCO frequency as a function of time, fVCO(t), is described by the equation, Pin 19 - V POL OUT: A low logic level indicates active-high V sync to pin 8, a high level indicates active-low. Pin 19 stays low in the absence of V sync. See Figure 9 for the output schematic. Pin 20 - H DRIVE OUT: This is an open-collector output which provides the drive pulse for the high power deflection circuit. The pulse duty cycle is controlled by pin 14. Polarity convention: Horizontal deflection output transistor is on when H DRIVE OUT is low. See Figure 5 for the output schematic. Pin 21 - GND: System ground. For best jitter performance, all LM1291 filter components and bypass capacitors should be connected to this pin via short paths. fVCO(t) j f1 a (f2 b f1)(1 b exp(bt/u)) where u e 40 c 103 c CFVC1. The above equation can be used to predict VCO behavior during frequency transitions, but in practice the value of CFVC1 is most easily determined empirically. In general, large vaIues minimize the chance of exceeding BVCEX, but generate long PLL capture times. Pin 22 - PHASE DET 2 CAP: The low-pass filter cap for the output of phase detector 2 is connected from this pin to pin 21 (GND) via a short path. Pin 23 - H DRlVE PHASE: A DC control voltage applied to this pin sets the phase of the flyback pulse with respect to the leading edge of H sync. See Figure 14 for the input schematic. 6 Application Hints (Continued) 3. Video mute: Many sync sources fail to exhibit a clean step change of H sync frequency during scanning mode transitions. For this reason, in most applications a pulse smoothing circuit is needed at pin 3. Typically a 2.2 mF cap to ground is used in conjunction with a 100 kX pull-up resistor. See Figure 16. The resulting pulse has a slow rise time at the trailing edge, which extends the effective mute duration slightly. Numerous designs require video blanking during scanning mode transitions. The LM1291 provides an active-low pulse at pin 3 when triggered by a step change of H sync frequency from f1 to f2. The pulse width is controlled by the time constants set up through capacitors CFVC2 and CFVC1, at pins 25 and 26 respectively. For CFVC2 t 3 c CFVC1, the pulse width is approximately: 40 c 103 c CFVC2 c ln lf2 b f1l # 2.13 c 103 J seconds Input/Output Schematics TL/H/12323 – 4 FIGURE 4 TL/H/12323 – 5 FIGURE 5 TL/H/12323 – 6 FIGURE 6 7 Input/Output Schematics (Continued) TL/H/12323 – 7 FIGURE 7 TL/H/12323 – 8 FIGURE 8 TL/H/12323 – 9 FIGURE 9 8 Input/Output Schematics (Continued) TL/H/12323 – 11 FIGURE 11 TL/H/12323 – 10 FIGURE 10 TL/H/12323 – 13 FIGURE 13 TL/H/12323 – 12 FIGURE 12 TL/H/12323 – 14 FIGURE 14 TL/H/12323 – 15 FIGURE 15 9 FIGURE 16 TL/H/12323 – 16 Typical Application 10 11 LM1291 Video PLL System for Continuous-Sync Monitors Physical Dimensions inches (millimeters) 28-Lead (0.600× Wide) Molded Dual-In-Line Package Order Number LM1291N NS Package Number N28B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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