3826 Group (A version) REJ03B0029-0200 Rev.2.00 2006.05.24 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3826 group (A version) is the 8-bit microcomputer based on the 740 family core technology. The 3826 group (A version) has the LCD drive control circuit, an 8channel A/D converter, D/A converter, serial interface and PWM as additional functions. The various microcomputers in the 3826 group (A version) include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3826 group (A version), refer the section on group expansion. •Timers ............................................................ 8-bit ✕ 3, 16-bit ✕ 2 • Serial interface • • • • FEATURES • Basic machine-language instructions ....................................... 71 • The minimum instruction execution time ............................ 0.4 µs • • • • • • (at 10 MHz oscillation frequency) Memory size ROM ................................................................ 48 K to 60 K bytes RAM ............................................................... 1536 to 2560 bytes Programmable input/output ports ............................................. 55 Software pull-up resistors .................................................... Built-in Output ports ................................................................................. 8 Input ports .................................................................................... 1 Interrupts .................................................. 17 sources, 16 vectors External ................ 7 sources (includes key input interrupt) Internal ................................................................ 9 sources Software ................................................................ 1 source • • • • • Serial I/O1 ...................... 8-bit ✕ 1 (UART or Clock-synchronous) Serial I/O2 .................................... 8-bit ✕ 1 (Clock-synchronous) PWM output .................................................................... 8-bit ✕ 1 A/D converter ............. 10-bit ✕ 8 channels or 8-bit ✕ 8 channels D/A converter .................................................. 8-bit ✕ 2 channels (used as DTMF and CTCSS function) LCD drive control circuit Bias ......................................................................... 1/2, 1/3 Duty .................................................................. 1/2, 1/3, 1/4 Common output ................................................................ 4 Segment output .............................................................. 40 2 Clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) Watchdog timer ............................................................. 14-bit ✕ 1 Power source voltage In high-speed mode (f(XIN) = 10 MHz) ................... 4.5 V to 5.5 V In high-speed mode (f(XIN) = 8 MHz) ..................... 4.0 V to 5.5 V In middle-speed mode (f(XIN) = 6 MHz) ................. 1.8 V to 5.5 V In low-speed mode .................................................. 1.8 V to 5.5 V Power dissipation In high-speed mode ................................................... Typ. 28 mW (f(XIN) = 10 MHz, VCC = 5 V, Ta = 25 °C) In low-speed mode ...................................................... Typ. 27 µW (f(XIN) = stop, f(XCIN) = 32 kHz, VCC = 3 V, Ta = 25 °C) Operating temperature range ................................... – 20 to 85°C APPLICATIONS Camera, household appliances, consumer electronics, etc. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 1 of 90 3826 Group (A version) SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 P14/SEG38 P15/SEG39 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 50 49 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M3826XMXA-XXXFP 100 RESET P70/INT0 P71 P72 P73 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 C1 VL1 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40 P77 P76 P75 P74 1 2 3 4 5 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOUT XIN XCOUT XCIN Package type : PRQP0100JB-A (100P6S-A) SEG13 SEG14 SEG15 SEG16 SEG17 P30/SEG18 P31/SEG19 P32/SEG20 P33/SEG21 P34/SEG22 P35/SEG23 P36/SEG24 P37/SEG25 P00/SEG26 P01/SEG27 P02/SEG28 P03/SEG29 P04/SEG30 P05/SEG31 P06/SEG32 P07/SEG33 P10/SEG34 P11/SEG35 P12/SEG36 P13/SEG37 Fig. 1 Pin configuration (Package type: PRQP0100JB-A) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VCC VREF AVSS COM3 COM2 COM1 COM0 VL3 VL2 C2 C1 VL1 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 M3826XMXA-XXXGP 38 37 36 35 34 33 32 31 30 29 28 27 26 P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/SCLK22/AN3 P62/SCLK21/AN2 P61/SOUT2/AN1 P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/φ/TOUT P42/INT2 P41/INT1 P40 P77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Package type : PLQP0100KB-A (100P6Q-A) Fig. 2 Pin configuration (Package type: PLQP0100KB-A) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 2 of 90 P14/SEG38 P15/SEG39 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 VSS XOU T XIN XCOUT XCIN RESET P70/INT0 P71 P72 P73 P74 P75 P76 39 38 X COUT Subclock output X CIN Subclock input φ I/O port P7 27 28 29 30 31 32 33 34 P7(8) Watchdog timer Sub-clock Sub-clock input output XCIN XCOUT 36 37 X COUT X CIN X OUT X IN Clock generating circuit Main clock output Main clock input INT0 page 3 of 90 3 4 7 8 P6(8) 6 9 10 VREF AVSS 92 93 A/D converter (8) SI/O2(8) I/O port P6 5 Reset PC H PS DA2 DA1 CNTR0,CNTR1 P5(8) PCL S Y X A 35 RESET Reset input I/O port P5 11 12 13 14 15 16 17 18 C P U ADT Rev.2.00 May. 24, 2006 REJ03B0028-0200 P4(8) I/O port P4 Timer X (16) φ SI/O1 (8) P3(8) Output port P3 65 66 67 68 69 70 71 72 TOUT Timer 3 (8) Timer 2 (8) Timer Y (16) Timer 1 (8) 19 20 21 22 23 24 25 26 PWM(8) 40 91 ROM VSS VCC Data bus (0V) (5V) INT1,INT2 Fig. 3 Functional block diagram I/O port P2 41 42 43 44 45 46 47 48 P2(8) DA2/CTCSS LCD display RAM (20 bytes) RAM I/O port P1 P0(8) I/O port P0 57 58 59 60 61 62 63 64 LCD drive control circuit 49 50 51 52 53 54 55 56 P1(8) DA1/DTMF Key input (Key-on wake up) interrupt FUNCTIONAL BLOCK DIAGRAM (Package type: PRQP0100JB-A) 2 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 90 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 94 95 96 COM0 COM1 COM2 COM3 VL1 C1 C2 VL2 VL3 97 98 99 100 3826 Group (A version) Real time port function 3826 Group (A version) PIN DESCRIPTION Table 1 Pin description (1) Pin Name Function VCC VSS VREF Power source AVSS Analog power source •GND input pin for A/D converter and D/A converter. RESET XIN Reset input •Reset input pin for active “L”. Clock input •Input and output pins for the main clock generating circuit. XOUT Clock output Function except a port function •Apply voltage of power source to V CC, and 0 V to VSS. (For the limits of VCC, refer to “Recommended operating conditions”. •Reference voltage input pin for A/D converter and D/A converter. Analog reference voltage •Connect to VSS. •Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. A feedback resistor is built-in. LCD power source •Input 0 ≤ VL1 ≤ VL2 ≤ VL3 voltage. C1, C2 Charge-pump capacitor pin •External capacitor pins for a voltage multiplier (3 times) of LCD control. COM0–COM3 Common output •LCD common output pins. VL1–VL3 •Input 0 – VL3 voltage to LCD. (0 ≤ VL1 ≤ VL2 ≤ VL3 when a voltage is multiplied.) •COM2 and COM3 are not used at 1/2 duty ratio. •COM3 is not used at 1/3 duty ratio. SEG0–SEG17 Segment output •LCD segment output pins. P00/SEG26– P07/SEG33 I/O port P0 •8-bit I/O port. •LCD segment output pins •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 8-bit pin to be programmed as either input or output. P10/SEG34– P15/SEG39 I/O port P1 •6-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •Pull-up control is enabled. •I/O direction register allows each 6-bit pin to be programmed as either input or output. P16, P17 •2-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. P20 – P27 •Pull-up control is enabled. •8-bit I/O port. I/O port P2 •CMOS compatible input level. •Key input (key-on wake-up) interrupt input pins •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. P30/SEG18 – P37/SEG25 Output port P3 •8-bit output. •CMOS 3-state output structure. •Port output control is enabled. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 4 of 90 •LCD segment output pins 3826 Group (A version) Table 2 Pin description (2) Pin P40 Name Function I/O port P4 Function except a port function •1-bit I/O port. •CMOS compatible input level. •N-channel open-drain output structure. •I/O direction register allows this pin to be individually programmed as either input or output. P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/PWM0, P51/PWM1 P52/RTP0, P53/RTP1 P54/CNTR0, P55/CNTR1 P56/DA1 P57/ADT/DA2 •7-bit I/O port. •CMOS compatible input level. •CMOS 3-state output structure. •I/O direction register allows each pin to be individually programmed as either input or output. •INTi interrupt input pins •System clock φ output pin •Timer 2 output pin •Serial I/O1 I/O pins •Pull-up control is enabled. •8-bit I/O port. I/O port P5 •PWM output pins •CMOS compatible input level. •CMOS 3-state output structure. •Real time port output pins •I/O direction register allows each pin to be individually programmed as either input or output. •Timer X, Y I/O pins •Pull-up control is enabled. •D/A converter output pin •D/A converter output pin •A/D external trigger input pin P60/SIN2/AN0, P61/SOUT2/AN1, P62/SCLK21/AN2, P63/SCLK22/AN3 P64/AN4– P67/AN7 I/O port P6 P70/INT0 P71–P77 Input port P7 I/O port P7 •8-bit I/O port. •A/D converter input pins •CMOS compatible input level. •Serial I/O2 I/O pins •CMOS 3-state output structure. •A/D converter input pins •I/O direction register allows each pin to be individually programmed as either input or output. •Pull-up control is enabled. •1-bit input port. •INT0 interrupt input pin •7-bit I/O port. •CMOS compatible input level. •N-channel open-drain output structure. •I/O direction register allows each pin to be individually programmed as either input or output. XCOUT XCIN Sub-clock output Sub-clock input Rev.2.00 May. 24, 2006 REJ03B0028-0200 •Sub-clock generating circuit I/O pins. (Connect a oscillator. External clock cannot be used.) page 5 of 90 3826 Group (A version) PART NUMBERING Product M3826 A M F A – XXX FP Package type FP : PRQP0100JB-A GP : PLQP0100KB-A ROM number Characteristics A : A version ROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M: Mask ROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes A : 2560 bytes Fig. 4 Part numbering Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 6 of 90 3826 Group (A version) GROUP EXPANSION Packages Renesas expands the 3826 group (A version) as follows. PLQP0100KB-A ......................... 0.5 mm-pitch plastic molded QFP PRQP0100JB-A ....................... 0.65 mm-pitch plastic molded QFP Memory Type Support for mask ROM version. Memory Size ROM size ........................................................... 48 K to 60 K bytes RAM size .......................................................... 1536 to 2560 bytes Memory Expansion Plan Mass production ROM size (bytes) 60K M3826AMFA 56K Mass production 52K 48K M38268MCA 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K 192 256 512 768 1024 1280 1536 1792 2048 2304 2560 RAM size (bytes) Fig. 5 Memory expansion plan Currently planning products are listed below. As of Apr. 2006 Table 3 Support products Part number ROM size (bytes) ROM size for User in ( ) RAM size (bytes) M38268MCA-XXXFP M38268MCA-XXXGP M3826AMFA-XXXFP M3826AMFA-XXXGP 49152 (49022) 1536 61440 (61310) 2560 Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 7 of 90 Package PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version 3826 Group (A version) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) [Stack Pointer (S)] The 3826 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. The central processing unit (CPU) has six registers. Figure 6 shows the 740 Family CPU register structure. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as arithmetic data transfer, etc., are executed mainly through the accumulator. The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. Figure 9 shows the operations of pushing register contents onto the stack and popping them from the stack. Table 6 shows the push and pop instructions of accumulator or processor status register. Store registers other than those described in Figure 9 with program when the user needs them during interrupts or subroutine calls. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. b0 b7 A Accumulator b0 b7 X Index register X b0 b7 Y b7 Index register Y b0 S b15 b0 b7 PCH Stack pointer Program counter PCL b7 b0 N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag Fig. 6 740 Family CPU register structure Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 8 of 90 3826 Group (A version) On-going Routine Interrupt request (Note) M (S) Execute JSR Push return address on stack M (S) (PCH) (S) (S) – 1 M (S) (PCL) (S) (S)– 1 M (S) (S) M (S) (S) Subroutine POP return address from stack (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) (S) – 1 (S) – 1 (PS) (S) – 1 Execute RTI Note: Condition for acceptance of an interrupt request here Push return address on stack (PCL) Interrupt Service Routine Execute RTS (S) (S) (PCH) (S) (S) + 1 (PS) M (S) (S) (S) + 1 (PCL) M (S) (S) (S) + 1 (PCH) M (S) Push contents of processor status register on stack I Flag is set from “0” to “1” Fetch the jump vector POP contents of processor status register from stack POP return address from stack Interrupt enable bit corresponding to each interrupt source is “1” Interrupt disable flag is “0” Fig. 7 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 9 of 90 3826 Group (A version) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. • Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. • Bit 1: Zero flag (Z) The Z flag is set to “1” if the result of an immediate arithmetic operation or a data transfer is “0”, and set to “0” if the result is anything other than “0”. • Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. • Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. • Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. When the BRK instruction is generated, the B flag is set to “1” automatically. When the other interrupts are generated, the B flag is set to “0”, and the processor status register is pushed onto the stack. • Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations. • Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set to “1” if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the V flag. • Bit 7: Negative flag (N) The N flag is set to “1” if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Instructions to set each bit of processor status register to “0” or “1” C flag Z flag I flag D flag B flag T flag V flag N flag Instruction setting to “1” SEC – SEI SED – SET – – Instruction setting to “0” CLC – CLI CLD – CLT CLV – Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 10 of 90 3826 Group (A version) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the system clock control bits, etc. The CPU mode register is allocated at address 003B16. b7 b0 1 CPU mode register (CPUM (CM) : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Do not select 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Not used (“1” at reading) (Write “1” to this bit at writing) XC switch bit 0 : Oscillation stop 1 : XCIN–XCOUT oscillating function Main clock (XIN–XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) System clock selection bit 0 : XIN–XOUT selected (middle-/high-speed mode) 1 : XCIN–XCOUT selected (low-speed mode) Fig. 8 Structure of CPU mode register Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 11 of 90 3826 Group (A version) MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Zero Page The 256 bytes from addresses 0000 16 to 00FF 16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. The interrupt vector area contains reset and interrupt vectors. RAM area RAM size (bytes) Address XXXX16 192 00FF16 256 013F16 004016 384 01BF16 005416 512 023F16 640 02BF16 768 033F16 896 03BF16 1024 043F16 1536 063F16 2048 083F16 2560 0A3F16 000016 SFR area LCD display RAM area Zero page 010016 RAM XXXX16 Not used ROM area ROM size (bytes) Address YYYY16 Address ZZZZ16 4096 F00016 F08016 8192 E00016 E08016 12288 D00016 D08016 16384 C00016 C08016 20480 B00016 B08016 24576 A00016 A08016 28672 900016 908016 32768 800016 808016 36864 700016 708016 40960 600016 608016 45056 500016 508016 49152 400016 408016 53248 300016 308016 FFFE16 57344 200016 208016 FFFF16 61440 100016 108016 Fig. 9 Memory map diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 12 of 90 YYYY16 Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 FFDC16 Interrupt vector area Reserved ROM area Special page 3826 Group (A version) 000016 Port P0 register (P0) 000116 Port P0 direction register (P0D) 000216 000316 Port P1 register (P1) 000416 Port P1 direction register (P1D) Port P2 register (P2) 000516 Port P2 direction register (P2D) 000616 000816 Port P3 register (P3) Port P3 output control register (P3C) Port P4 register (P4) 000916 Port P4 direction register (P4D) 000716 000A16 Port P5 register (P5) 000B16 Port P5 direction register (P5D) 000C16 Port P6 register (P6) 000D16 Port P6 direction register (P6D) 000E16 Port P7 register (P7) 000F16 Port P7 direction register (P7D) 001016 001116 001216 001316 001416 001516 001616 001716 AD conversion low-order register (ADL) Key input control register (KIC) PULL register A (PULLA) PULL register B (PULLB) 002016 Timer X low-order register (TXL) 002116 Timer X high-order register (TXH) 002216 Timer Y low-order register (TYL) 002316 Timer Y high-order register (TYH) 002416 Timer 1 register (T1) 002516 Timer 2 register (T2) 002616 Timer 3 register (T3) 002716 Timer X mode register (TXM) 002816 Timer Y mode register (TYM) 002916 Timer 123 mode register (T123M) 002A16 TOUT/φ output control register (CKOUT) 002B16 PWM control register (PWMCON) 002C16 PWM prescaler (PREPWM) 002D16 PWM register (PWM) 002E16 CTSCSS timer (low) (CTCSSL) 002F16 CTSCSS timer (high) (CTCSSH) 003016 DTMF high group timer (DTMFH) 003116 DTMF low group timer (DTMFL) 003216 DA1 conversion register (DA1) 003316 DA2 conversion register (DA2) 003416 AD control register (ADCON) 003516 AD conversion high-order register (ADH) 003616 DA control register (DACON) 003716 Watchdog timer control register (WDTCON) 001816 Transmit/Receive buffer register (TB/RB) 001916 Serial I/O1 status register (SIO1STS) 001A16 Serial I/O1 control register (SIO1CON) 003816 Segment output enable register (SEG) 003916 LCD mode register (LM) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART control register (UARTCON) 003B16 CPU mode register (CPUM) 003C16 Interrupt request register 1(IREQ1) 003D16 Interrupt request register 2(IREQ2) 003E16 Interrupt control register 1(ICON1) 003F16 Interrupt control register 2(ICON2) 001C16 Baud rate generator (BRG) 001D16 Serial I/O2 control register (SIO2CON) 001E16 Reserved area (Note) 001F16 Serial I/O2 register (SIO2) Note: Do not write to the addresses of reserved area. Fig. 10 Memory map of special function register (SFR) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 13 of 90 3826 Group (A version) I/O PORTS Direction Registers b7 The I/O ports (ports P0, P1, P2, P4, P5, P6, P71–P77) have direction registers. Ports P16, P17, P4, P5, P6, and P71–P77 can be set to input mode or output mode by each pin individually. P00–P07 and P10-P15 are respectively set to input mode or output mode in a lump by bit 0 of the direction registers of ports P0 and P1 (see Figure 11). When “0” is set to the bit corresponding to a pin, that pin becomes an input mode. When “1” is set to that bit, that pin becomes an output mode. If data is read from a port set to output mode, the value of the port latch is read, not the value of the pin itself. A port set to input mode is floating. If data is read from a port set to input mode, the value of the pin itself is read. If a pin set to input mode is written to, only the port latch is written to and the pin remains floating. b0 Ports P00 to P07 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) b7 b0 Port P1 direction register (P1D : address 000316) Ports P10 to P15 direction register 0 : Input mode 1 : Output mode Not used (Undefined at reading) (If writing to these bits, write “0”.) Port P16 direction register Port P17 direction register 0 : Input mode 1 : Output mode Port P3 Output Control Register Bit 0 of the port P3 output control register (address 000716) enables control of the output of ports P30–P37. When the bit is set to “1”, the port output function is valid. When resetting, bit 0 of the port P3 output control register is set to “0” (the port output function is invalid) and pulled up. Port P0 direction register (P0D : address 000116) Note: In ports set to output mode, the pull-up control bit becomes invalid and pull-up resistor is not connected. Fig. 11 Structure of port P0 direction register, port P1 direction register b7 b0 Port P3 output control register (P3C : address 000716) Ports P30 to P37 output control bit 0 : Output function is invalid (Pulled up) 1 : Output function is valid (No pull up) Not used (Undefined at reading) (If writing to these bits, write “0”.) Note: In pins set to segment output by segment output enable bits 0, 1 (bits 0, 1 of segment output enable register (address 3816)), this bit becomes invalid and pull-up resistor is not connected. Fig. 12 Structure of port P3 output control register Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 14 of 90 3826 Group (A version) Pull-up Control By setting the PULL register A (address 001616) or the PULL register B (address 0017 16), ports P0 to P2, P4 to P6 can control pull-up with a program. However, the contents of PULL register A and PULL register B do not affect ports set to output mode and the ports are no pulled up. The PULL register A setting is invalid for pins selecting segment output with the segment output enable register and the pins are not pulled up. b7 b0 PULL register A (PULLA : address 001616) P00, P01 pull-up control bit P02, P03 pull-up control bit P04–P07 pull-up control bit P10–P13 pull-up control bit P14, P15 pull-up control bit P16, P17 pull-up control bit P20–P23 pull-up control bit P24–P27 pull-up control bit b7 b0 PULL register B (PULLB : address 001716) P41–P43 pull-up control bit P44–P47 pull-up control bit P50–P53 pull-up control bit P54–P57 pull-up control bit P60–P63 pull-up control bit P64–P67 pull-up control bit Not used “0” at reading) 0 : Disable 1 : Enable Note: The contents of PULL register A and PULL register B do not affect ports set to output mode. Fig. 13 Structure of PULL register A and PULL register B Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 15 of 90 3826 Group (A version) Table 6 List of I/O port function (1) Non-Port Function Pin Name P00/SEG26– P07/SEG33 Port P0 Input/output, byte unit CMOS compatible input level CMOS 3-state output LCD segment output PULL register A Segment output enable register P10/SEG34– P15/SEG39 Port P1 Input/output, 6-bit unit CMOS compatible input level CMOS 3-state output LCD segment output PULL register A Segment output enable register (1) (2) Input/output, individual bits CMOS compatible input level CMOS 3-state output PULL register A (4) P16 , P17 Input/Output I/O Format P20–P27 Port P2 Input/output, individual bits CMOS compatible input level CMOS 3-state output Key input (key-on wake-up) interrupt input P30/SEG18– P37/SEG25 Port P3 Output CMOS 3-state output LCD segment output P40 Port P4 Input/output, individual bits CMOS compatible input level N-channel open-drain output CMOS compatible input level CMOS 3-state output P41/INT1, P42/INT2 P43/φ/TOUT P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 Related SFRs Diagram No. (1) (2) PULL register A Interrupt control register 2 Key input control register Segment output enable register Port P3 output control register (3) (13) INTi interrupt input Timer 2 output System clock φ output Serial I/O1 I/O Interrupt edge selection register PULL register B Timer 123 mode register TOUT/φ output control register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register (4) (12) (5) (6) (7) (8) PWM output PULL register B PWM control register (10) Real time port output PULL register B Timer X mode register (9) P54/CNTR0 Timer X I/O (11) P55/CNTR1 Timer Y input PULL register B Timer X mode register PULL register B P56/DA1 DA1 output DTMF input DA2 output CTCSS output A/D external trigger input Timer Y mode register PULL register B DA control register PULL register B DA control register AD control register P50/PWM0, P51/PWM1 Port P5 Input/output, individual bits P52/RTP0, P53/RTP1 P57/ADT/ DA2 Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 16 of 90 CMOS compatible input level CMOS 3-state output (14) (15) (15) 3826 Group (A version) Table 7 List of I/O port function (2) Pin P60/SIN2/AN0 Name Port P6 P61/SOUT2/ AN1 Input/Output Input/ output, individual bits I/O Format CMOS compatible input level CMOS 3-state output Non-Port Function A/D converter input Serial I/O2 I/O Related SFRS PULL register B AD control register Serial I/O2 control register Diagram No. (17) (18) P62/SCLK21/ AN2 (19) P63/SCLK22 / AN3 (20) P64/AN4– P67/AN7 P70/INT0 Port P7 P71–P77 Input CMOS compatible input level Input/ output, individual bits CMOS compatible input level N-channel open-drain output COM0–COM3 Common Output LCD common output SEG0–SEG17 Segment Output LCD segment output A/D converter input AD control register PULL register B (16) INT0 interrupt input Interrupt edge selection register (23) (13) LCD mode register (21) (22) Notes 1: How to use double-function ports as function I/O pins, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or V CC before execution of the STP instruction. When an electric potential is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate and power source current may increase. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 17 of 90 3826 Group (A version) (1) Ports P01–P07, P11–P15 Pull-up VL2/VL3/VCC Segment/Port LCD drive timing Segment data Interface logic level shift circuit Data bus Port latch Port direction register Segment VL1/VSS Port Segment output enable bit Port direction register (2) Ports P00, P10 Pull-up VL2/VL3/VCC Segment/Port LCD drive timing Direction register Segment data Data bus Interface logic level shift circuit Port latch Segment VL1/VSS Segment output Port enable bit Port direction register (3) Port P3 Pull-up Segment data Port latch Port P3 output control bit Data bus LCD drive timing VL2/VL3/VCC Segment/Port Interface logic level shift circuit Segment VL1/VSS Port Segment output Port P3 output control bit enable bit (4) Ports P16, P17, P2, P41, P42 (5) Port P44 Pull-up control Serial I/O1 enable bit Receive enable bit Direction register Data bus Direction register Port latch Data bus Key input interrupt input INT1, INT2 interrupt input Except P16, P17 Fig. 14 Port block diagram (1) Rev.2.00 May. 24, 2006 REJ03B0028-0200 Pull-up control page 18 of 90 Port latch Serial I/O1 input 3826 Group (A version) (6) Port P45 (7) Port P46 Pull-up control P45/TxD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Pull-up control Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Port latch Data bus Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Data bus Serial I/O1 output Port latch Serial I/O1 clock output Serial I/O1 clock input (8) Port P47 (9) Ports P52,P53 Pull-up control Pull-up control Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Direction register Data bus Port latch Port latch Real time port control bit Real time port data Serial I/O1 ready output (11) Port P54 (10) Ports P50,P51 Pull-up control Pull-up control Direction register Direction register Data bus Data bus Port latch Port latch Pulse output mode Timer output PWM function enable bit PWM output CNTR0 interrupt input Fig. 15 Port block diagram (2) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 19 of 90 3826 Group (A version) (13) Ports P40,P71–P77 (12) Port P43 Pull-up control Direction register Direction register Data bus Data bus Port latch Port latch TOUT/φ output enable bit Timer 2 TOUT output TOUT/φ output selection bit System clock φ output (15) Ports P56,P57 (14) Port P55 Direction register Direction register Data bus Pull-up control Pull-up control Data bus Port latch CNTR1 interrupt input Port latch A/D external trigger input Except P56 D/A converter output DA1, DA2 output enable bits (16) Ports P64–P67 (17) Port P60 Pull-up control Pull-up control Direction register Data bus Port latch A/D converter input Analog input pin selection bit Direction register Data bus Port latch Serial I/O2 input A/D converter input Analog input pin selection bit Fig. 16 Port block diagram (3) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 20 of 90 3826 Group (A version) (19) Port P62 Serial I/O2 synchronous clock selection bit (18) Port P61 P61/SOUT2 P-channel output disable bit Serial I/O2 transmit end signal Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Pull-up control Pull-up control Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register Port latch Data bus Serial I/O2 output A/D converter input Analog input pin selection bit Port latch Serial I/O2 clock output Serial I/O2 clock input A/D converter input Analog input pin selection bit (20) Port P63 Pull-up control Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Synchronous clock output pin selection bit Direction register (21) COM0–COM3 VL3 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VL2 Data bus Port latch VL1 Serial I/O2 clock output VSS A/D converter input Analog input pin selection bit (23) Port P70 (22) SEG0–SEG17 VL2/VL3 Data bus The voltage applied to the sources of Pchannel and N-channel transistors is the controlled voltage by the bias value. VL1/VSS Fig. 17 Port block diagram (4) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 21 of 90 INT0 input 3826 Group (A version) INTERRUPTS Interrupt Operation Interrupts occur by seventeen sources: seven external, nine internal, and one software. When an interrupt request is accepted, the program branches to the interrupt jump destination address set in the vector address (see Table 8). By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt jump destination address is read from the vector table into the program counter. 3. The interrupt disable flag is set to “1” and the corresponding interrupt request bit is set to “0”. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt is accepted if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set to “0” or “1” by program. Interrupt request bits can be set to “0” by program, but cannot be set to “1” by program. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. When the interrupt disable (I) flag is set to “1”, all interrupt requests except the BRK instruction interrupt and reset are not accepted. When several interrupt requests occur at the same time, the interrupts are received according to priority. Table 8 Interrupt vector addresses and priority Interrupt Source Priority Vector Addresses (Note 1) High Low Interrupt Request Generating Conditions At reset Non-maskable At detection of either rising or falling edge of INT0 input External interrupt (active edge selectable) Remarks Reset (Note 2) INT0 1 2 FFFD16 FFFB16 FFFC16 FFFA16 INT1 3 FFF916 FFF816 At detection of either rising or falling edge of INT1 input External interrupt (active edge selectable) Serial I/O1 reception 4 FFF716 FFF616 At completion of serial I/O1 data reception Valid when serial I/O1 is selected Serial I/O1 transmission 5 FFF516 FFF416 Valid when serial I/O1 is selected Timer X 6 FFF316 FFF216 At completion of serial I/O1 transmit shift or when transmission buffer is empty At timer X underflow Timer Y 7 FFF116 FFF016 At timer Y underflow Timer 2 Timer 3 FFEF16 FFED16 FFEB16 FFEE16 FFEC16 FFEA16 At timer 2 underflow CNTR0 8 9 10 At timer 3 underflow At detection of either rising or falling edge of CNTR0 input External interrupt (active edge selectable) CNTR1 11 FFE916 FFE816 At detection of either rising or falling edge of CNTR1 input External interrupt (active edge selectable) Timer 1 INT2 12 FFE716 FFE616 At timer 1 underflow 13 FFE516 FFE416 At detection of either rising or falling edge of INT2 input External interrupt (active edge selectable) Serial I/O2 14 FFE316 FFE216 At completion of serial I/O2 data transmission or reception Valid when serial I/O2 is selected Key input (Key-on wake-up) 15 FFE116 FFE016 At falling of conjunction of input level for port P2 (at input mode) External interrupt (valid at falling) ADT 16 FFDF16 FFDE16 At falling edge of ADT input At completion of A/D conversion Valid when ADT interrupt is selected External interrupt (valid at falling) Valid when A/D interrupt is selected At BRK instruction execution Non-maskable software interrupt A/D conversion BRK instruction 17 FFDD16 FFDC16 Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset is not an interrupt. Reset has the higher priority than all interrupts. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 22 of 90 3826 Group (A version) ■Notes on interrupts When setting the followings, the interrupt request bit may be set to “1”. •When switching external interrupt active edge Related register: Interrupt edge selection register (address 3A16) Timer X mode register (address 2716) Timer Y mode register (address 2816) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: Interrupt source selection bit of AD control register (bit 6 of address 3416) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. ➀Set the corresponding interrupt enable bit to “0” (disabled). ➁Set the interrupt edge select bit (polarity switch bit) or the interrupt source selection bit. ➂Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Interrupt request acceptance BRK instruction Reset Fig. 18 Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit Not used (“0” at reading) 0 : Falling edge active 1 : Rising edge active b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) b7 b0 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit Serial I/O2 interrupt request bit Key input interrupt request bit ADT/A/D conversion interrupt request bit Not used (“0” at reading) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit b7 0 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Timer 1 interrupt enable bit INT2 interrupt enable bit Serial I/O2 interrupt enable bit Key input interrupt enable bit ADT/A/D conversion interrupt enable bit Not used (“0” at reading) (Write “0” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 19 Structure of interrupt-related registers Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 23 of 90 3826 Group (A version) Key Input Interrupt (Key-on Wake Up) The key input interrupt is enabled when any of port P2 is set to input mode and the bit corresponding to key input control register is set to “1”. A Key input interrupt request is generated by applying “L” level voltage to any pin of port P2 of which key input interrupt is en- abled. In other words, it is generated when AND of input level goes from “1” to “0”. A connection example of using a key input interrupt is shown in Figure 22, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P20–P23. Port PXx “L” level output PULL register A Bit 7 ✽ P27 output ✽ P27 key input control bit Port P27 direction register = “1” ✽✽ Port P27 latch Key input interrupt request P26 key input control bit Port P26 direction register = “1” ✽ ✽ Port P26 latch P26 output P25 key input control bit Port P25 direction register = “1” ✽ ✽✽ P25 output Port P25 latch P24 key input control bit Port P24 direction register = “1” ✽ ✽✽ P24 output Port P24 latch PULL register A Bit 6 = “1” Port P23 P23 key input control bit = “1” direction register = “0” ✽ ✽✽ P23 input Port P2 Input reading circuit Port P23 latch P22 key input control bit = “1” Port P22 direction register = “0” ✽ ✽✽ Port P22 latch P22 input P21 key input control bit = “1” Port P21 direction register = “0” ✽ ✽✽ P21 input Port P21 latch P20 key input control bit = “1” Port P20 direction register = “0” ✽ P20 input ✽✽ Port P20 latch ✽ P-channel transistor for pull-up ✽ ✽ CMOS output buffer Fig. 20 Connection example when using key input interrupt and port P2 block diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 24 of 90 3826 Group (A version) The key input interrupt is controlled by the key input control register and the port direction register. When enabling the key input interrupt, set “1” to the key input control bit. A key input can be accepted from pins set as the input mode in ports P20–P27. b7 b0 Key input control register (KIC : address 001516) P20 key input control bit P21 key input control bit P22 key input control bit P23 key input control bit P24 key input control bit P25 key input control bit P26 key input control bit P27 key input control bit 0 : Key input interrupt disabled 1 : Key input interrupt enabled Fig. 21 Structure of key input control register Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 25 of 90 3826 Group (A version) TIMERS The 3826 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Data bus Real time port control bit “1” P52/RTP0 Latch “0 ” P52 direction register P52 latch Real time port control bit “1” RTP1 data for real time port Q D P53/RTP1 Real time port control bit “0” Latch “0 ” P53 direction register RTP0 data for real time port Q D Timer X mode register write signal P53 latch “1 ” P54/CNTR0 f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer X operatCNTR0 active ing mode bits edge switch bit “00”,“01”,“11” “0 ” Timer X stop control bit Timer X (low) latch (8) S T Q Pulse width HL continuously measurement mode Rising edge detection P54 latch Pulse output mode CNTR1 active edge switch bit P55/CNTR1 Falling edge detection f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer Y stop control bit Period measurement mode Timer Y (low) latch (8) Timer Y (high) latch (8) Timer Y low-order register (8) Timer Y high-order register (8) “00”,“01”,“11” “0 ” f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer 1 count source selection bit “0 ” Timer 1 latch (8) Timer 1 register (8) XCIN “1 ” TOUT output active edge switch bit “0” P43/φ/TOUT P43 direction register TOUT/φ “1 ” output selection bit φ TOUT/φ output enable bit P43 latch Fig. 22 Timer block diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 Timer Y interrupt request “10” Timer Y operating mode bits “1 ” page 26 of 90 Timer X interrupt request Pulse output mode Q “1 ” Timer X (high) latch (8) Timer X low-order register (8) Timer X high-order register (8) “10” Pulse width “1” measurement mode CNTR0 active edge switch bit “0” P54 direction register Timer X write control bit Timer 2 count source selection bit Timer 2 latch (8) “0 ” Timer 2 register (8) “1 ” f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) Timer 2 write control bit Timer 1 interrupt request Timer 2 interrupt request TOUT/φ output enable bit Q S T Q f(XIN)/16 (f(XCIN)/16 when φ = XCIN/2) “0 ” Timer 3 latch (8) Timer 3 register (8) “1 ” Timer 3 count source selection bit Timer 3 interrupt request 3826 Group (A version) Timer X The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P54/ CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction register). ●Timer X Write Control Which write control can be selected by the timer X write control bit (bit 0) of the timer X mode register (address 002716), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer latch by writing data to the timer X register and the timer is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the latch and the timer at the same time by writing data to the timer X register. The write operation is independent of timer X count operation, operating or stopping. When the value is written in latch only, a value is simultaneously set to the timer X and the timer X latch if the writing in the highorder register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion. ●Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P5 2 and P5 3 each time the timer X underflows. (However, if the real time port control bit is changed from “0” to “1” after set of the real time port data, data are output independent of the timer X operation.) If the data for the real time port is changed while the real time port function is valid, the changed data are output at the next underflow of timer X. Before using this function, set the P52/RTP0, P53/RTP1 pins to output mode (set “1” to bits 2, 3 of port P5 direction register). (4) Pulse width measurement mode ■Note on CNTR0 interrupt active edge selection The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If CNTR 0 active edge switch bit is “0”, the timer counts while the input signal of CNTR 0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the P54/CNTR0 pin to input mode (set “0” to bit 4 of port P5 direction register). CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. Timer X is a 16-bit timer and is equipped with the timer latch. The division ratio of timer X is given by 1/(n+1), where n is the value in the timer latch. Timer X is a down-counter. When the contents of timer X reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer X interrupt request bit is set to “1”. Timer X can be selected in one of four modes by the timer X mode register and can be controlled the timer X write and the real time port. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the P54/CNTR0 pin to output mode (set “1” to bit 4 of port P5 direction register). (3) Event counter mode ●Read and write to timer X high-order, low-order registers When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-order registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is performed. •Write operation to the high- or low-order register before reading the timer X low-order register •Read operation from the high- or low-order register before writing to the timer X high-order register b7 b0 Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and timer 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid RTP0 data for real time port RTP1 data for real time port Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNT R0 active edge switch bit 0 : Count at rising edge in event counter mode Start from “H” output in pulse output mode Measure “H” pulse width in pulse width measurement mode Falling edge active for CNTR0 interrupt 1 : Count at falling edge in event counter mode Start from “L” output in pulse output mode Measure “L” pulse width in pulse width measurement mode Rising edge active for CNT R0 interrupt Timer X stop control bit 0 : Count start 1 : Count stop Fig. 23 Structure of timer X mode register Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 27 of 90 3826 Group (A version) Timer Y Timer Y is a 16-bit timer and is equipped with the timer latch. The division ratio of timer Y is given by 1/(n+1), where n is the value in the timer latch. Timer Y is a down-counter. When the contents of timer Y reach “0000 16”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the timer Y interrupt request bit is set to “1”. Timer Y can be selected in one of four modes by the timer Y mode register. (1) Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). (2) Period measurement mode CNTR1 interrupt request is generated at rising or falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Except for this, the operation in period measurement mode is the same as in timer mode. The timer value just before the reloading at rising or falling of CNTR 1 pin input signal is retained until the next valid edge is input. The rising or falling timing of CNTR 1 pin input signal can be discriminated by CNTR 1 interrupt. When using a timer in this mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). (3) Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the P55/CNTR1 pin to input mode (set “0” to bit 5 of port P5 direction register). (4) Pulse width HL continuously measurement mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the P5 5 /CNTR 1 pin to input mode (set “0” to bit 5 of port P5 direction register). ■Note on CNTR1 interrupt active edge selection CNTR1 interrupt active edge depends on the value of the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the value of CNTR1 active edge switch bit. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 28 of 90 b7 b0 Timer Y mode register (TYM : address 002816) Not used (“0” at reading) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNT R1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNT R1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop Fig. 24 Structure of timer Y mode register 3826 Group (A version) Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers and is equipped with the timer latch. The count source for each timer can be selected by the timer 123 mode register. The division ratio of each timer is given by 1/(n+1), where n is the value in the timer latch. All timers are down-counters. When the contents of the timer reach “0016”, an underflow occurs at the next count pulse and the contents of the timer latch are reloaded into the timer and the count is continued. When the timer underflows, the interrupt request bit corresponding to that timer is set to “1”. When a value is written to the timer 1 register and the timer 3 register, a value is simultaneously set as the timer latch and the timer. When the timer 1 register, the timer 2 register, or the timer 3 register is read, the count value of the timer can be read. ●Timer 2 Write Control Which write can be selected by the timer 2 write control bit (bit 2) of the timer 123 mode register (address 002916), writing data to both the latch and the timer at the same time or writing data only to the latch. When the operation “writing data only to the latch” is selected, the value is set to the timer 2 latch by writing data to the timer 2 register and the timer 2 is updated at next underflow. After reset, the operation “writing data to both the latch and the timer at the same time” is selected, and the value is set to both the timer 2 latch and the timer 2 at the same time by writing data to the timer 2 register. If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the highorder register and the underflow of timer 2 are performed at the same timing. ●Timer 2 Output Control When the timer 2 (TOUT) output is enabled by the TOUT/φ output enable bit and the TOUT/φ output selection bit, an inversion signal from the TOUT pin is output each time timer 2 underflows. In this case, set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register). ■Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 29 of 90 b7 b0 Timer 123 mode register (T123M :address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enablel bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and counter 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output signal 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output signal 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) Note: System clock φ is f(XCIN)/2 in the low-speed mode. Fig. 25 Structure of timer 123 mode register 3826 Group (A version) SERIAL INTERFACE Serial I/O1 ceiver must use the same clock as an operation clock. When an internal clock is selected as an operation clock, transmit or receive is started by a write signal to the transmit buffer register. When an external clock is selected as an operation clock, serial I/ O1 becomes the state where transmit or receive can be performed by a write signal to the transmit buffer register. Transmit and receive are started by input of an external clock. Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O mode, the transmitter and the re- Data bus Address 001816 Receive buffer register Serial I/O1 control register Receive interrupt request Receive shift register P44/RXD Address 001A16 Receive buffer full flag (RBF) Shift clock Receive clock control circuit P46/SCL K1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit XIN Baud rate generator P47/SRDY1 Transmit clock control circuit Falling-edge detector F/F 1/4 Address 001C16 1/4 Shift clock P45/TXD Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request Transmit shift register Transmit buffer empty flag (TBE) Address 001916 Transmit buffer reg ister Address 001816 Data bus Serial I/O1 status register Fig. 26 Block diagram of clock synchronous serial I/O1 Transmit and receive shift clock (1/2 to 1/2048 of the internal clock, or an external clock) (Note 1) Serial output TXD D0 D1 D2 D3 D4 D5 D6 D7 Serial input RXD D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write signal to receive/transmit buffer register (address 001816) TBE = “0” TBE = “1” (Note 3) TSC = “0” (Note 2) RBF = “1” (Note 4) TSC = “1” (Note 3) Overrun error (OE) detection Notes 1 : After data transferring, the TxD pin keeps D7 output value. 2 : If data is written to the transmit buffer register when TSC = “0”, the transmit clock is generated continuously and serial data can be output continuously from the T XD pin. 3 : Select the serial I/O1 transmit interrupt request factor between when the transmit buffer register has emptied (TBE = “1”) or after the transmit shift operation has ended (T SC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 4 : T he serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”. Fig. 27 Operation of clock synchronous serial I/O1 function Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 30 of 90 3826 Group (A version) ter, but the two buffers have the same address (0018 16 ) in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted during transmitting, and the receive buffer register can hold received one-byte data while the next one-byte data is being received. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) is selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- Data bus Address 001816 P44/RXD Serial I/O1 control register Address 001A16 OE Receive buffer register Character length selection bit STdetector 7 bits Receive shift register Receive buffer full flag (RBF) Receive interrupt request 1/16 8 bits UART control register Address 001B16 SP detector PE FE Clock control circuit Serial I/O1 synchronization clock selection bit P46/SCL K1 BRG count source selection bit Frequency division ratio 1/(n+1) XI N Baud rate generator Address 001C16 1/4 ST/SP/PA generator Transmit shift register shift completion flag (TSC) 1/16 P45/TXD Transmit shift register Character length selection bit Transmit buffer register Address 001816 Transmit interrupt source selection bit Transmit interrupt request Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 28 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer register write signal TBE = “0” TSC = “0” TBE = “1” Serial output TxD ST TBE = “0” TSC = “1”✽ TBE = “1” D0 D1 SP ST D0 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer register read signal ✽ Generated (Notes 1, 2) RBF = “1” Serial input RxD ST D0 D1 D1 SP ST SP at 2nd bit in 2-stop-bit mode RBF = “0” D0 D1 Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit for reception). 2 : T he serial I/O1 receive interrupt request occurs when the receive buffer full flag (RBF) becomes “1”. 3 : Select the serial I/O1 transmit interrupt request occurrence factor between when the transmit buffer register has emptied (TBE = “1”) or after the transmit shift operation has ended (T SC = “1”), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. Fig. 29 Operation of UART serial I/O1 function Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 31 of 90 (Notes 1, 2) RBF = “1” SP 3826 Group (A version) [Transmit Buffer/Receive Buffer Register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer register is writeonly and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer register is “0”. [Serial I/O1 Status Register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is set to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set to “1”. A write signal to the serial I/O1 status register sets all the error flags (OE, PE, FE, and SE) (bit 3 to bit 6, respectively) to “0”. Writing “0” to the serial I/O1 enable bit (SIOE) also sets all the status flags to “0”, including the error flags. All bits of the serial I/O1 status register are set to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift register shift completion flag and the transmit buffer empty flag become “1”. [Serial I/O1 Control Register (SIO1CON)] 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. [UART Control Register (UARTCON)] 001B16 The UART control register consists of the bits which set the data format of an data transmit and receive, and the bit which sets the output structure of the P45/TXD pin. [Baud Rate Generator (BRG)] 001C16 The baud rate generator is the 8-bit counter equipped with a reload register. Set the division value of the BRG count source to the baud rate generator. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. ■Notes on serial I/O When setting the transmit enable bit to “1”, the serial I/O1 transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronous with the transmission enabled, take the following sequence. ➀Set the serial I/O1 transmit interrupt enable bit to “0” (disabled). ➁Set the transmit enable bit to “1”. ➂Set the serial I/O1 transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 32 of 90 3826 Group (A version) b7 b7 b0 Serial I/O1 status register (SIO1STS : address 001916) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. Overrun error flag (OE) 0: No error 1: Overrun error SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinary I/O pin 1: P47 pin operates as SRDY1 output pin Parity error flag (PE) 0: No error 1: Parity error Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Framing error flag (FE) 0: No error 1: Framing error Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Summing error flag (SE) 0: (OE) U (PE) U (FE) =0 1: (OE) U (PE) U (FE) =1 Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Not used (“1” at reading) Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O b0 UART control regi ster (UART CON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (ST PS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (“1” at reading) Fig. 30 Structure of serial I/O1 control registers Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 33 of 90 Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44–P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44–P47 operate as serial I/O pins) 3826 Group (A version) b7 Serial I/O2 b0 Serial I/O2 control register (SIO2CON : address 001D16) Serial I/O2 can be used only for clock synchronous serial I/O. For serial I/O2, the transmitter and the receiver must use the same clock as a synchronous clock. When an internal clock is selected as a synchronous clock, the serial I/O2 is initialized and, transmit and receive is started by a write signal to the serial I/O2 register. When an external clock is selected as an synchronous clock, the serial I/O2 counter is initialized by a write signal to the serial I/O2 register, serial I/O2 becomes the state where transmission or reception can be performed. Write to the serial I/O2 register while SCLK21 is “H” state when an external clock is selected as an synchronous clock. Either P62/SCLK21 or P63/SCLK22 pin can be selected as an output pin of the synchronous clock. In this case, the pin that is not selected as an output pin of the synchronous clock functions as a I/ O port. Internal synchronous clock select bits b2 b1 b0 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: Do not select 1 0 1: 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK21/SCLK22 signal output P61/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) [Serial I/O2 Control Register (SIO2CON)] 001D16 Transfer direction selection bit 0: LSB first 1: MSB first The serial I/O2 control register contains eight control bits for the serial I/O2 functions. After setting to this register, write data to the serial I/O2 register and start transmit and receive. Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock Synchronous clock output pin selection bit 0: SCLK21 1: SCLK22 Fig. 31 Structure of serial I/O2 control register 1/8 1/16 1/32 Divider XIN Internal synchronous clock select bits Data bus 1/64 1/128 1/256 P63 latch (Note) Serial I/O2 synchronous clock selection bit P63/SCLK22 “1 ” SCLK2 Synchronous circuit “0 ” External clock P62 latch “0 ” P62/SCLK21 (Note) “1” Serial I/O2 counter (3) P61 latch “0 ” P61/SOUT2 “1 ” Serial I/O2 port selection bit P60/SIN2 Serial I/O 2 register (8) Note: It is selected by the serial I/O2 synchronous clock selection bit, the synchronous clock output pin selection bit, and the serial I/O2 port selection bit. Fig. 32 Block diagram of serial I/O2 function Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 34 of 90 Serial I/O2 interrupt request 3826 Group (A version) ●Serial I/O2 Operating The serial I/O2 counter is initialized to “7” by writing to the serial I/O2 register. After writing, whenever a synchronous clock changes from “H” to “L”, data is output from the SOUT2 pin. Moreover, whenever a synchronous clock changes from “L” to “H”, data is taken in from the SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out simultaneously. When the internal clock is selected as a synchronous clock, it is as follows if a synchronous clock is counted 8 times. •Serial I/O2 counter = “0” •Synchronous clock stops in “H” state •Serial I/O2 interrupt request bit = “1” The SOUT2 pin is in a high impedance state after transfer is completed. When the external clock is selected as a synchronous clock, if a synchronous clock is counted 8 times, the serial I/O2 interrupt request bit is set to “1”, and the SOUT2 pin holds the output level of D7. However, if a synchronous clock continues being input, the shift of the serial I/O2 register is continued and transmission data continues being output from the SOUT2 pin. Synchronous clock (Note 1) Serial I/O2 register write signal (Notes 2, 3) Serial I/O2 output SOUT2 D0 D1 D2 D3 D4 D5 D6 D7 Serial I/O2 input SIN2 Serial I/O2 interrupt request bit = “1” Notes 1: When the internal clock is selected as the synchronous clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the synchronous clock, the SOUT2 pin goes to high impedance after transfer completion. 3: When the external clock is selected as the synchronous clock, the SOUT2 pin keeps D7 output level after transfer completion. However, if synchronous clocks input are carried on, the transmit data will be output continuously from the SOUT2 pin because shifts of serial I/O2 shift register is continued as long as synchronous clocks are input. Fig. 33 Timing of serial I/O2 function Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 35 of 90 3826 Group (A version) PULSE WIDTH MODULATION (PWM) PWM Operation The 3826 group has a PWM function with an 8-bit resolution, using f(XIN) or f(XIN)/2 as a count source. When either bit 1 (PWM0 function enable bit) or bit 2 (PWM1 function enable bit) of the PWM control register or both bits are enabled, operation starts from initializing status, and pulses are output starting at “H”. When one PWM output is enabled and that the other PWM output is enabled, PWM output which is enabled to output later starts pulse output from halfway of PWM period (see Figure 37). When the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Data Setting The PWM output pins are shared with ports P50 and P51. Set the PWM period by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If PWM count source is f(XIN) and the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ✕ (n+1)/f(XIN) = 31.875 ✕ (n+1) µs (when f(XIN) = 8 MHz) Output pulse “H” period = PWM period ✕ m/255 = 0.125 ✕ (n+1) ✕ m µs (when f(XIN) = 8 MHz) 31.875 ✕ m ✕ (n+1) µs 255 PWM output T = [31.875 ✕ (n+1)] µs m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when f(X IN ) = 8 MHz) Fig. 34 Timing of PWM cycle Data bus PWM prescaler pre-latch PWM register pre-latch PWM1 function enable bit Transfer control circuit PWM prescaler latch PWM register latch Port P51 lacth P51 /PWM1 Count source selection bit “0” PWM prescaler XIN 1/2 PWM circuit P50 /PWM0 “1” Port P50 lacth PWM0 function enable bit Fig. 35 Block diagram of PWM function Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 36 of 90 3826 Group (A version) b0 b7 PWM control register (PWMCON : address 002B16) Count source selection bit 0 : f(XIN) 1 : f(XIN)/2 PWM0 function enable bit 0 : PWM0 disabled 1 : PWM0 enabled PWM1 function enable bit 0 : PWM1 disabled 1 : PWM1 enabled Not used (“0” at reading) Fig. 36 Structure of PWM control register A PWM (internal) C B B = C T2 T stop stop T T T2 Port PWM 0 output PWM 1 output Port Port Port PWM register write signal (Changes from “A” to “B” during “H” period) PWM prescaler write signal (Changes from “T” to “T2” during PWM period) PWM 0 function enable bit PWM 1 function enable bit When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. Fig. 37 PWM output timing when PWM register or PWM prescaler is changed Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 37 of 90 3826 Group (A version) A/D CONVERTER [AD Conversion Low-Order Register (ADL)] 001416 [AD Conversion High-Order Register (ADH)] 003516 The AD conversion registers are read-only registers that store the result of an A/D conversion. When reading this register during an A/D conversion, the previous conversion result is read. The high-order 8 bits of a conversion result is stored in the AD conversion high-order register (address 003516), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the AD conversion low-order register (address 001416). Bit 0 of the AD conversion low-order register is the conversion mode selection bit. When this bit is set to “0”, that becomes the 10-bit A/D mode. When this bit is set to “1”, that becomes the 8-bit A/D mode. Comparator and Control Circuit The comparator and control circuit compare an analog input voltage with the comparison voltage and store the result in the AD conversion register. When an A/D conversion is completed, the control circuit sets the AD conversion completion bit and the A/D conversion interrupt request bit to “1”. Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A/D conversion. Use the clock divided from the main clock f(XIN) as the system clock φ. b7 b0 AD control register (ADCON : address 003416) Analog input pin selection bits b2b1b0 0 0 0 0 1 1 1 1 [AD Control Register (ADCON)] 003416 The AD control register controls the A/D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 indicates the completion of an A/D conversion. The value of this bit remains at “0” during an A/D conversion, then it is set to “1” when the A/D conversion is completed. Writing “0” to this bit starts the A/D conversion. Bit 4 is the VREF input switch bit which controls connection of the resistor ladder and the reference voltage input pin (VREF). The resistor ladder is always connected to VREF when bit 4 is set to “1”. When bit 4 is set to “0”, the resistor ladder is cut off from VREF except for A/D conversion performed. When bit 5, which is the AD external trigger valid bit, is set to “1”, A/D conversion starts also by a falling edge of an ADT input. When using an A/D external trigger, set the P57/ADT pin to input mode (set “0” to bit 7 of port P5 direction register). 0 0 1 1 0 0 1 1 0 : P60/AN0 1 : P61/AN1 0 : P62/AN2 1 : P63/AN3 0 : P64/AN4 1 : P65/AN5 0 : P66/AN6 1 : P67/AN7 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed VREF input switch bit 0 : AUTO 1 : ON AD external trigger valid bit 0 : A/D external trigger invalid 1 : A/D external trigger valid Interrupt source selection bit 0 : Interrupt request at AD conversion completed 1 : Interrupt request at ADT input falling Not used (“0” at reading) Comparison Voltage Generator The comparison voltage generator divides the voltage between AVSS and VREF by 256 (when 8-bit A/D mode) or 1024 (when 10bit A/D mode), and outputs the divided voltages. b7 b0 AD conversion low-order register (ADL : address 001416) Conversion mode selection bit 0 : 10-bit A/D mode 1 : 8-bit A/D mode Channel Selector The channel selector selects one of the input ports P6 7/AN7–P60/AN0. Not used (“0” at reading) •For 10-bit A/D mode A/D conversion result •For 8-bit A/D mode Not used (undefined at reading) Fig. 38 Structure of A/D converter-related registers Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 38 of 90 3826 Group (A version) •10-bit reading (Read address 003516, then 001416) b0 b7 AD conversion high-order register (ADH: Address 003516) AD conversion low-order register (ADL: Address 001416) b9 b8 b7 b6 b5 b4 b3 b2 (high-order) b0 b7 (low-order) b1 b0 Conversion mode selection bit 0 : 10-bit A/D mode 1 : 8-bit A/D mode Note : Bits 0 to 5 of address 001416 become “0” at reading. •8-bit reading (Read only address 003516) b7 AD conversion high-order register (ADH: Address 0035 ) b0 b7 b6 b5 b4 b3 b2 b1 b0 Fig. 39 Read of AD conversion register Data bus AD control register b 0 b 7 P57/ADT/DA2 3 P62/SCLK21/AN2 P63/SCLK22/AN3 P64/AN4 P65/AN5 Channel selector P60/SIN2/AN0 P61/SOUT2/AN1 ADT/A/D interrupt request A/D control circuit Comparator AD conversion low-order register AD conversion high-order register (Address 003516) 8 Resistor ladder P66/AN6 P67/AN7 AVSS VRE F Fig. 40 A/D converter block diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 39 of 90 (Address 001416) 3826 Group (A version) D/A Converter b0 b7 The 3826 group has a D/A converter with 8-bit resolution and 2 channels (DA1, DA2). The D/A converter is started by setting the DTMF/DA1 selection bit and the CTCSS/DA2 selection bit to “0” and setting the value in the DA conversion register. When the DTMF/DA1 output enable bit and the CTCSS/DA2 output enable bit is set to “1”, the result of D/ A conversion is output from the corresponding DA1 pin or DA2 pin. When using the D/A converter, set the P56/DA1 pin and the P57/ DA2 pin to input mode (set “0” to bits 6, 7 of port P5 direction register) and the pull-up resistor should be in the OFF state previously. The output analog voltage V is determined by the value n (base 10) in the DA conversion register as follows: DA control register (DACON : address 003616) DTM F/DA1 output enable bit 0 : Disabled 1 : Enabled CTCSS/DA2 output enable bit 0 : Disabled 1 : Enabled DTMF/DA1 selection bit 0 : DA1 function 1 : DTMF function CTCSS/DA2 selection bit 0 : DA2 function 1 : CTCSS function V=VREF ✕ n/256 (n=0 to 255) Where VREF is the reference voltage. Low group ROM data selection bit 0 : Sine wave 1 : “0” fixed At reset, the DA conversion registers are set to “0016”, the DTMF/ DA1 output enable bit and the CTCSS/DA2 output enable bit are set to “0”, and the P56/DA1 pin and the P57/DA2 pin goes to high impedance state. The D/A converter is not buffered, so connect an external buffer when driving a low-impedance load. High group ROM data selection bit 0 : Sine wave 1 : “0” fixed High/Low group timer write control bit 0 : Write value in latch only 1 : Write value in latch and counter ■ Note on applied voltage to VREF pin When the P56/DA1 pin and the P57/DA2 pin are used as an I/O port, be sure to apply Vcc to VREF pin. When these pins are used as D/A conversion output pins, the Vcc level is recommended for the applied voltage to VREF pin. When the voltage below Vcc level is applied, the D/A conversion accuracy may be worse. CTCSS timer write control bit 0 : Write value in latch only 1 : Write value in latch and counter Fig. 41 Structure of DA control register DA1 output enable bit R-2R resistor ladder Data bus P56/DA1 8-bit timer High group ROM 5bit ✕ 32 10-bit timer 5-bit adder Selector XIN/2 Selector 8-bit timer Selector DA1 conversion register (8) Low group ROM 5bit ✕ 32 CTCSS ROM 8bit ✕ 64 * Selector Selector DA2 conversion register (8) P57/DA2 * When DTMF is selected, the high-order 6 bits are automatically set as the DTMF output. The low-order 2 bits is set by writing data to the D-A1 conversion register. R-2R resistor ladder DA2 output enable bit Fig. 42 Block diagram of D/A converter Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 40 of 90 Data bus 3826 Group (A version) DTMF Function (Dual Tone Multi Frequency) The digital value for one period of high group and low group output is shown in Figure 43. DTMF output is automatically input to high-order 6 bits of the D/A1 conversion register as 6-bit D/A data. The low-order 2 bits of the D/A1 conversion register are fixed to the value written in the D/A1 conversion register. Moreover, only the sine wave of high group can be output by setting “1” to the bit 4 of the D/A control register. By setting “1” to the bit 5 of the D/A control register similarly, only the sine wave of low group can be output. Writing to the DTMF high group timer and the DTMF low group timer can also be changed to “writing to latch and timer simultaneously” by setting “1” to the bit 6 of the D/A con trol register. “Writing to only latch” is set after reset release. If the D/A1 conversion register is read when the DTMF function is selected,the digital value of DTMF output can be read. DTMF function is used to output the result which generated automatically the waveform of sine wave of two kinds of different frequency, and added two kinds of this sine wave as an analog value. DTMF output waveform can be output from DA1 pin. DTMF waveform is output by setting “1” (enabled) to the DTMF/DA1 output enable bit (bit 0 of address 003616), and setting “1” to the DTMF/ DA1 selection bit (bit 2 of address 003616). At this time, set “0” (input state) to the direction register of ports P56/DA1 pin and pull-up resistor to be OFF state. In order to set two kinds of frequency which generates DTMF waveform, write a value in the DTMF high group timer and the DTMF low group timer, respectively. The value written in each above-mentioned timer is n, the sine wave of the following frequency can be generated. f= f(XIN)/2 (Hz) (n+1) ✕ 32 DA data of low group waveform (1 period) for DTMF DA1 value (8bit)* DA1 value (8bit)* Set “0616” or more to the DTMF high group timer and the DTMF low group timer. After reset release, “0616” is automatically set to them. 7816 DA data of high group waveform (1 period) for DTMF 7816 6416 6416 5016 5016 3C16 3C16 2816 2816 1416 1416 016 0 5 10 15 20 Conversion time of low group ROM 25 30 016 0 5 10 15 20 Conversion time of high group ROM * This is the value set to DA1 conversion register when the low-order 2 bits are “0”. Fig. 43 Waveform data of high group and low group Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 41 of 90 25 30 3826 Group (A version) 1209Hz (2) High group frequency • 1209 Hz • 1336 Hz • 1477 Hz • 1633 Hz Table 9 shows the example of frequency accuracy (at f(XIN)=4 MHz). Table 9 Example of frequency accuracy (at f(XIN) = 4 MHz) Rating frequency (Hz) 697 770 852 941 1209 1336 1477 1633 Rev.2.00 May. 24, 2006 REJ03B0028-0200 n (Timer value) 89 80 72 65 51 46 41 37 page 42 of 90 3 6 9 # A B C D 1633Hz (1) Low group frequency • 697 Hz • 770 Hz • 852 Hz • 941 Hz 2 5 8 0 1477Hz 1 4 7 * Low group frequency and high group frequency are as follows. 1336Hz L o w G r o u p t F r e q u e n c y, H i g h G r o u p Frequency 697Hz 770Hz 852Hz Low group frequency 941Hz High group frequency Fig. 44 Key matrix of telephone and rating frequency Output frequency (Hz) 694.4 771.6 856.2 946.9 1201.9 1329.7 1488.1 1644.7 Error frequency (Hz) –2.6 1.6 4.2 5.9 –7.1 –6.3 11.1 11.7 Deviation (%) –0.367 0.208 0.488 0.630 –0.580 –0.460 0.750 0.720 3826 Group (A version) CTCSS Function (Continuous Tone-Controlled Squelch System) When reading a value from the CTCSS timer, read the high-order byte first. By the value written in the CTCSS timer is n, the sine wave of the following frequency is generated. The CTCSS function is used to generate the sine wave of single frequency automatically. The CTCSS output waveform can be output from DA2 pin. CTCSS waveform is outputted by setting “1” to the CTCSS/DA2 output enable bit (bit 1 of address 003616), and setting “1” to the CTCSS/DA 2 selection bit (bit 3 of address 003616). In order to set the frequency of CTCSS output, value is written in the CTCSS timer. The CTCSS timer consists of a 10-bit timer. When writing a value to the CTCSS timer, write the low-order byte first. f= f (XIN)/2 (Hz) (n+1) ✕ 64 Set “006 16” or more to the CTCSS timer. “0016” is automatically set to the high-order of the CTCSS timer and “0616” is automatically set to the low-order of the CTCSS timer after reset release. The amplitude of CTCSS output is obtained by the following formula. C= Vcc 2 If the D/A2 conversion register is read when the CTCSS function is selected, the digital value of CTCSS output can be read. Table 10 shows the example of frequency accuracy (at f(XIN ) = 4 MHz). Table 10 Example of frequency accuracy (at f(XIN) = 4 MHz) n (Timer value) Rating frequency (Hz) Output frequency (Hz)] 465 67.0 67.06 405 77.0 76.97 352 88.5 88.53 312 100.0 99.84 291 107.2 107.02 271 114.8 114.89 253 123.0 123.03 236 131.8 131.86 220 141.3 141.40 205 151.4 151.70 192 162.2 161.92 179 173.8 173.61 167 186.2 186.01 153 203.5 202.92 142 218.1 218.53 133 233.6 233.20 124 250.3 250.00 “0” DAi output enable bit R DAi R R “1” 2R 2R “0” “1” AVSS VREF Fig. 45 Equivalent connection circuit of D/A converter Rev.2.00 May. 24, 2006 REJ03B0028-0200 R 2R R 2R R 2R Deviation (%) 0.089 –0.038 0.030 –0.160 –0.167 0.078 0.026 0.043 0.073 0.198 –0.174 –0.109 –0.101 –0.284 0.198 –0.167 –0.120 R 2R 2R 2R LSB MSB DAi conversion register 2R Error frequency (Hz) 0.06 –0.03 0.027 –0.16 –0.18 0.09 0.03 0.06 0.10 0.30 –0.28 –0.19 –0.19 –0.58 0.43 –0.39 –0.30 page 43 of 90 3826 Group (A version) enable bit is set to “1” (LCD ON) after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. LCD DRIVE CONTROL CIRCUIT The 3826 group has the Liquid Crystal Display (LCD) drive control circuit consisting of the following. LCD display RAM Segment output enable register LCD mode register Voltage multiplier Selector Timing controller Common driver Segment driver Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD • • • • • • • • • b7 Table 9 Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 80 dots or 8 segment LCD 10 digits 120 dots or 8 segment LCD 15 digits 160 dots or 8 segment LCD 20 digits b0 Segment output enable register (SEG : address 003816) 0 Segment output enable bit 0 0 : Output ports P30–P35 1 : Segment output SEG18–SEG23 Segment output enable bit 1 0 : Output ports P36, P37 1 : Segment output SEG24,SEG25 Segment output enable bit 2 0 : I/O ports P00–P05 1 : Segment output SEG26–SEG31 Segment output enable bit 3 0 : I/O ports P06,P07 1 : Segment output SEG32,SEG33 Segment output enable bit 4 0 : I/O port P10 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P11–P15 1 : Segment output SEG35–SEG39 LCD output enable bit 0 : Disabled 1 : Enabled Not used (“0” at reading) (Write “0” to this bit at writing.) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits b1b0 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0–COM2) 1 1 : 4 duty (use COM0–COM3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disable 1 : Voltage multiplier enable LCD circuit divider division ratio selection bits b6b5 0 0 : Clock input 0 1 : 2 division of Clock input 1 0 : 4 division of Clock input 1 1 : 8 division of Clock input LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Note : LCDCK is a clock for a LCD timing controller. Fig. 46 Structure of segment output enable register and LCD mode register Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 44 of 90 3826 Group (A version) page 45 of 90 Fig. 47 Block diagram of LCD controller/driver Rev.2.00 May. 24, 2006 REJ03B0028-0200 Data bus LCD enable bit Address 004016 Address 005316 Address 004116 Duty ratio selection bits LCD display RAM LCD circuit divider division ratio selection bits 2 2 Voltage multiplier control bit Selector Selector Selector Selector LCD divider Bias control bit “1” Selector Selector Timing controller Level shift Level shift Level shift Level shift Level shift Level shift Level Shift Bias control Level Shift Level Shift LCDCK Level Shift VCC Segment Segment Segment Segment driver driver driver driver SEG0 SEG1 SEG2 SEG3 LCDCK count source selection bit “0” f(XCIN)/ 32 Segment Segment driver driver P30/SEG18 P14/SEG38 P15/SEG39 LCD output Common Common Common Common enable bit driver VSS VL1 VL2 VL3 C1 C2 driver driver driver COM0 COM1 COM2 COM3 f(XIN)/8192 (f(XCIN)/8192 in lowspeed mode) 3826 Group (A version) Voltage Multiplier (3 Times) Bias Control and Applied Voltage to LCD Power Input Pins The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. Set each bit of the segment output enable register and the LCD mode register in the following order for operating the voltage multiplier. 1. Set the segment output enable bits (bits 0 to 5) of the segment output enable register to “0” or “1”. 2. Set the duty ratio selection bits (bits 0 and 1), the bias control bit (bit 2), the LCD circuit divider division ratio selection bits (bits 5 and 6), and the LCDCK count source selection bit (bit 7) of the LCD mode register to “0” or “1”. 3. Set the LCD output enable bit (bit 6) of the segment output enable register to “1” (enabled). Apply the limit voltage or less to the VL1 pin. 4. Set the voltage multiplier control bit (bit 4) of the LCD mode register to “1” (voltage multiplier enabled). However, be sure to select 1/3 bias for bias control. When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. To the LCD power input pins (VL1–VL3), apply the voltage shown in Table 10 according to the bias value. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Table 10 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias 1/2 bias Voltage value VL3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD Note : V LCD is the maximum value of supplied voltage for the LCD panel. ■Notes on Voltage Multiplier When using the voltage multiplier, apply the limit voltage or less to the VL1 pin, then set the voltage multiplier control bit to “1” (enabled). When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins (VL1–VL3). When the LCD output enable bit is set to “0” (disabled) (during reset is included), the VL3 pin is connected to VCC inside of this microcomputer. When the voltage exceeding VCC is applied to VL3, apply VL3 voltage after setting the LCD output enable bit to “1” (enabled). VCC VCC Contrast control VL3 VL3 Contrast control VL3 R4 R1 VL2 VL2 C2 C2 VL2 Open C2 Open C1 Open R2 C1 C1 VL1 VL1 1/3 bias when using the voltage multiplier Open VL1 1/3 bias when not using the voltage multiplier 1/2 bias R3 R1 = R2 = R3 Fig. 48 Example of circuit at each bias Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 46 of 90 R5 R4 = R5 3826 Group (A version) Common Pin and Duty Ratio Control LCD Display RAM The common pins (COM 0–COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). After reset, the VCC (VL3) voltage is output from the common pins. Addresses 004016 to 005316 are the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The frequency of internal signal LCDCK decided LCD drive timing and the frame frequency can be determined with the following equation: Table 11 Duty ratio control and common pins used Duty ratio Duty ratio selection bits 2 Bit 1 0 Bit 0 1 3 4 1 1 0 1 Common pins used COM0, COM1 (Note 1) COM0–COM2 (Note 2) COM0–COM3 f(LCDCK)= Notes 1: COM2 and COM3 are open. 2: COM3 is open. (frequency of count source for LCDCK) (divider division ratio for LCD) Frame frequency= f(LCDCK) duty ratio Segment Signal Output Pins Segment signal output pins are classified into the segment-only pins (SEG 0–SEG17), the segment or output port pins (SEG18– SEG25), and the segment or I/O port pins (SEG26–SEG39). Segment signals are output according to the bit data of the LCD RAM corresponding to the duty ratio. After reset, a VCC (=VL3) voltage is output to the segment-only pins and the segment/output port pins are the high impedance condition and pulled up to VCC (=VL3) voltage. Also, the segment/I/O port pins (SEG26–SEG39) are set to input mode as I/O ports, and VCC (=VL3) is applied to them by pull-up resistor. Bit 7 6 5 4 3 2 1 0 Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 Fig. 49 LCD display RAM map Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 47 of 90 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 SEG1 SEG0 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG9 SEG8 SEG11 SEG10 SEG13 SEG12 SEG15 SEG14 SEG17 SEG16 SEG19 SEG18 SEG21 SEG20 SEG23 SEG22 SEG25 SEG24 SEG27 SEG26 SEG29 SEG28 SEG31 SEG30 SEG33 SEG32 SEG35 SEG34 SEG37 SEG36 SEG39 SEG38 3826 Group (A version) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS COM0 COM1 COM2 COM3 VL3 VSS SEG0 OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2=VL1 VSS COM0 COM1 COM2 VL3 VSS SEG0 ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2=VL1 VSS COM0 COM1 VL3 VSS SEG0 ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 50 LCD drive waveform (1/2 bias) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 48 of 90 3826 Group (A version) Internal signal LCDCK timing 1/4 duty Voltage level VL3 VL2 VL1 VSS COM0 COM1 COM2 COM3 VL3 SEG0 VSS OFF COM3 ON COM2 COM1 OFF COM0 COM3 ON COM2 COM1 COM0 1/3 duty VL3 VL2 VL1 VSS COM0 COM1 COM2 VL3 SEG0 VSS ON OFF COM0 COM2 ON COM1 OFF COM0 COM2 ON COM1 OFF COM0 COM2 1/2 duty VL3 VL2 VL1 VSS COM0 COM1 VL3 SEG0 VSS ON OFF ON OFF ON OFF ON OFF COM1 COM0 COM1 COM0 COM1 COM0 COM1 COM0 Fig. 51 LCD drive waveform (1/3 bias) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 49 of 90 3826 Group (A version) ● value of high-order 6-bit counter ● value of STP instruction disable bit ● value of count source selection bit. Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 6bit watchdog timer H. At reset or writing to the watchdog timer control register (address 0037 16), the watchdog timer is set to “3FFF16”. When any data is not written to the watchdog timer control register (address 003716) after reset, the watchdog timer is stopped. The watchdog timer starts to count down from “3FFF16” by writing to the watchdog timer control register and an internal reset occurs at an underflow. Accordingly, when using the watchdog timer function, write the watchdog timer control register before an underflow. The watchdog timer does not function when writing to the watchdog timer control register has not been done after reset. When not using the watchdog timer, do not write to it. When the watchdog timer control register is read, the following values are read: Data bus “FF16” is set when watchdog timer is written to. XCIN “1” Internal system clock selection bit “0” (Note) 1/16 When the STP instruction disable bit is “0”, the STP instruction is enabled. The STP instruction is disabled when this bit is set to “1”. If the STP instruction which is disabled is executed, it is processed as an undefined instruction, so that a reset occurs internally. This bit can be set to “1” but cannot be set to “0” by program. This bit is “0” after reset. When the watchdog timer H count source selection bit is “0”, the detection time is set to 8.19 s at f(XCIN) = 32 kHz and 32.768 ms at f(XIN) = 8 MHz. When the watchdog timer H count source selection bit is “0”, the detection time is set to 32 ms at f(XCIN) = 32 kHz and 128 µs at f(XIN) = 8 MHz. There is no difference in the detection time between the middle-speed mode and the high-speed mode. Watchdog timer L (8) Watchdog timer H count source selection bit “0” “1” Watchdog timer H (6) “3F16” is set when watchdog timer is written to. XIN Undefined instruction Reset STP instruction disable bit STP instruction Reset circuit Internal reset RESET Reset release time wait Note: This is the bit 7 of CPU mode register and is used to switch the middle-/high-speed mode and low-speed mode. Fig. 52 Block diagram of watchdog timer b7 b0 Watchdog timer register (WDTCON: address 003716) Watchdog timer H (for read-out of high-order 6 bit) “3FFF16” is set to the watchdog timer by writing values to this address. STP instruction disable bit 0 : STP instruction enabled 1 : STP instruction disabled Watchdog timer H count source selecion bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 or f(XCIN)/16 Fig. 53 Structure of watchdog timer control register f(XIN) Approx. 1 ms (f(XIN) = 8 MHZ) Internal reset signal Watchdog timer detection Fig. 54 Timing of reset output Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 50 of 90 3826 Group (A version) TOUT/φ OUTPUT FUNCTION The system clock φ or timer 2 divided by 2 (TOUT output) can be output from port P43 by setting the TOUT/φ output enable bit of the timer 123 mode register and the TOUT/φ output control register. Set the P43/φ/TOUT pin to output mode (set “1” to bit 3 of port P4 direction register) when outputting TOUT/φ. b7 b0 TOUT/φ output control register (CKOUT : address 002A16) TOUT/φ output control bit 0 : System clock φ output 1 : TOUT output Not used (“0” at reading) b7 b0 Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : Start at “H” output 1 : Start at “L” output TOUT/φ output enable bit 0 : TOUT/φ output disabled 1 : TOUT/φ output enabled Timer 2 write control bit 0 : Write data in latch and timer 1 : Write data in latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bit 0 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 1 : f(XCIN) Not used (“0” at reading) φ output-related registers Fig. 55 Structure of TOUT/φ Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 51 of 90 3826 Group (A version) RESET CIRCUIT When the power source voltage is within limits, and main clock XIN-XOUT is stable, or a stabilized clock is input to the XIN pin, if the RESET pin is held at an “L” level for 2 µs or more, the microcomputer is in an internal reset state. Then the RESET pin is returned to an “H” level, reset is released after approximate 8200 cycles of f(XIN), the program in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.2 VCC(min.) for the power source voltage of VCC(min.). *V CC (min.) = Minimum value of power supply voltage limits applied to VCC pin (Note) VCC 0V VCC RESET RESET VCC RESET Power source voltage detection circuit 0.2VCC level 2 µs 0V X IN 0V Power on Oscillation stabilized Note: Reset release voltage Vcc = Vcc (min.) Fig. 56 Example of reset circuit XI N System clock φ RESET Internal reset Reset address from vector table Address Undefined Undefined Undefined Undefined FFFC FFFD ADL Data ADH, ADL ADH SYNC XIN : Approx. 8200 cycles Fig. 57 Reset Sequence Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 52 of 90 Note : The frequency of system clock φ is f(XIN) divided by 8. 3826 Group (A version) Address Register contents Address Register contents 0016 (29) CTCSS timer (low-order) 002E16 0616 000316 0016 (30) CTCSS timer (high-order) 002F16 0016 Port P2 direction register 000516 0016 (31) DTMF high group timer 003016 0616 (4) Port P3 output control register 000716 0016 (32) DTMF low group timer 003116 0616 (5) Port P4 direction register 000916 0016 (33) DA1 conversion register 003216 0016 (6) 0016 (1) Port P0 direction register 000116 (2) Port P1 direction register (3) Port P5 direction register 000B16 0016 (34) DA2 conversion register 003316 (7) Port P6 direction register 000D16 0016 (35) AD control register 003416 0 0 0 0 1 0 0 0 (8) Port P7 direction register 000F16 0016 (36) DA control register 003616 (9) AD conversion low-order register 001416 ✕ ✕ 0 0 0 0 0 1 (37) Watchdog timer control register 003716 0 0 1 1 1 1 1 1 (10) Key input control register 001516 0016 (38) Segment output enable register 003816 0016 (11) PULL register A 001616 3F16 (39) LCD mode register 003916 0016 (12) PULL register B 001716 0016 (40) Interrupt edge selection register 003A16 0016 0016 (13) Serial I/O1 status register 001916 1 0 0 0 0 0 0 0 (41) CPU mode register 003B16 0 1 0 0 1 0 0 0 (14) Serial I/O1 control register 001A16 (42) Interrupt request register 1 003C16 0016 (15) UART control register 001B16 1 1 1 0 0 0 0 0 (43) Interrupt request register 2 003D16 0016 (16) Serial I/O2 control register 001D16 0016 (44) Interrupt control register 1 003E16 0016 (17) Timer X low-order register 002016 FF16 (45) Interrupt control register 2 003F16 0016 (18) Timer X high-order register 002116 FF16 (46) Processor status register (19) Timer Y low-order register 002216 FF16 (47) Program counter (20) Timer Y high-order register 002316 FF16 (21) Timer 1 register 002416 FF16 (48) Watchdog timer (high-order) 3F16 (22) Timer 2 register 002516 0116 (49) Watchdog timer (low-order) FF16 (23) Timer 3 register 002616 FF16 (24) Timer X mode register 002716 0016 (25) Timer Y mode register 002816 0016 (26) Timer 123 mode register 002916 0016 (27) TOUT/φ output control register 002A16 0016 (28) PWM control register 002B16 0016 0016 Fig. 58 Internal state of microcomputer immediately after reset Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 53 of 90 (PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕ (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Note: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined 3826 Group (A version) CLOCK GENERATING CIRCUIT The 3826 group has two built-in oscillation circuits: main clock XIN-XOUT oscillation circuit and sub-clock XCIN-XCOUT oscillation circuit. An oscillation circuit can be formed by connecting an oscillator between X IN and X OUT (X CIN and X COUT). Use the circuit constants in accordance with the oscillator manufacturer’s recommended values. A feed-back resistor exists on-chip (An external feed-back resistor may be needed depending on conditions.). However, an external feed-back resistor is needed between XCIN and XCOUT since a resistor does not exist between them. To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock oscillation circuit cannot directly input clocks that are externally generated. Accordingly, be sure to cause an external oscillator to oscillate. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins go to high-impedance state. Frequency Control (1) Middle-speed mode The clock input to the XIN pin is divided by 8 and it is used as the system clock φ. After reset, this mode is selected. (2) High-speed mode The clock input to the XIN pin is divided by 2 and it is used as the system clock φ. Oscillation Control (1) Stop mode If the STP instruction is executed, the system clock φ stops at an “H” level, and main and sub clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Before the STP instruction, set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits are set to timer 1, high-order 8 bits are set to timer 2). Either f(XIN) or f(XCIN) divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are set to “0”. Set the timer 1 and timer 2 interrupt enable bits to “0” before executing the STP instruction. Oscillation restarts at reset or when an external interrupt is received, but the system clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize when a ceramic resonator is used. (2) Wait mode If the WIT instruction is executed, only the system clock φ stops at an “H” state. The states of main clock and sub clock are the same as the state before the executing the WIT instruction, and oscillation does not stop. Since supply of internal clock φ is started immediately after the interrupt is received, the instruction can be executed immediately. (3) Low-speed mode • The clock input to the XCIN pin is divided by 2 and it is used as the system clock φ. XCIN XCOUT •A low-power consumption operation can be realized by stopping the main clock in this mode. To stop the main clock, set the main clock stop bit of the CPU mode register to “1”. When the main clock is restarted, after setting the main clock stop bit to “0”, set enough time for oscillation to stabilize by program. Note: If you switch the mode between middle/high-speed and lowspeed, stabilize both X IN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/highspeed and low-speed, set the frequency in the condition that f(XIN) > 3•f(XCIN). Rf XOUT Rd (Note) Rd CCOUT CCIN Notes : XIN CIN COUT Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 59 Oscillator circuit XCIN Rf XCOUT XIN XOUT Open Rd External oscillation circuit CCIN CCOUT VCC VSS Fig. 60 External clock input circuit Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 54 of 90 3826 Group (A version) XCIN XCOUT “0” XC switch bit (Note 1) “1” XIN Timer 1 count source selection bit XOUT (Note 2) System clock selection bit (Note 1) Low-speed mode 1/2 1/4 Timer 2 count source selection bit “1” 1/2 Timer 1 “0” “0” Timer 2 “1” Middle-/High-speed mode Main clock division ratio selection bit Middle-speed mode System clock φ High-speed mode or Low-speed mode Main clock stop bit Q S S R STP instruction WIT instruction R Q Q S R STP instruction Reset Interrupt disable flag I Interrupt request Notes 1: When using the sub clock for the system clock φ, set the XC switch bit to “1”. 2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 61 Clock generating circuit block diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 55 of 90 3826 Group (A version) Reset CM ” “1 M6 C ” “1 ” “0 Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “0” High-speed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) “0” Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM6 “0” CM6 “0” “1” ” “0 CM5 “1” 5 CM” “1 M6 C ” “1 Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) ” “0 CM6 “1” C “0 M5 CM ” “1 6 ” “1 ” “0 ” “0” “0” CM7 Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 1 (32 kHz oscillating) CM5 “1” “1” CM7 “0” “1” “0” C “0 M4 CM ” “1 6 ” “1 ” “0 ” “1” CM4 ” “0 “0” CM4 “0” “1” 4 “1” High-speed mode (f(φ) = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) CM6 “1” Middle-speed mode (f(φ) = 1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (8 MHz oscillating) CM4 = 0 (32 kHz stopped) Low-speed mode (f(φ) = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (8 MHz stopped) CM4 = 1 (32 kHz oscillating) b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Xc switch bit 0: Oscillation stop 1: XCIN, XCOUT CM5 : Main clock (XIN–XOUT) stop bit 0: Oscillating 1: Stopped CM6 : Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM7 : System clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: XCIN–XCOUT selected (low-speed mode) Notes 1: Switch the mode according to the arrows shown between the mode blocks. (Do not switch between the mode directly without an arrow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended. 3: When the stop mode is ended, a delay time can be set by timer 1 and timer 2. 4: Timer and LCD operate in the wait mode. 5: Wait until oscillation stabilizes after oscillating the main clock before the switching from the low-speed mode to middle-/high-speed mode. 6: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the system clock. Fig. 62 State transitions of system clock Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 56 of 90 3826 Group (A version) NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. After a reset, initialize flags (T flag, D flag, etc.) which affect program execution. Interrupt When the contents of an interrupt request bits are changed by the program, execute a BBC or BBS instruction after at least one instruction. This is for preventing executing a BBC or BBS instruction to the contents before change. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1”. The TxD pin of serial I/O1 retains the level then after transmission is completed. In serial I/O2 selecting an internal clock, the S OUT2 pin goes to high impedance state after transmission is completed. In serial I/O2 selecting an external clock, the SOUT2 pin retains the level then after transmission is completed. A/D Converter Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. The input to the comparator is combined by internal capacitors. Therefore, since conversion accuracy may be worse by losing of an electric charge when the conversion speed is not enough, make sure that f(XIN) is at least 500 kHz during an A/D conversion. The normal operation of A/D conversion cannot be guaranteed when performing the next operation: •When writing to CPU mode register during A/D conversion operation •When writing to AD control register during A/D conversion operation •When executing STP instruction or WIT instruction during A/D conversion operation Instruction Execution Time Ports Use instructions such as LDM and STA, etc., to set the port direction registers. The contents of the port direction registers cannot be read. The following cannot be used: • LDA instruction • The memory operation instruction when the T flag is “1” • The bit-test instruction (BBC or BBS, etc.) • The read-modify-write instruction (calculation instruction such as ROR etc., bit manipulation instruction such as CLB or SEB etc.) • The addressing mode which uses the value of a direction register as an index Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 57 of 90 The instruction execution time is obtained by multiplying the frequency of the system clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the system clock φ depends on the main clock division ratio selection bit and the system clock selection bit. 3826 Group (A version) NOTES ON USE Countermeasures Against Noise Noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20 mm). ● Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit RESET VSS VSS N.G. Reset circuit VSS RESET XIN XOUT VSS N.G. XIN XOUT VSS O.K. Fig. 64 Wiring for clock I/O pins (2) Connection of bypass capacitor across VSS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VCC VCC VSS VSS VSS O.K. Fig. 63 Wiring for the RESET pin ➁ Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. ● Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 58 of 90 N.G. O.K. Fig. 65 Bypass capacitor across the VSS line and the VCC line 3826 Group (A version) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful especially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. ● Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. ● Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M XIN XOUT VSS Large current GND ➁ Installing oscillator away from signal lines where potential levels change frequently N.G. Do not cross CNTR XIN XOUT VSS Fig. 66 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 59 of 90 (4) Analog input The analog input pin is connected to the capacitor of a comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A/D conversion accuracy, and the amount of proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evaluation for each product of every after confirming product specification. 3826 Group (A version) NOTES ON USE Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. ROM ORDERING METHOD 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk. • For the mask ROM confirmation and the mark specifications, refer to the “Renesas Technology Corp.” Homepage (http://www.renesas.com/en/rom) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 60 of 90 3826 Group (A version) ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 12 Absolute maximum ratings Symbol VCC VI Parameter Conditions VI VI VI VI VI VI VO Power source voltage Input voltage P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67 Input voltage P70–P77 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage C1, C2 Input voltage RESET, XIN Output voltage C1, C2 All voltages are based on V SS . When an input voltage is measured, output transistors are cut off. VO Output voltage P00–P07, P10–P15, P30–P37 At output port At segment output VO VO VO VO Pd Topr Tstg Output voltage P16, P17, P20–P27, P40–P47, P50–P57, P60–P67, P71–P77 Output voltage VL3 Output voltage VL2, SEG0–SEG17 Output voltage XOUT Power dissipation Operating temperature Storage temperature Ta = 25°C Ratings –0.3 to 6.5 Unit V –0.3 to VCC +0.3 V –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to 6.5 –0.3 to VCC –0.3 to VL3 V V V V V V V V V –0.3 to VCC +0.3 V –0.3 to 6.5 –0.3 to VL3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V mW °C °C RECOMMENDED OPERATING CONDITIONS Table 13 Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VCC Parameter Power source voltage (Note 1) High-speed mode Middle-speed mode Min. f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz f(XIN) = 4 MHz f(XIN) = 10 MHz f(XIN) = 8 MHz f(XIN) = 6 MHz Low-speed mode At start oscillating (Note 2) VSS VLI VREF AVSS VIA Power source voltage Power source voltage At using voltage multiplier A/D, D/A conversion reference voltage Analog power source voltage Analog input voltage AN0–AN7 4.5 4.0 3.0 2.0 3.0 2.0 1.8 1.8 0.15 ✕ f+1.3 1.3 2.0 Limits Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 1.8 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 2.1 VCC 0 AVSS VCC Unit V V V V V V V V V V V V V V Notes 1: When using the A/D or D/A converter, refer to “A/D Converter Characteristics” or “D/A Converter characteristics”. 2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. f: This is an oscillator’s oscillation frequency. For example, when oscillation frequency is 8 MHz, substitute “8”. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 61 of 90 3826 Group (A version) Table 14 Recommended operating conditions (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VIH VIH VIH VIH VIL VIL VIL VIL Parameter “H” input voltage “H” input voltage “H” input voltage “H” input voltage “L” input voltage “L” input voltage “L” input voltage “L” input voltage P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN P00–P07, P10–P17, P40, P43, P45, P47, P50–P53, P56, P61, P64–P67, P71–P77 P20–P27, P41, P42, P44, P46, P54, P55, P57, P60, P62, P63, P70 RESET XIN Min. Limits Typ. Max. Unit 0.7 VCC VCC V 0.8 VCC VCC V 0.8 VCC 0.8 VCC VCC VCC V V 0 0.3 VCC V 0 0.2 VCC V 0 0 0.2 VCC 0.2 VCC V V Table 15 Recommended operating conditions (3) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) “H” total peak output current “H” total peak output current “L” total peak output current “L” total peak output current “L” total peak output current “H” total average output current “H” total average output current “L” total average output current “L” total average output current “L” total average output current “H” peak output current IOH(peak) “H” peak output current IOL(peak) “L” peak output current IOL(peak) “L” peak output current IOL(peak) IOH(avg) IOH(avg) “L” peak output current “H” average output current “H” average output current IOL(avg) “L” average output current IOL(avg) “L” average output current IOL(avg) “L” average output current P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 (Note 1) P41–P47, P50–P57, P60–P67 (Note 1) P40, P71–P77 (Note 1) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) P00–P07, P10–P15, P30–P37 (Note 2) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 2) P40, P71–P77 (Note 2) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) P00–P07, P10–P15, P30–P37 (Note 3) P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 (Note 3) P40, P71–P77 (Note 3) Limits Min. Typ. Max. –20 –20 20 20 80 –10 –10 10 10 40 –1.0 Unit mA mA mA mA mA mA mA mA mA mA mA –5.0 mA 5.0 mA 10 mA 20 –0.5 –2.5 mA mA mA 2.5 mA 5.0 mA 10 mA Notes1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 62 of 90 3826 Group (A version) Table 16 Recommended operating conditions (4) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter f(CNTR0) f(CNTR1) Input frequency for timers X and Y (duty cycle 50%) f(XIN) Main clock input oscillation frequency (Note 1) f(XCIN) Test conditions Min. Limits Typ. (4.5 V ≤ VCC ≤ 5.5 V) (4.0 V ≤ VCC < 4.5 V) (2.0 V ≤ VCC < 4.0 V) (VCC < 2.0 V) High-speed mode (4.5 V ≤ VCC ≤ 5.5 V) High-speed mode (4.0 V ≤ VCC < 4.5 V) High-speed mode (2.0 V ≤ VCC < 4.0 V) Middle-speed mode (Note 3) (3.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 3) (2.0 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 3) Sub-clock input oscillation frequency (At duty 50 %) (Notes 2, 3) 32.768 Max. Unit 5.0 2✕VCC–4 VCC 5✕VCC–8 10.0 MHz MHz MHz MHz MHz 4✕VCC–8 MHz 2✕VCC MHz 10.0 MHz 8.0 MHz 6.0 50 MHz kHz Notes 1: When using the A/D or D/A converter, refer to “A/D Converter Characteristics” or “D/A Converter characteristics”. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power suppl voltage is low and high frequency oscillator is used, an oscillation start will require sufficient conditions. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 63 of 90 3826 Group (A version) Table 17 Electrical characteristics (1) (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter VOH “H” output voltage P00–P07, P10–P15, P30–P37 VOH “H” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 VOL VOL VOL VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL IIL IIL ILOAD ILEAK “L” output voltage P00–P07, P10–P15, P30–P37 “L” output voltage P16, P17, P20–P27, P41–P47, P50–P57, P60–P67 “L” output voltage P40, P71–P77 Hysteresis INT0–INT2, ADT, CNTR0, CNTR1, P20–P27 Hysteresis SCLK, RXD, SIN2 Hysteresis RESET “H” input current P00–P07, P10–P17, P20–P27, P40–P47, P50–P57, P60–P67, P70–P77 “H” input current RESET “H” input current XIN “L” input current P00–P07,P10–P17, P20–P27,P41–P47, P50–P57, P60–P67 “L” input current P40, P70–P77 “L” input current RESET “L” input current XIN Output load current P30–P37 Output leak current P30–P37 Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 64 of 90 Test conditions IOH = –1 mA IOH = –0.25 mA VCC = 2.2 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.5 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 3.0 mA IOL = 2.5 mA VCC = 2.2 V IOL = 10 mA IOL = 5 mA VCC = 2.2 V Limits Min. VCC–2.0 Typ. V V VCC–2.0 VCC–0.5 V V VCC–0.8 V 2.0 0.5 0.8 V V 2.0 0.5 V V 0.8 V 0.5 0.3 V V V 0.5 V 0.5 0.5 V V µA VI = VCC VI = VSS VI = VSS VCC = 5.0 V, VO = VCC, Pullup ON Output transistors “off” VCC = 2.2 V,VO = VCC, Pullup ON Output transistors “off” VO = VCC, Pullup OFF Output transistors “off” VO = VSS, Pullup OFF Output transistors “off” Unit VCC–0.8 VCC = 2.0 V to 5.0 V VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5 V, VI = VSS Pull-ups “on” VCC = 2.2 V, VI = VSS Pull-ups “on” Max. 5.0 5.0 µA µA –5.0 µA 4.0 –60.0 –120.0 –240.0 µA –5.0 –20.0 –40.0 µA –5.0 –5.0 µA µA µA –60.0 –4.0 –120.0 –240.0 µA –5.0 –20.0 –40.0 µA 5.0 µA –5.0 µA 3826 Group (A version) Table 18 Electrical characteristics (2) (VCC = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Symbol VRAM ICC Parameter RAM retention voltage Power source current Test conditions Min. Limits Typ. 1.8 At clock stop mode • High-speed mode, VCC = 5 V Max. 5.5 Unit V 5.5 11.0 mA 4.5 9.0 mA 1.2 2.4 mA 15 30 µA 7 14 µA 9 18 µA 4.5 9.0 µA 0.1 1.0 µA f(XIN) = 10 MHz f(XCIN) = 32.768 kHz Output transistors “off” A/D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off” A/D converter in operating • High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off” A/D converter stop • Low-speed mode, VCC = 5 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 5 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” • Low-speed mode, VCC = 3 V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off” • Low-speed mode, VCC = 3 V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” IL1 Power source current (VL1) (Note) All oscillation stopped (in STP state) Output transistors “off” VL1 = 1.8 V Ta = 25 °C Ta = 85 °C Note: When the voltage multiplier control bit of the LCD mode register (bit 4 at address 003916) is “1”. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 65 of 90 10 4.0 µA µA 3826 Group (A version) Table 19 A/D converter characteristics (1) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 8-bit A/D mode (when conversion mode selection bit (bit 0 of address 001416) is “1”) Symbol – Parameter Test conditions Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.7 to 5.5 V tCONV Conversion time f(XIN) = 8 MHz RLADDER IVREF IIA Ladder resistor Reference power source input current Analog port input current VREF = 5 V – Min. 12 50 Limits Typ. 35 150 Max. 8 ±2 12.5 (Note) 100 200 5.0 Unit Bits LSB µS kΩ µA µA Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 14 µS. Table 20 A/D converter characteristics (2) (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 500 kHz to 10 MHz, in middle/high-speed mode unless otherwise noted) 10-bit A/D mode (when conversion mode selection bit (bit 0 of address 001416) is “0”) Symbol – Parameter Test conditions Resolution Absolute accuracy (excluding quantization error) VCC = VREF = 2.7 to 5.5 V tCONV Conversion time f(XIN) = 8 MHz RLADDER IVREF IIA Ladder resistor Reference power source input current Analog port input current VREF = 5 V – Min. 12 50 Limits Typ. 35 150 Max. 10 ±4 15.5 (Note) 100 200 5.0 Unit Bits LSB µS kΩ µA µA Note: When the internal trigger is used in the middle-speed mode, the max. value of tCONV is 17 µS. Table 21 D/A converter characteristics (VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed mode unless otherwise noted) Symbol – – tsu RO IVREF Parameter Test conditions Min. Limits Typ. Resolution Absolute accuracy Setting time Output resistor Reference power source input current VCC = VREF = 5 V VCC = VREF = 2.7 V 1 (Note) 3 2.5 Max. 8 1.0 2.0 4 3.2 Unit Bits % % µs kΩ mA Note: Using one D/A converter, with the value in the DA conversion register of the other D/A converter being “0016”, and excluding currents flowing through the A/D resistance ladder. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 66 of 90 3826 Group (A version) Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter tw(RESET) tc(XIN) Reset input “L” pulse width Main clock input cycle time (XIN input) twH(XIN) Main clock input “H” pulse width twL(XIN) Main clock input “L” pulse width tc(CNTR) CNTR0, CNTR1 input cycle time twH(CNTR) CNTR0, CNTR1 input “H” pulse width twL(CNTR) CNTR0, CNTR1 input “L” pulse width twH(INT) twL(INT) tc(SCLK1) twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 67 of 90 Min. (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC (4.5 V ≤ VCC (4.0 V ≤ VCC ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) ≤ 5.5 V) < 4.5 V) Limits Typ. 2 100 1000/(4✕Vcc-8) 40 45 40 45 200 1000/(2✕Vcc-4) 85 105 85 105 80 80 800 370 370 220 100 1000 400 400 200 200 Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3826 Group (A version) Table 23 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol Parameter tw(RESET) tc(XIN) Reset input “L” pulse width Main clock input cycle time (XIN input) twH(XIN) Main clock input “H” pulse width twL(XIN) Main clock input “L” pulse width tc(CNTR) CNTR0, CNTR1 input cycle time twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1) CNTR0, CNTR1 input “H” pulse width CNTR0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time twH(SCLK1) twL(SCLK1) tsu(RXD–SCLK1) th(SCLK1–RXD) tc(SCLK2) twH(SCLK2) twL(SCLK2) tsu(RXD–SCLK2) th(SCLK2–RXD) Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 68 of 90 Min. Limits Typ. 2 (2.0 V ≤ VCC ≤ 4.0 V) 125 (VCC < 2.0 V) 1000/(10✕Vcc-12) (2.0 V ≤ VCC ≤ 4.0 V) 50 (VCC < 2.0 V) 70 (2.0 V ≤ VCC ≤ 4.0 V) 50 (VCC < 2.0 V) 70 (2.0 V ≤ VCC ≤ 4.0 V) 1000/VCC (VCC < 2.0 V) 1000/(5✕Vcc-8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 2000 950 950 400 200 Max. Unit µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3826 Group (A version) Table 24 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time Limits Min. tC (SCLK1)/2–30 tC (SCLK1)/2–30 Max. Typ. 140 –30 30 30 tC (SCLK2)/2–160 tC (SCLK2)/2–160 0.2 ✕ tC (SCLK2) 0 40 Unit ns ns ns ns ns ns ns ns ns ns ns Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. Table 25 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted) Symbol twH(SCLK1) twL(SCLK1) td(SCLK1–TXD) tv(SCLK1–TXD) tr(SCLK1) tf(SCLK1) twH(SCLK2) twL(SCLK2) td(SCLK2–SOUT2) tv(SCLK2–SOUT2) tf(SCLK2) Parameter Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note) Serial I/O1 output valid time (Note) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time Min. Limits Typ. Max. tC (SCLK1)/2–100 tC (SCLK1)/2–100 350 –30 100 100 tC (SCLK2)/2–240 tC (SCLK2)/2–240 0.2 ✕ tC (SCLK2) 0 100 Note: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 1 kΩ Measurement output pin Measurement output pin 100 pF CMOS output 100 pF N-channel open-drain output (Note) Note: When P71–P77, P40 and bit 4 of the UART control register (address 001B16 ) is “1” (N-channel opendrain output mode). Fig. 65 Circuit for measuring output switching characteristics Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 69 of 90 Unit ns ns ns ns ns ns ns ns ns ns ns 3826 Group (A version) tC(CNTR) tWL(CNTR) tWH(CNTR) 0.8VCC C N TR 0 , C N TR 1 0.2VCC tWL(INT) tWH(INT) 0.8VCC INT0–INT2 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XI N 0.2VCC tC(SCLK1), tC(SCLK2) tr tWL(SCLK1), tWL(SCLK2) tf SCLK1 SCLK2 0.8VCC 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) RX D SIN2 th(SCLK1-RXD), th(SCLK2-SIN2) 0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2-SOUT2) TX D SOUT2 Fig. 66 Timing diagram Rev.2.00 May. 24, 2006 REJ03B0028-0200 tWH(SCLK1), tWH(SCLK2) page 70 of 90 tv(SCLK1-TXD), tv(SCLK2-SOUT2) 3826 Group (A version) PACKAGE OUTLINE JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 50 76 bp c1 Reference Symbol c E *2 HE b1 D E A2 HD HE A A1 bp b1 c c1 100 26 1 ZE Terminal cross section 25 Index mark ZD y *3 e A1 c A A2 F bp e x y ZD ZE L L1 L x L1 Detail F JEITA Package Code P-HLQFP100-14x20-0.65 RENESAS Code PLQP0100JB-A Previous Code 100P6K-A Dimension in Millimeters Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0° 8° 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0 MASS[Typ.] 1.2g HD *1 D 80 51 80 51 81 50 50 81 HE E1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 E D2 31 100 1 31 30 Index mark c 100 30 1 e y *3 bp A1 A A2 F L x Detail F Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 71 of 90 Reference Symbol Dimension in Millimeters Min D 19.9 E 13.9 A2 HD 21.8 HE 15.8 A A1 0.05 bp 0.27 c 0.105 0° e x y L 0.35 D2 E1 Nom 20.0 14.0 1.4 22.0 16.0 Max 20.1 14.1 22.2 16.2 1.7 0.125 0.2 0.32 0.37 0.125 0.175 8° 0.65 0.13 0.10 0.5 0.65 15.0 9.0 3826 Group (A version) 3.3 Notes on use 3.3.1 Notes on programming (1) Processor status register ➀ Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. ● Reason After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Reset ↓ Initializing of flags ↓ Main program Fig. 3.3.1 Initialization of processor status register ➁ How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. (S) (S)+1 Stored PS Fig. 3.3.3 Stack memory contents after PHP instruction execution Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 72 of 90 3826 Group (A version) (2) Decimal calculations ■ Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. ■ Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Set D flag to “1” ↓ ADC or SBC instruction ↓ NOP instruction ↓ SEC, CLC, or CLD instruction Fig. 3.3.4 Status flag at decimal calculations (3) Multiplication and Division Instructions • The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. • The execution of these instructions does not change the contents of the processor status register. (4) JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. (5) BRK instruction When the BRK instruction is executed with the following conditions satisfied, the interrupt execution is started from the address of interrupt vector which has the highest priority. • Interrupt request bit and interrupt enable bit are set to “1”. • Interrupt disable flag (I) is set to “1” to disable interrupt. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 73 of 90 3826 Group (A version) (6) Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (memory and SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. •Bit management instructions: CLB, SEB •Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF •Add and subtract instructions: DEC, INC •Logical operation instructions (1’s complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = “1” operate in the way as the read-modify-write instruction. Do not execute the read invalid memory and SFR. [Reason] When the read-modify-write instruction is executed to read invalid memory and SFR, the instruction may cause the following consequence: the instruction reads unspecified data from the memory due to the read invalid condition. Then the instruction modifies this unspecified data and writes the data to the memory. The result will be random data written to the memory or some unexpected event. (7) Instruction execution time Each instruction execution time is obtained from the cycle time of system clock φ multiplied by the number of instruction cycles listed in the machine instruction table. Note that the cycle time of system clock φ is defined by the system clock division ratio selection bit and the system clock selection bit. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 74 of 90 3826 Group (A version) 3.3.2 Notes on I/O port (1) Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction (Note), the value of the unspecified bit may be changed. ● Reason I/O ports can be set to input or output mode in a bit unit. When reading or writing are performed to the port Pi (i = 0–7) register, the microcomputer operates as follows. •Port in input mode -Read-access: reads pin’s level (The contents of port latch and pin’s level are unrelated.) -Write-access: writes data to port latch (The contents of port latch and pin’s level are unrelated.) •Port in output mode -Read-access: reads port latch (The contents of port latch and pin’s level are unrelated.) -Write-access: writes data to port latch (The contents of port latch are output from the pin.) The bit managing instructions are read-modify-write form instructions (refer to “3.3.1 Notes on programming (6)”) for reading and writing data by a byte unit. Therefore, when the bit managing instructions are executed to the port set to input mode, the instruction read the pin’s states, modify the specification bit, and then write data to the port latch. At this time, if the contents of the original port latch are different from the pins’s level, the contents of the port latch of bit which is not specified by instruction will change. In addition to this, if the bit managing instructions are executed to the port Pi register in order to setting output data when port Pi is configured as a mixed input and output port, the contents of the port latch of bit in the input mode which is not specified by instruction may change. Note: Bit managing instructions: SEB instruction, CLB instruction (2) The port direction registers are write-only registers. Therefore, the following instructions cannot be used to this register: •LDA instruction •Memory operation instruction when T flag is “1” •Instructions operating in addressing mode that modifies direction register •Bit test instructions such as BBC and BBS •Bit modification instructions such as CLB and SEB •Arithmetic instructions using read-modify-write form instructions such as ROR The LDM, STA instructions etc. are used for setting of the direction register. (3) Pull-up Operation When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. ● Reason Pull-up control is effective only when each direction register is set to the input mode. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 75 of 90 3826 Group (A version) 3.3.3 Termination of unused pins (1) Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. ➀Output ports Open them. ➁Input ports Connect each pin to V CC or V SS through each resistor of 1 kΩ to 10 kΩ. A for pins whose potential affects to operation modes such as the INTi pin or others, select the V CC pin or the VSS pin according to their operation mode. ➂ I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. The port which can select a built-in pull-up resistor can also use the builtin pull-up resistor. When using the I/O ports as the output mode, open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) Termination remarks ■ Input ports Do not open them. ● Reason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➁ shown on the above. ■ I/0 ports setting as input mode [1] Do not open in the input mode. ● Reason • The power source current may increase depending on the first-stage circuit. • An effect due to noise may be easily produced as compared with proper termination ➂ shown on the above. [2] I/O ports : Do not connect to VCC or V SS directly. ● Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur. [3] I/O ports : Do not connect multiple ports in a lump to V CC or V SS through a resistor. ● Reason If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 76 of 90 3826 Group (A version) 3.3.4 Notes on interrupts (1) Unused interrupts Set the interrupt enable bit for unused interrupts to “0” (disabled). (2) Change of relevant register settings When setting the followings, the interrupt request bit may be set to “1”. •When switching external interrupt active edge Related register: •Interrupt edge selection register (address 3A 16) •Timer X mode register (address 27 16) •Timer Y mode register (address 28 16) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Related register: •Interrupt source selection bit of AD control register (bit 6 of address 34 16) When not requiring for the interrupt occurrence synchronous with these setting, take the following sequence. Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge select bit, active edge switch bit, or the interrupt source select bit. ↓ NOP (One or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 3.3.5 Sequence of changing relevant register ■ Reason When setting the followings, the interrupt request bit of the corresponding interrupt may be set to “1”. •When switching external interrupt active edge Concerned register: INT0 interrupt edge selection bit (bit 0 of Interrupt edge selection register (address 3A16)) INT1 interrupt edge selection bit (bit 1 of Interrupt edge selection register (address 3A16)) INT2 interrupt edge selection bit (bit 2 of Interrupt edge selection register (address 3A16)) CNTR0 active edge switch bit (bit 6 of timer X mode register (address 2716)) CNTR1 active edge switch bit (bit 6 of timer Y mode register (address 2816)) •When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated. Concerned register: Interrupt source selection bit (bit 6 of AD control register (address 3416)) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 77 of 90 3826 Group (A version) (3) Check of interrupt request bit When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to “0”, take the following sequence. Set the interrupt request bit to “0” (no interrupt issued) ↓ NOP (one or more instructions) ↓ Execute the BBC or BBS instruction Fig. 3.3.6 Sequence of check of interrupt request bit ■ Reason If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 78 of 90 3826 Group (A version) 3.3.5 Notes on timer This clause describes notes for the various operation modes of Timer X, Timer Y, Timer 1, Timer 2, and Timer 3. (1) Timer X ■For all modes ◆When reading and writing to the timer X high-order and low-order registers, be sure to read/write both the timer X high- and low-order registers. When reading the timer X high-order and low-order registers, read the high-order register first. When writing to the timer X high-order and low-order registers, write the low-order register first. The timer X cannot perform the correct operation if the next operation is performed. •Write operation to the high- or low-order register before reading the timer X low-order register •Read operation from the high- or low-order register before writing to the timer X high-order register ◆When the operation “writing data only to the latch” is selected by the timer X write control bit (bit 0 of timer X mode register (address 2716)) is selected, a value is simultaneously set to the timer X and the timer X latch if the writing in the high-order register and the underflow of timer X are performed at the same timing. Unexpected value may be set in the high-order timer on this occasion. ■Pulse output mode ◆When reading port P5 4 (bit 4 of port P5 register (address 0A 16)) in the pulse output mode, the pin state is read instead of the contents of the port latch. ■Real time port function ◆After reset is released, the port P5 direction register is set as the input mode and ports P5 0–P5 7 functions as regular ports. To use as the RTP function pin, set the corresponding bit of the port P5 direction register to the output mode. ■CNTR 0 active edge selection ◆The CNTR 0 active edge selection bit (bit 6 of timer X mode register) also effects the active edge of the generation of the CNTR 0 interrupt request. (2) Timer Y ■For all modes ◆When reading and writing to the timer Y high-order and low-order registers, be sure to read/write both the timer Y high- and low-order registers. When reading the timer Y high-order and low-order registers, read the high-order register first. When writing to the timer Y high-order and low-order registers, write the low-order register first. The timer Y cannot perform the correct operation if the next operation is performed. •Write operation to the high- or low-order register before reading the timer Y low-order register •Read operation from the high- or low-order register before writing to the timer Y high-order register ■CNTR 1 active edge selection ◆The CNTR 1 active edge selection bit (bit 6 of timer Y mode register (address 2816)) also effects the active edge of the generation of the CNTR1 interrupt request. However, both edges are valid for the request generation regardless of the bit state in the continuous HL pulse-width measurement mode. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 79 of 90 3826 Group (A version) (3) Timers 1–3 Set the value of timer in the order of the timer 1 register, the timer 2 register, and the timer 3 register after the count source selection of timer 1 to 3. <Reason> •When the count source of timers 1 to 3 is changed, the timer counting value may become arbitrary value because a thin pulse is generated in count input of timer. •If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may become undefined value because a thin pulse is generated in timer 1 output. (4) Timer 2 If the value is written in latch only, a value is simultaneously set to the timer 2 and the timer 2 latch when the writing in the high-order register and the underflow of timer 2 are performed at the same timing. (5) All timers ■The count source for timers is effected by system clock φ which is selected by the system clock selection bit (bit 7 of CPU mode register (address 3B 16)). ■Set the timer which is not used as follows: •Stop the count (when using a timer with stop control) •Set “0” to the corresponding interrupt enable bit Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 80 of 90 3826 Group (A version) 3.3.6 Notes on serial I/O1 (1) Writing to baud rate generator (BRG) Write data to BRG while the transmission and reception operations are stopped. (2) Setting procedure when using serial I/O1 transmit interrupt When the serial I/O1 transmit interrupt is used, take the following sequence. ➀Set the serial I/O1 transmit interrupt enable bit (bit 3 of interrupt control register 1 (address 3E16)) to “0” (disabled). ➁Set the transmit enable bit (bit 4 of serial I/O1 control register (address 1A 16)) to “1”. ➂Set the serial I/O1 transmit interrupt request bit (bit 3 of interrupt request register 1 (address 3C 16)) to “0” (no interrupt request issued) after 1 or more instruction has executed. ➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled). <Reason> When the transmission enable bit is set to “1”, the transmit buffer empty flag (bit 0 of serial I/O1 status register (address 19 16)) and the transmit shift register completion flag (bit 2 of serial I/O1 status register) are set to “1”. Therefore, the serial I/O1 transmit interrupt request bit is set to “1” regardless of the state of the transmit interrupt source selection bit (bit 3 of serial I/O1 control register). (3) Data transmission control with referring to transmit shift register completion flag After the transmit data is written to the transmit buffer register (address 18 16), the transmit shift register completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (4) Setting serial I/O1 control register again Set the serial I/O1 control register again after the transmission and the reception circuits are reset by setting both the transmit enable bit and the receive enable bit to “0”. Set both the transmit enable bit (TE) and the receive enable bit (RE) to “0” ↓ Set the bits 0 to 3 and bit 6 of the serial I/O1 control register ↓ Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time Fig. 3.3.7 Sequence of setting serial I/O1 control register again Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 81 of 90 3826 Group (A version) (5) Pin state after transmit completion The TxD pin holds the state of the last bit of the transmission after transmission completion. When the internal clock is selected for the transmit clock in the clock synchronous serial I/O mode, the SCLK1 pin holds “H”. (6) Serial I/O1 enable bit during transmit operation When the serial I/O1 enable bit (bit 7 of serial I/O1 control register) is set to “0” (serial I/O1 disabled) when data transmission is in progress, the transmission progress internally. However, the external data transfer is terminated because the pins become regular I/O ports. In addition to this, when data is written to the transmission buffer register, data transmission is started internally. When the serial I/O1 enable bit is set to “1”, the transmission is output to the TxD pin in the middle of the transfer. (7) Transmission control when external clock is selected When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to “1” at “H” of the SCLK1 input level. Also, write the transmit data to the transmit buffer register at “H” of the SCLK1 input level. (8) Receive operation in clock synchronous serial I/O mode When receiving data in the clock synchronous serial I/O mode, set not only the receive enable bit but also the transmit enable bit to “1”. Then write dummy data to the transmission buffer register. When the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and the receive operation is started. When the external clock is selected as the transfer clock, the serial I/O becomes ready for data receive at this point and, when the external clock is input to the clock input pin, the receive operation is started. The P45/TxD pin outputs the dummy data written in the transmission buffer register. (9) Transmit and receive operation in clock synchronous serial I/O mode When stopping transmitting and receiving operations in the clock synchronous serial I/O mode, set the receive enable bit and the transmit enable bit to “0” simultaneously. If only one of them is stopped the receive or transmit operation may loose synchronization, causing a bit slippage. 3.3.7 Notes on serial I/O2 (1) Switching synchronous clock When switching the synchronous clock by the serial I/O2 synchronous clock selection bit (bit 6 of serial I/O2 control register (address 1D16)), initialize the serial I/O2 counter (write data to serial I/ O2 register (address 1F16)). (2) Notes when selecting external clock When an external clock is selected as the synchronous clock, the S OUT2 pin holds the output level of D7 after transmission is completed. However, if the clock is input to the serial I/O continuously, the serial I/O2 register continue the shift operation and output data from the SOUT2 pin continuously. A write operation to the serial I/O2 register must be performed when the S CLK21 pin is “H”. When the internal clock is selected as the synchronous clock, the S OUT2 pin holds the highimpedance state after transmission. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 82 of 90 3826 Group (A version) 3.3.8 Notes on PWM output circuit ●“L” level output before starting PWM output When at least one of two is set to “1” when both the PWM0 function enable bit and the PWM1 function enable bit are “0”, “L” level is output from the corresponding PWM pin during the period shown below. Then, PWM output is started from “H” level. •Count source selection bit = “0”, where n is the value set in the prescaler n + 1 2 • f(XIN) sec. •Count source selection bit = “1”, where n is the value set in the prescaler n + 1 f(X IN) sec. ●Change of PWM output When the PWM prescaler and the PWM register are changed during PWM output, the PWM waveforms corresponding to updated data will be output from the next repetitive cycle. Figure 3.3.8 shows the change of PWM output. PWM output Changes PWM prescaler and PWM register Fig. 3.3.8 Change of PWM output Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 83 of 90 From the next repetitive cycle, output modified waveform 3826 Group (A version) 3.3.9 Notes on A/D converter (1) Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the user side. ● Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion precision to be worse. (2) Analog power source input pin AVss The AV SS pin is an analog power source input pin. Regardless of using the A/D conversion function or not, connect it as following : • AV SS : Connect to the V SS line ● Reason If the AV SS pin is opened, the microcomputer may have a failure because of noise or others. (3) Reference voltage input pin V REF Connect an approximately 1000 pF capacitor across the AVss pin and the V REF pin. Besides, connect the capacitor across the V REF pin and the AVss pin at equal length as close as possible. (4) Clock frequency during A/D conversion Use the A/D converter in the following conditions: • Select X IN-XOUT as system clock φ by the system clock selection bit (bit 7 of CPU mode register (address 3B16)). When selecting XCIN-XCOUT as system clock φ, the A/D conversion function cannot be used. • f(X IN) is 500 kHz or more. • Do not execute the STP or WIT instruction during A/D conversion. ● Reason The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. This may cause the A/D conversion precision to be worse. (5) When the falling edge is input to the ADT pin during A/D conversion at the time of A/D external trigger effective, the conversion processing is interrupted and the A/D conversion starts again. In addition, even if “0” is set to the AD conversion completion bit by the program during A/D conversion, re-conversion is not performed but the original conversion is continued. (6) The A/D converter will not operate normally if one of the following operation is applied during the A/D conversion: •Writing to CPU mode register •Writing to AD control register •Executing the STP instruction and WIT instruction Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 84 of 90 3826 Group (A version) 3.3.10 Notes on D/A converter (1) Pin states at reset The P56/DA1 pin and the P5 7/ADT/DA 2 pin go to high impedance state at reset. (2) Connecting low-impedance device The DAi output pin have no buffer, so connect an external buffer when driving a low-impedance load. (3) Reference voltage input pin V REF •When the P5 6/DA 1 pin and the P5 7/ADT/DA 2 pin are used as DAi output pins, the Vcc level is recommended for the applied voltage to the V REF pin. When the voltage below Vcc level is applied, the D/A conversion accuracy may be worse. •Connect an approximately 1000 pF capacitor across the AVss pin and the V REF pin. Besides, connect the capacitor across the VREF pin and the AVss pin at equal length as close as possible. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 85 of 90 3826 Group (A version) 3.3.11 Notes on LCD drive control circuit (1) Count source for LCDCK The LCDCK count source selection bit (bit 7 of LCD mode register (address 39 16)) is set to “0” after reset, selecting f(X CIN)/32. The sub clock has stopped after reset. Therefore, turn on LCD after starting the oscillation and stabilizing the oscillation. Select the LCDCK count source after the corresponding clock source becomes stable. (2) STP instruction When executing the STP instruction, execute the STP instruction after setting the LCD enable bit to “0”. If the STP instruction is executed during LCD lighting, direct-current voltage will be applied to the LCD panel. (3) When not using LCD When not using an LCD, leave the LCD segment and common pins open. Connect the V L1 pin to Vss, and the V L2 and V L3 pins to Vcc. (4) Using voltage multiplier circuit When using the voltage multiplier, apply the limit voltage or less to the V L1 pin, then set the voltage multiplier control bit to “1” (enabled). If above the limit voltage is applied to the V L1 pin, current may flow in the voltage multiplier circuit at the time of the voltage multiplier circuit operation start. For the limit value, refer to “3.1 Electrical characteristics”. When not using the voltage multiplier, set the LCD output enable bit to “1”, then apply proper voltage to the LCD power input pins (V L1–VL3). When the LCD output enable bit is set to “0” (disabled), the Vcc voltage is applied to the V L3 pin inside of this microcomputer. (5) LCD drive power supply Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1–0.33 µF to VL1–VL3 pins. The example of a strengthening measure of the LCD drive power supply is shown in Figure 3.3.9. VL3 •Connect by the shortest possible wiring. •Connect the bypass capacitor to the VL1–VL3 pins as short as possible. (Referential value: 0.1–0.33 µF) VL2 VL1 3826 group Fig. 3.3.9 Strengthening measure example of LCD drive power supply Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 86 of 90 3826 Group (A version) (6) Data setting to LCD display RAM When writing a data into the LCD display RAM during LCD being turned ON (LCD enable bit = “1”), write the confirmed data. Do not write temporarily on the LCD display RAM because this might cause the LCD display flickering. Figure 3.3.10 shows the write procedure for LCD display RAM when LCD is on. (1)Right process example Contents of addres 004016 are “FF16” LCD ON LCD display ON or OFF ? OFF ON LCD ON or OFF Sets LCD display RAM data Sets LCD display RAM data LRAM0 (Address : 4016) ← “FF16” LRAM0 (Address : 4016) ← “0016” •Sets determinate data to LCD diplay RAM (2) Error process example LCD ON Contents of addres 004016 are “FF16” Sets LCD display RAM data LRAM0 (Address : 4016) ← “0016” LCD OFF LCD display ON or OFF ? •Sets turn off data to LCD display RAM OFF ON LCD ON or OFF Sets LCD display RAM data •Sets determinate data to LCD display RAM LRAM0 (Address : 4016) ← “FF16” Fig. 3.3.10 Write procedure for LCD display RAM when LCD is on Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 87 of 90 3826 Group (A version) 3.3.12 Notes on watchdog timer (1) The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. (2) The watchdog timer stops during the stop mode. However, the watchdog timer is running during the clock stabilization period and the watchdog timer control register must be written just before executing the STP instruction. (3) The count source of the watchdog timer is affected by the system clock φ selected by the system clock selection bit (bit 7 of CPU mode register (address 3B 16)). 3.3.13 Notes on reset circuit (1) Reset input voltage control Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min). (2) Countermeasures for reset signal slow rising In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. Use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following: •Make the length of the wiring which is connected to a capacitor as short as possible. •Be sure to verify the operation of application products on the user side. ●Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. (3) Port state immediately after reset Table 3.3.1 shows the each pin state during RESET pin is “L”. Table 3.3.1 Each pin state during RESET pin is “L” Pin state Pin name Input mode (with pull-up) P0, P1 (SEG26–SEG39) P2, P41–P4 7, P5, P6 Input mode (high-impedance) P3 (SEG 18–SEG 25) Pulled up to Vcc level P70 High-impedance P4 0, P7 1–P77 Input mode (high-impedance) SEG0–SEG 17 COM0–COM 3 Vcc level output Vcc level output Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 88 of 90 3826 Group (A version) 3.3.14 Notes on clock generating circuit ●Mode transition Both the main clock (XIN-X OUT) and sub-clock (XCIN-X COUT) need time for the oscillations to stabilize. The mode transition between middle-/high-speed and low-speed mode must be performed after the corresponding clock becomes stable. The sub-clock, needs extra time to stabilize particularly when executing operations after power-on and stop mode. The main and sub clocks require the following condition for mode transition. f(X IN) > 3✕f(X CIN) Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 89 of 90 3826 Group (A version) 3.3.15 Notes on standby function (1) Once the STP instruction is disabled by the STP instruction disable bit (bit 6 of watchdog timer control register (address 37 16)), the microcomputer cannot be return to the STP instruction enable state. (2) When using the standby function, note the following. The power dissipation may increase depending on functions and pin states. Take the following countermeasures for reduce the power dissipation. ■Countermeasures for reduce power dissipation •Input ports: Fix to “H” or “L” externally •Output ports: Fix to level that avoid leak-current. (Example: Fix the pin to “H“ when the circuit which current flows and LED turns on at “L” output.) •A/D input pins: Fix to “H” or “L” externally •PWMi function enable bits (bits 1 and 2 of PWM control register (address 2B 16)): “0” •LCD enable bit: “0” •Complete A/D conversion (Confirm the AD conversion completion bit (bit 3 of AD control register (address 34 16)) is “1”) •VREF input switch bit (bit 4 of AD control register): “0” •D/Ai conversion register (addresses 32 16, 33 16): “0016” (3) When using stop mode ■Operation after restoration by occurrence of interrupt request •All the timer 123 mode register bits are automatically set to “0” except for bit 4. •When an interrupt request occurs in the stop mode, the stop mode is released and the clock stopped by STP starts the oscillation. The oscillation stabilizing time of main clock is secured to restoration from the stop mode when both the main and sub clocks are oscillating and the main clock is set for the system clock when executing the STP instruction. Note that the oscillation of sub clock may not be stable after main clock oscillation being stable. ■When LCD display Execute the STP instruction after turning LCD to OFF by setting the LCD enable bit (bit 3 of LCD mode register (address 39 16)) to “0”. If the STP instruction is executed while the LCD is ON, direct voltage will be applied to the LCD panel. ■Watchdog timer The watchdog timer stops during the stop mode but operates during the oscillation stabilizing time. Therefore, the watchdog timer control register must be written just before executing the STP instruction to prevent its underflow. (4) When using wait mode ■Restoration by reset input When the sub clock is selected as the system clock and the main clock is stopped at the time WIT instruction is executed, if the RESET pin input level is set to “L”, the sub clock oscillation stops and the main clock oscillation starts. Oscillation is unstable at first and requires an oscillation stabilizing time. Retain the RESET pin input level at “L” until the oscillation is stabilized. After the oscillation has stabilized, retain the RESET pin at “L” for 2 µs or more in order to set the internal reset state. ■Watchdog timer The watchdog timer operates during the wait mode. The watchdog timer control register must be written to prevent its underflow. Rev.2.00 May. 24, 2006 REJ03B0028-0200 page 90 of 90 REVISION HISTORY Rev. 3826 Group (A version) Data Sheet Date Description Summary Page 1.00 Feb. 18, 2003 1.02 Jul. 31, 2003 – 1 4 7 18 19 20 21 39 44 58 61 63 64 65 66 2.00 May.24, 2006 67 1 6 7 13 38 39 53 54 55 60 First edition issued Power dissipation revised. Table 1 Pin description (1) VCC VSS; Function description revised. Fig.5 Memory expansion plan revised. Fig.14 Port block diagram (1); (4) Ports P16, P17,P2, P41, P42 and (5) Port P44 revised. Fig.15 Port block diagram (2); (7) Port P46 and (11) Port P54 revised. Fig.16 Port block diagram (3); (14) Port P55, (15) Ports P56, P57 and (17) Port P60 revised. Fig.17 Port block diagram (4); (19) Port P62 revised. Fig.40 A-D converter block diagram Voltage Multiplier (3 Times) Description of order for operating the voltage multiplier revised. ROM ORDERING METHOD revised. Table 16 Recommended operating conditions (4); f(CNTR0) f(CNTR1) revised. Table 18 Electrical characteristics (2); ICC revised. Table 19 A-D converter characteristics (1); Note revised. Table 20 A-D converter characteristics (2); Note revised. Table 22 Timing requirements (1); tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 23 Timing requirements (2); tc(SCLK), tWH(SCLK), tWL(SCLK), tsu(RxD-SCLK), th(SCLK-RxD); revised. Table 25 Switching characteristics (2) ; tr(SCLK1) tf(SCLK1) revised. Package revised. Word standardized: “A/D converter”, “D/A converter”, “Serial interface” FEATURES: • A/D converter revised. APPLICATIONS: “household appliances” added. Fig. 4: Description of RAM added. Fig. 5: Development status: “under development” → “mass production” Table 3: Date revised. SFR: AD conversion low-order register (ADL) added to address 001416 and AD conversion high-order register (ADH) added to address 003516. A/D CONVERTER: Description revised and ADL added to Fig. 38. Fig. 39 added and Fig. 40 revised. Fig. 58: AD conversion low-order register added. Description revised. Fig. 59: Note added. Fig. 61: Note 2 added. Note on Power supply voltage added. (1/2) REVISION HISTORY Rev. 3826 Group (A version) Data Sheet Date Description Summary Page 2.00 May.24, 2006 ROM ORDERING METHOD: URL revised. Table 19: “f(XIN) = 8 MHz” added to Test condition of tCONV revised. Table 20 A/D converter characteristics (2) [10-bit A/D mode] added. Table 22: “(Note)” of tc(SCLK2), twH(SCLK2), twL(SCLK2) eliminated. 67 Table 23: “(Note)” of tc(SCLK2), twH(SCLK2), twL(SCLK2) eliminated. 68 Table 25: Note 2 eliminated. 69 72 to 90 APPENDIX added. 60 66 (2/2) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. 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