AVAGO HCPL-0708-560E High speed cmos optocoupler Datasheet

HCPL-0708
High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Available in SO-8 package, the HCPL-0708 optocoupler
utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of the HCPL-0708 are a high
speed LED and a CMOS detector IC. The detector incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an
output driver.
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Functional Diagram
NC
1
8
VDD
ANODE
2
7
NC
CATHODE
3
6
VO
NC
4
5
GND
TRUTH TABLE
LED
VO, OUTPUT
OFF
ON
H
L
+5 V CMOS compatibility
15 ns typical pulse width distortion
30 ns max. pulse width distortion
40 ns max. propagation delay skew
High speed: 15 MBd
60 ns max. propagation delay
10 kV/µs minimum common mode rejection
–40 to 100°C temperature range
Safety and regulatory approvals pending
– UL recognized
3750 V rms for 1 min. per UL 1577 for HCPL-0708
– CSA component acceptance Notice #5
– IEC/EN/DIN EN 60747-5-2 approved for HCPL-0708 Option 060
Applications
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Scan drive in PDP
Digital field bus isolation: DeviceNet, SDS, Profibus
Multiplexed data transmission
Computer peripheral interface
Microprocessor system interface
*A 0.1 µF bypass capacitor must be
connected between pins 5 and 8.
HCPL-0710 Functional Diagram
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-0708 is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Part
Number
Option
RoHS
Compliant
non RoHS
Compliant Package
Surface
Mount
-000E
no option
X
100 per tube
SO-8
Gull
Wing
Tape
& Reel
UL 5000 Vrms/
1 Minute rating
IEC/EN/DIN
EN 60747-5-2
Quantity
HCPL-0708 -500E
#500
X
X
1500 per reel
-560E
-
X
X
1500 per reel
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example1:
HCPL-0708-500E to order product of Small Outline SO-8 package in Tape and Reel packaging and RoHS compliant.
Example 2:
HCPL-0708 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
Package Outline Drawing
LAND PATTERN RECOMMENDATION
8
7
6
5
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE 1
2
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
1.524
(0.060)
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Solder Reflow Thermal Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
TIME (SECONDS)
Note: Non-halide flux should be used.
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-0708 has been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01 (Option 060 only)
PEAK
TEMP.
230°C
250
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air
L(I01)
4.9
mm
Gap (Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
L(I02)
4.8
mm
Tracking (Creepage)
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
0.08
mm
Gap (Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
≥175
IIIa
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimen­sions are needed as a starting point for the equipment designer when determining the circuit insulation
requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require­
ments must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
Volts
Insulation thickness between emitter and
detector; also known as distance through
insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on factors such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
Description
Symbol
HCPL-0708 Option 060
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
I-IV
for rated mains voltage ≤300 V rms
I-III
for rated mains voltage ≤450 V rms
Climatic Classification
55/85/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input to Output Test Voltage, Method b†
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
VPR
1050
V peak
Input to Output Test Voltage, Method a†
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
VPR
840
V peak
VIOTM
4000
V peak
TS
IS,INPUT
PS,OUTPUT
150
150
600
°C
mA
mW
RIO
≥109
Ω
Highest Allowable Overvoltage†
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, V10 = 500 V
†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description.
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
125
°C
Ambient Operating Temperature[1]
TA
–40
+100
°C
Supply Voltages
VDD
0
6
Volts
Output Voltage
VO
–0.5
VDD2 +0.5
Volts
Average Output Current
IO
2
mA
Average Forward Input Current
IF
20
mA
Lead Solder Temperature
Figure
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
+100
°C
Supply Voltages
VDD
4.5
5.5
V
Input Current (ON)
IF
10
16
mA
Figure
1, 2
Electrical Specifications
Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V.
All typical specifications are at TA = 25°C, VDD = +5 V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Notes
Input Forward Voltage
VF
1.3
1.5
1.8
V
IF = 12 mA
1
Input Reverse
Breakdown Voltage
BVR
5
V
IR = 10 µA
Logic High Output
Voltage
VOH
4.0
4.8
V
IF = 0, IO = –20 µA
Logic Low Output
Voltage
VOL
0.01
0.1
V
IF = 12 mA, IO = 20 µA
Input Threshold Current
ITH
8.2
mA
IOL = 20 µA
2
Logic Low Output
Supply Current
IDDL
6.0
14.0
mA
IF = 12 mA
4
Logic High Output
Supply Current
IDDH
4.5
11.0
mA
IF = 0
3
Switching Specifications
Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V.
All typical specifications are at TA = 25°C, VDD = +5 V.
Parameter
Test Conditions
Fig.
Notes
Propagation Delay Time
tPHL
20
35
60
ns
to Logic Low Output
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
5
1
Propagation Delay Time
tPLH
13
21
60
ns
to Logic High Output
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
5
1
Pulse Width
Symbol
PW
Min.
Typ.
Max.
100
Units
ns
Pulse Width Distortion
|PWD|
0
14
30
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
2
2
Propagation Delay Skew
tPSK
40
ns
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
3
3
Output Rise Time
tR
20
ns
(10 - 90%)
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
Output Fall Time
tF
25
ns
(90 - 10%)
IF = 12 mA, CL = 15 pF
CMOS Signal Levels
Common Mode
|CMH|
10
15
kV/µs
Transient Immunity at
Logic High Output
VCM = 1000 V, TA = 25°C,
IF = 0 mA
4
4
Common Mode
|CML|
10
15
kV/µs
Transient Immunity at
Logic Low Output
VCM = 1000 V, TA = 25°C,
IF = 12 mA
5
5
Package Characteristics
All Typicals at TA = 25°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Input-Output Insulation
II-O
1
µA
Input-Output Momentary
VISO
3750
Vrms
Withstand Voltage
Test Conditions
45% RH, t = 5 s
VI-O = 3 kV dc,
TA = 25°C
RH ≤ 50%, t = 1 min.,
TA = 25°C
Input-Output Resistance
RI-O
1012
Ω
VI-O = 500 V dc
Input-Output Capacitance
CI-O
0.6
pF
f = 1 MHz, TA = 25°C
Notes:
1. tPHL propagation delay is measured from the 50% level on the risiing edge of the input pulse to the 2.5 V level of the falling edge of the VO
signal. tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the
VO signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
IF
TA = 25°C
+
VF
–
10
1.0
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.5
1.6
8
VDD = 5.0 V
IOL = 20 µA
7
6
5
4
3
2
-40
7.5
50
VDD = 5.0 V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
-40
0
25
85
100
TA – TEMPERATURE – °C
Figure 4. Typical logic low O/P supply current vs.
temperature.
HCPL-0708 fig 4
85
100
Figure 2. Typical input threshold current vs.
temperature.
tp – PROPAGATION DELAY – ns
Iddl – LOGIC LOW OUTPUT SUPPLY CURRENT – mA
8.0
25
TA – TEMPERATURE – °C
VF – FORWARD VOLTAGE – V
Figure 1. Typical input diode forward characteristic.
0
VDD = 5.0 V
TA = 25 °C
45
40
Tphl
35
30
25
Tplh
20
15
PWD
10
5
0
5
6
7
8
9 10 11 12 13 14
IF – PULSE INPUT CURRENT – mA
Figure 5. Typical switching speed vs. pulse input
current.
HCPL-0708 fig 5
Iddh – LOGIC HIGH OUTPUT SUPPLY CURRENT – mA
100
Ith – INPUT THRESHOLD CURRENT – mA
IF – FORWARD CURRENT – mA
1000
6.0
5.5
VDD = 5.0 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
-40
0
25
85
100
TA – TEMPERATURE – °C
Figure 3. Typical logic high O/P supply current vs.
temperature.
HCPL-0708 fig 3
Application Information
Bypassing and PC Board Layout
The HCPL-0708 optocoupler is extremely easy to use. No
external interface circuitry is required because the HCPL0708 uses high-speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
VDD
8
1
As shown in Figure 6, the only external component required for proper operation is the bypass capacitor. Capacitor values should be between 0.01 µF and 0.1 µF. For
each capacitor, the total lead length between both ends
of the capacitor and the power-supply pins should not
exceed 20 mm. Figure 7 illustrates the recommended
printed circuit board layout for the HPCL-0708.
C
2
XXX
YWW
IF
3
7 NC
6
VO
5
4
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 6. Recommended printed circuit board layout.
VDD
XXX
YWW
IF
C2
VO
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width Distortion and Propagation
Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system. The propaga­tion delay from low to high (tPLH) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low
12 mA
INPUT
IF
50%
0 mA
tPLH
OUTPUT
VO
Figure 8.
10
90%
10%
tPHL
90%
10%
VOH
2.5 V CMOS
VOL
to high. Similarly, the propagation delay from high to
low (tPHL) is the amount of time required for the input
signal to propagate to the output, causing the output to
change from high to low. See Figure 8.
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maxi­mum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being trans­mitted. Typically, PWD on the order of 20 - 30% of the minimum pulse
width is tolerable; the exact figure depends on the particular application.
Propagation delay skew, tPSK, is an important parameter
to con­sider in parallel data applications where synchronization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large
enough it will determine the maximum rate at which
parallel data can be sent through the optocouplers.
IF
VO
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 10 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
50%
DATA
INPUTS
2.5 V,
CMOS
CLOCK
tPSK
IF
Propagation delay skew is defined as the difference between the minimum and maximum propa­gation delays,
either tPLH or tPHL, for any given group of optocoup­lers
which are operating under the same conditions (i.e., the
same drive current, supply volt­age, output load, and operating temperature). As illustrated in Figure 9,­ if the inputs of a group of optocouplers are switched either ON
or OFF at the same time, tPSK is the difference between
the shortest propagation delay, either tPLH or tPHL, and
the longest propagation delay, either tPLH or tPHL.
50%
DATA
OUTPUTS
VO
2.5 V,
CMOS
tPSK
CLOCK
tPSK
Figure 9. Propagation delay skew waveform.
Propagation delay skew repre­sents the uncertainty of
where an edge might be after being sent through an optocoupler. Figure 10 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent
Figure 10. Parallel data transmission example.
through optocouplers in a parallel application is twice tPSK.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-0708 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV02-0877EN
AV02-0877EN January 8, 2008
12