LINER LTC1278-4I 12-bit, 500ksps sampling a/d converter with shutdown Datasheet

LTC1278
12-Bit, 500ksps Sampling
A/D Converter with Shutdown
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DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
Single Supply 5V or ±5V Operation
Two Speed Grades,500ksps (LTC1278-5)
400ksps (LTC1278-4)
70dB S/(N + D) and 74dB THD at Nyquist
No Missing Codes Over Temperature
75mW (Typ) Power Dissipation
Power Shutdown with Instant Wake-Up
Internal Reference Can Be Overdriven Externally
Internal Synchronized Clock; No Clock Required
High Impedance Analog Input
0V to 5V or ±2.5V Input Range
New Flexible, Friendly Parallel Interface to DSPs
and FIFOs
24-Pin Narrow PDIP and SW Packages
The LTC®1278 is a 1.6µs, 500ksps, sampling 12-bit A/D
converter that draws only 75mW from a single 5V or ±5V
supplies. This easy-to-use device comes complete with
a 200ns sample-and-hold, a precision reference and an
internally trimmed clock. Unipolar and bipolar conversion modes add to the flexibility of the ADC. The low
power dissipation is made even more attractive by a
8.5mW power-down feature. Instant wake-up from shutdown allows the converter to be powered down even
during brief inactive periods.
The LTC1278 converts 0V to 5V unipolar inputs from a
single 5V supply and ±2.5V bipolar inputs from ±5V
supplies. Maximum DC specs include ±1LSB INL and
±1LSB DNL. Outstanding guaranteed AC performance
includes 70dB S/(N + D) and 78dB THD at the input
frequency of 100kHz over temperature.
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APPLICATI
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S
High Speed Data Acquisition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
The internal clock is trimmed for 1.6µs conversion time.
The clock automatically synchronizes to each sample
command, eliminating problems with asynchronous clock
noise found in competitive devices. A separate convert
start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATI
Single 5V Supply, 500kHz, 12-Bit Sampling A/D Converter
LTC1278-5
+
10µF
24
+
23
22
21
20
19
18
17
10µF
0.1µF
µP CONTROL
LINES
CONVERSION START INPUT
POWER DOWN INPUT
16
15
14
12
74
11
68
10
62
NYQUIST
FREQUENCY
9
56
8
S/(N+D) (dB)
ANALOG INPUT 1 A
AVDD
(0V TO 5V) 2 IN
VREF
VSS
3
AGND
BUSY
0.1µF
4
D11(MSB) CS
5
D10
RD
6
D9
CONVST
7
D8
SHDN
8
D7
DVDD
9
D6
D0
10
12-BIT
D5
D1
PARALLEL
11
D4
D2
BUS
12
DGND
D3
EFFECTIVE NUMBER OF BITS
2.42V
REFERENCE
OUTPUT
Effective Bits and Signal-to-(Noise + Distortion)
vs Input Frequency
5V
7
6
5
4
3
2
13
1
0
10k
LTC1278 • TA01
fSAMPLE = 500kHz
100k
INPUT FREQUENCY (Hz)
1M
2M
LT1278 G4
1
LTC1278
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PACKAGE/ORDER I FOR ATIO
RATI GS
W W
W
AVDD = DVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) .............................................. 12V
Negative Supply Voltage (VSS)
Bipolar Operation Only .......................... – 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation............... VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)
Unipolar Operation ................................– 0.3V to 12V
Bipolar Operation........................... VSS – 0.3V to 12V
Digital Output Voltage
Unipolar Operation ................... – 0.3V to VDD + 0.3V
Bipolar Operation................ VSS – 0.3V to VDD + 0.3V
Power Dissipation ............................................. 500mW
Operating Temperature Range
LTC1278-4C, LTC1278-5C ..................... 0°C to 70°C
LTC1278-4I ....................................... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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CO VERTER CHARACTERISTICS
PARAMETER
AIN
1
24 AVDD
VREF
2
23 VSS
AGND
3
22 BUSY
D11(MSB)
4
21 CS
D10
5
20 RD
D9
6
19 CONVST
D8
7
18 SHDN
D7
8
17 DVDD
D6
9
16 D0
D5 10
15 D1
D4 11
14 D2
DGND 12
13 D3
N PACKAGE
24-LEAD PDIP
LTC1278-4CN
LTC1278-5CN
LTC1278-4IN
LTC1278-4CSW
LTC1278-5CSW
LTC1278-4ISW
SW PACKAGE
24-LEAD PLASTIC SO WIDE
TJMAX = 110°C, θJA = 100°C/W (N)
TJMAX = 110°C, θJA = 130°C/W (SW)
Consult factory for Military grade parts.
With Internal Reference (Notes 5, 6)
Resolution (No Missing Codes)
MIN
●
(Note 7)
Differential Linearity Error
Offset Error
ORDER
PART NUMBER
TOP VIEW
CONDITIONS
Integral Linearity Error
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AXI U
LTC1278-4/LTC1278-5
TYP
MAX
12
●
±1
●
±1
LSB
●
±4
±6
LSB
LSB
±15
LSB
ppm/°C
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A ALOG I PUT
LTC1278-4/LTC1278-5
MIN
TYP
MAX
UNITS
±10
●
(Note 5)
SYMBOL PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
4.95V ≤ VDD ≤ 5.25V (Unipolar)
4.75V ≤ VDD ≤ 5.25V, – 5.25V ≤ VSS ≤ – 2.45V (Bipolar)
●
●
IIN
Analog Input Leakage Current
CS = High
●
CIN
Analog Input Capacitance
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
2
LSB
±45
Gain Error
IOUT(REF) = 0
UNITS
Bit
(Note 8)
Gain Error Tempco
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ABSOLUTE
0 to 5
±2.5
V
V
±1
45
5
µA
pF
pF
LTC1278
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DY A IC ACCURACY
(Note 5)
LTC1278-4/LTC1278-5
MIN
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
100kHz Input Signal
250kHz Input Signal
●
THD
Total Harmonic Distortion
First 5 Harmonics
100kHz Input Signal
250kHz Input Signal
●
– 80
– 74
– 78
dB
dB
Peak Harmonic or Spurious Noise
100kHz Input Signal
250kHz Input Signal
●
– 84
– 74
– 78
dB
dB
Intermodulation Distortion
fIN1 = 99.37kHz, fIN2 = 102.4kHz
fIN1 = 249.37kHz, fIN2 = 252.4kHz
IMD
70
72
70
Full Linear Bandwidth (S/(N + D) ≥ 68dB)
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I TER AL REFERE CE CHARACTERISTICS
dB
dB
– 82
– 70
Full Power Bandwidth
dB
dB
4
MHz
350
kHz
(Note 5)
LTC1278-4/LTC1278-5
MIN
TYP
MAX
PARAMETER
CONDITIONS
VREF Output Voltage
IOUT = 0
VREF Output Tempco
IOUT = 0
VREF Line Regulation
4.95V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ – 4.95V
VREF Load Regulation
0V ≤ |IOUT| ≤ 1mA
2.400
●
2.420
2.440
±10
±45
0.01
0.01
UNITS
V
ppm/°C
LSB/V
LSB/V
2
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DIGITAL I PUTS A D DIGITAL OUTPUTS
UNITS
LSB/mA
(Note 5)
LTC1278-4/LTC1278-5
MIN
TYP
MAX
SYMBOL PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.95V
●
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
●
±10
µA
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDD = 4.95V
IO = – 10µA
IO = – 200µA
●
VDD = 4.95V
IO = 160µA
IO = 1.6mA
●
2.4
UNITS
V
5
pF
4.7
V
V
4
0.05
0.10
0.4
V
V
IOZ
High Z Output Leakage D11 to D0
VOUT = 0V to VDD, CS High
●
±10
µA
COZ
High Z Output Capacitance D11 to D0
CS High (Note 9 )
●
15
pF
ISOURCE
Output Source Current
VOUT = 0V
– 10
mA
ISINK
Output Sink Current
VOUT = VDD
10
mA
3
LTC1278
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POWER REQUIRE E TS
(Note 5)
SYMBOL PARAMETER
CONDITIONS
LTC1278-4/LTC1278-5
MIN
TYP
MAX
VDD
Positive Supply Voltage (Notes 10, 11)
Unipolar
Bipolar
4.95
4.75
5.25
5.25
V
V
VSS
Negative Supply Voltage (Note 10)
Bipolar Only
– 2.45
– 5.25
V
IDD
Positive Supply Current
fSAMPLE = 500ksps
SHDN = 0V
●
●
15.0
1.7
29.5
3.0
mA
mA
ISS
Negative Supply Current
fSAMPLE = 500ksps, VSS = – 5V
●
0.12
0.30
mA
PD
Power Dissipation
fSAMPLE = 500ksps
SHDN = 0V
●
75.0
8.5
150
15
mW
mW
LTC1278-4/LTC1278-5
MIN
TYP
MAX
UNITS
●
UNITS
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TI I G CHARACTERISTICS
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE(MAX)
Maximum Sampling Frequency
LTC1278-4
LTC1278-5
●
●
tSAMPLE(MIN)
Minimum Throughput Time
(Acquisition Time Plus Conversion Time)
LTC1278-4
LTC1278-5
●
●
tCONV
Conversion Time
LTC1278-4
LTC1278-5
tACQ
Acquisition Time
t1
CS↓ to RD↓ Setup Time
(Notes 9, 10)
●
0
ns
t2
CS↓ to CONVST↓ Setup Time
(Notes 9, 10)
●
20
ns
t3
SHDN↑ to CONVST↓ Wake-Up Time
(Note 10)
t4
CONVST Low Time
(Notes 10, 12)
t5
CONVST↓ to BUSY↓ Delay
CL = 100pF
Commercial
Industrial
●
●
CL = 100pF
●
20
●
– 20
400
500
2.0
1.6
2.5
2.0
µs
µs
2.3
1.85
µs
µs
200
ns
350
●
ns
40
Data Ready Before BUSY↑
t7
Wait Time RD↓ After BUSY↑
Mode 2, (see Figure 14) (Note 9)
t8
Data Access Time After RD↓
CL = 20pF (Note 9)
Commercial
Industrial
●
●
CL = 100pF
Commercial
Industrial
●
●
Commercial
Industrial
●
●
20
20
20
Bus Relinquish Time
ns
40
t6
t9
kHz
110
130
140
40
ns
ns
ns
ns
ns
50
90
110
120
ns
ns
ns
70
125
150
170
ns
ns
ns
30
75
85
90
ns
ns
ns
t10
RD Low Time
(Note 9)
●
t8
ns
t11
CONVST High Time
(Notes 9, 12)
●
40
ns
t12
Aperture Delay of Sample-and-Hold
Jitter < 50ps
4
15
ns
LTC1278
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TI I G CHARACTERISTICS
(Note 5)
The ● indicates specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS (ground for unipolar
mode) or above VDD, they will be clamped by internal diodes. This product
can handle input currents greater than 60mA below VSS (ground for
unipolar mode) or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS (ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 60mA below VSS (ground for unipolar mode)
without latch-up. These pins are not clamped to VDD.
Note 5: AVDD = DVDD = VDD = 5V, (VSS = – 5V for bipolar mode), fSAMPLE =
400kHz (LTC1278-4), 500kHz (LTC1278-5), tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve. The
deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 1/2LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: AIN must not exceed VDD or fall below VSS by more than 50mV for
specified accuracy. Therefore the minimum supply voltage for the unipolar
mode is 4.95V. The minimum for the bipolar mode is 4.75V, – 2.45V.
Note 12: The falling CONVST edge starts a conversion. If CONVST returns
high at a bit decision point during the conversion it can create small errors.
For best performance ensure that CONVST returns high either within 120ns
after conversion start (i.e., before the first bit decision) or after BUSY rises
(i.e., after the last bit test). See mode 1a and 1b (Figures 12 and 13) timing
diagrams.
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TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity vs
Output Code
1.0
fSAMPLE = 500kHz
DNL ERROR (LSB)
0.5
0
–0.5
0
–0.5
12
74
11
68
10
62
NYQUIST
FREQUENCY
9
56
8
S/(N+D) (dB)
INL ERROR (LSB)
0.5
fSAMPLE = 500kHz
EFFECTIVE NUMBER OF BITS
1.0
ENOBs and S/(N + D) vs
Input Frequency
Differential Nonlinearity vs
Output Code
7
6
5
4
3
2
1
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
LT1278 G1
–1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
LT1278 G2
0
10k
fSAMPLE = 500kHz
100k
INPUT FREQUENCY (Hz)
1M
2M
LT1278 G4
5
LTC1278
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TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
and Amplitude
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
VIN = 0dB
70
70
60
VIN = –20dB
50
40
30
20
VIN = –60dB
10
60
50
40
30
20
10
fSAMPLE = 500kHz
0
fSAMPLE = 500kHz
0
10k
100k
1M
INPUT FREQUENCY (Hz)
1k
10M
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
10M
LTC1278 G10
–60
–70
–40
–50
–60
2ND HARMONIC
–70
–80
THD
3RD HARMONIC
–90
–100
10k
100k
INPUT FREQUENCY (Hz)
1M
2M
4000
–40
–60
–80
3500
3000
2500
2000
1500
1000
–80
–100
500
–90
–100
10k
0
–120
1M
2M
0
50k
100k
150k
FREQUENCY (Hz)
200k
20
fSAMPLE = 500kHz
15
10
5
0
–55
–25
75
0
25
50
TEMPERATURE (C°)
100
125
10k
LTC1278 G9
Power Supply Feedthrough
vs Ripple Frequency
0
Reference Voltage vs Load Current
2.435
fSAMPLE = 500kHz
–20
2.430
–40
VSS (VRIPPLE = 10mV)
–60
DGND (VRIPPLE = 0.1V)
–80
AVDD (VRIPPLE = 1mV)
–100
–120
1k
10k
100k
2.425
2.420
2.415
2.410
1M
RIPPLE FREQUENCY (Hz)
LTC1278 G3
100
1k
RSOURCE (Ω)
LTC1278 G8
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
Supply Current vs Temperature
10
250k
REFERENCE VOLTAGE (V)
100k
INPUT FREQUENCY (Hz)
LTLTC1278 G11
6
–30
4500
ACQUISITION TIME (ns)
–50
–20
Acquisition Time vs
Source Impedance
fSAMPLE = 500kHz
fIN1 = 96.80kHz
fIN2 = 101.68kHz
–20
–20
–40
fSAMPLE = 500kHz
LT1278 G6
0
fSAMPLE = 500kHz
–30
–10
Intermodulation Distortion Plot
AMPLITUDE (dB)
SPURIOUS FREE DYNAMIC RANGE (dB)
0
–10
0
LTC1278 G5
Spurious Free Dynamic Range vs
Input Frequency
SUPPLY CURRENT (mA)
Distortion vs Input Frequency
80
SIGNAL TO NOISE RATIO (dB)
SIGNAL/(NOISE + DISTORTION) (dB)
80
Signal-to-Noise Ratio (without
Harmonics) vs Input Frequency
LTC1278 G7
2.405
–5
–4
–3
0
–2
–1
LOAD CURRENT (mA)
1
2
LTC1278 G12
LTC1278
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PI FU CTIO S
AIN (Pin 1): Analog Input. 0V to 5V (Unipolar), ±2.5V
(Bipolar).
RD (Pin 20): READ Input. This enables the output
drivers when CS is low.
VREF (Pin 2): 2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
CS (Pin 21): The CHIP SELECT input must be low for the
ADC to recognize CONVST and RD inputs.
AGND (Pin 3): Analog Ground.
BUSY (Pin 22): The BUSY output shows the converter
status. It is low when a conversion is in progress.
D11 to D4 (Pins 11 to 4): Three-State Data Outputs.
D11 is the Most Significant Bit.
DGND (Pin 12): Digital Ground.
D3 to D0 (Pins 13 to 16): Three-State Data Outputs.
DVDD (Pin 17 ): Digital Power Supply, 5V. Tie to AVDD pin.
VSS (Pin 23): Negative Supply. – 5V for bipolar operation. Bypass to AGND with 0.1µF ceramic. Analog
ground for unipolar operation.
AVDD (Pin 24): Positive Supply, 5V. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
SHDN (Pin 18): Power Shutdown.
CONVST (Pin 19): Conversion Start Signal. This active
low signal starts a conversion on its falling edge (to
recognize CONVST, CS has to be low).
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FU CTIO AL BLOCK DIAGRA
CSAMPLE
AVDD
AIN
ZEROING
SWITCH
DVDD
2.42V REF
VSS
(0V FOR UNIPOLAR MODE
OR –5V FOR BIPOLAR MODE)
VREF
COMPARATOR
12-BIT CAPACITIVE DAC
12
AGND
12
SUCCESSIVE APPROXIMATION
REGISTER
DGND
•
•
•
OUTPUT LATCHES
D11
D0
LTC1278 • BD
INTERNAL
CLOCK
CONTROL LOGIC
SHDN CONVST
RD
CS
BUSY
7
LTC1278
TEST CIRCUITS
Load Circuits for Access Timing
Load Circuits for Output Float Delay
5V
5V
3k
3k
DBN
DBN
DBN
3k
CL
DBN
3k
CL
DGND
10pF
DGND
DGND
DGND
A) VOH TO HIGH-Z
B) HIGH-Z TO VOL (t8)
AND VOH TO VOL (t6)
A) HIGH-Z TO VOH (t8)
AND VOL TO VOH (t6)
10pF
B) VOL TO HIGH-Z
1278 • TA08
LTC1278 TA08
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TI I G DIAGRA S
CS to CONVST Setup Timing
CS to RD Setup Timing
SHDN to CONVST Wake-Up Timing
CS
CS
SHDN
t2
t1
t3
CONVST
RD
CONVST
LTC1278 • TC02
LTC1278 • TC01
LTC1278 • TC03
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APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1278 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of conversion the successive approximation register (SAR) is reset. Once a conversion cycle
has begun it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
8
SAMPLE
SAMPLE
SI
CSAMPLE
–
AIN
HOLD
+
CDAC
COMPARATOR
DAC
VDAC
S
A
R
12-BIT
LATCH
LTC1278 F1
Figure 1. AIN Input
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 200ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
LTC1278
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APPLICATIONS INFORMATION
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.
The Effective Number of Bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
–20
–40
74
12
68
11
10
62
NYQUIST
FREQUENCY
9
56
8
S/(N+D) (dB)
fSAMPLE = 500kHz ±5V
fIN = 97.045kHz
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 500kHz the LTC1278 maintains very good ENOBs up
to the Nyquist input frequency of 250kHz. Refer to Figure 3.
EFFECTIVE NUMBER OF BITS
The LTC1278 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an
FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2
shows a typical LTC1278 FFT plot.
AMPLITUDE (dB)
Effective Number of Bits
N = [S/(N + D) – 1.76]/6.02
DYNAMIC PERFORMANCE
0
a 500kHz sampling rate and a 100kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 250kHz.
7
6
5
4
3
2
1
–60
fSAMPLE = 500kHz
0
10k
–80
100k
INPUT FREQUENCY (Hz)
1M
2M
LT1278 G4
Figure 3. Effective Bits and Signal-to-Noise + Distortion vs
Input Frequency
–100
–120
0
50k
100k
150k
FREQUENCY (Hz)
200k
250k
LTC1278 F2
Figure 2. LTC1278 Nonaveraged, 4096 Point FFT Plot
Signal-to-Noise Ratio
The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2 shows a typical spectral content with
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
THD = 20log
√V22 + V32 + V42 ... + VN2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input
9
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0
–10
fSAMPLE = 500kHz
–20
–30
fSAMPLE = 500kHz
fIN1 = 96.80kHz
fIN2 = 101.68kHz
–20
–40
–60
–80
–40
–100
–50
–60
–70
–80
THD
0
50k
100k
150k
FREQUENCY (Hz)
200k
250k
LTC1278 G8
3RD HARMONIC
–90
–100
10k
–120
2ND HARMONIC
Figure 5. Intermodulation Distortion Plot
100k
INPUT FREQUENCY (Hz)
1M
2M
LT1278 G6
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa + fb) and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
waves are equal in magnitude, the value (in decibels) of
the 2nd order IMD products can be expressed by the
following formula:
IMD (fa ± fb) = 20log
Amplitude at (fa ± fb)
Amplitude at fa
Figure 5 shows the IMD performance at a 100kHz input.
10
0
AMPLITUDE (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
frequency is shown in Figure 4. The LTC1278 has good
distortion performance up to the Nyquist frequency and
beyond.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal.
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1278 has been designed to optimize input bandwidth,
allowing ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise
floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond
Nyquist.
Driving the Analog Input
The analog input of the LTC1278 is easy to drive. It draws
only one small current spike while charging the sampleand-hold capacitor at the end of conversion. During conversion the analog input draws no current. The only
requirement is that the amplifier driving the analog input
must settle after the small current spike before the next
LTC1278
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conversion starts. Any op amp that settles in 200ns to
small current transients will allow maximum speed operation. If slower op amps are used, more settling time can be
provided by increasing the time between conversions.
Suitable devices capable of driving the ADC’s AIN input
include the LT1360, LT1220, LT1223 and LT1224 op
amps.
INPUT RANGE
±2.58V
(= ±1.033 × VREF)
Internal Reference
Figure 7. Supplying a 2.5V Reference Voltage to the LTC1278
with the LT1019A-2.5
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
The VREF pin can be driven with a DAC or other means to
provide input span adjustment in bipolar mode. The VREF
pin must be driven to at least 2.45V to prevent conflict with
the internal reference. The reference should be driven to
no more than 4.8V to keep the input span within the ±5V
supplies.
Figure 6 shows an LT1006 op amp driving the reference
pin. (In the unipolar mode, the input span is already 0V to
5V with the internal reference so driving the reference is
not recommended, since the input span will exceed the
supply and codes will be lost at the full scale.) Figure 7
shows a typical reference, the LT1019A-2.5 connected to
the LTC1278. This will provide an improved drift (equal to
the maximum 5ppm/°C of the LT1019A-2.5) and a ±2.582V
full scale.
5V
VOUT
LT1019A-2.5
VREF(OUT) ≥ 2.45V
LT1006
–
VREF
3Ω
LTC1278 F7
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
Figure 8a shows the ideal input/output characteristics for
the LTC1278. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, ... FS – 1.5LSB). The output code is naturally
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
8b shows the input/output transfer characteristics for the
bipolar mode in two’s complement format.
1LSB = FS = 5V
4096 4096
111...111
111...110
111...101
111...100
UNIPOLAR
ZERO
000...011
000...010
000...001
000...000
0V
1
LSB
FS – 1LSB
INPUT VOLTAGE (V)
LTC1278 F8a
Figure 8a. LTC1278 Unipolar Transfer Characteristics
011...111
OUTPUT CODE
+
AGND
10µF
–5V
BIPOLAR
ZERO
011...110
LTC1278
AIN
VREF
3Ω
GND
5V
INPUT RANGE
±1.033VREF(OUT)
LTC1278
AIN
VIN
OUTPUT CODE
The LTC1278 has an on-chip, temperature compensated,
curvature corrected, bandgap reference, which is factory
trimmed to 2.42V. It is internally connected to the DAC and
is available at Pin 2 to provide up to 1mA current to an
external load.
5V
000...001
000...000
111...111
111...110
AGND
100...001
10µF
–5V
FS = 5V
1LSB = FS/4096
100...000
LTC1278 F6
–FS/2
Figure 6. Driving the VREF with the LT1006 Op Amp
–1 0V 1
LSB
LSB
INPUT VOLTAGE (V)
FS/2 – 1LSB
LTC1278 • F8b
Figure 8b. LTC1278 Bipolar Transfer Characteristics
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R1
50Ω
ANALOG
INPUT
+
V1
A1
–
R2
10k
FULL-SCALE
ADJUST
AGND
LTC1278 F9a
ANALOG
INPUT
0V TO 5V
10k
R9
20Ω
R3
100k R7
100k
LTC1278
R8
20k
OFFSET
ADJUST
LTC1278 F9c
Figure 9c. LTC1278 Bipolar Offset and Full-Scale Adjust Circuit
AIN
–
5V
R5
4.3k
FULL-SCALE
5V
ADJUST
–5V
+
R2
10k
R4
100k
R6
200Ω
Figure 9a. Full-Scale Adjust Circuit
R1
10k
AIN
–
R4
100Ω
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
+
R2
10k
AIN
LTC1278
R3
10k
R1
10k
R4
100k
R5
4.3k
FULL-SCALE
5V
ADJUST
R3
100k R7
100k
R6
400Ω
LTC1278
R8
10k
OFFSET
ADJUST
LTC1278 F9b
driving the analog input of the LTC1278 while the input
voltage is 1/2LSB below ground. This is done by applying
an input voltage of – 0.61mV (– 0.5LSB) to the input in
Figure 9c and adjusting the R8 until the ADC output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, an input voltage of 2.49817V
(FS – 1.5LSBs) is applied to the input and R5 is adjusted
until the output code flickers between 0111 1111 1110
and 0111 1111 1111.
Figure 9b. LTC1278 Unipolar Offset and Full-Scale Adjust Circuit
BOARD LAYOUT AND BYPASSING
Unipolar Offset and Full-scale Error Adjustments
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1278, a printed circuit board is
required. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
In applications where absolute accuracy is important, then
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. For zero offset
error apply 0.61mV (i.e., 1/2LSB) at the input and adjust
the offset trim until the LTC1278 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error apply an analog input of 4.99817V (i.e., FS
– 1 1/2LSB or last code transition) at the input and adjust
R5 until the LTC1278 output code flickers between 1111
1111 1110 and 1111 1111 1111.
Bipolar Offset and Full-scale Error Adjustments
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error adjustment is achieved by trimming the offset of the op amp
12
High quality tantalum and ceramic bypass capacitors
should be used at the AVDD and VREF pins as shown in
Figure 10. For the bipolar mode, a 0.1µF ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Input signal leads to AIN and signal return leads from
AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended.
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Also, since any potential difference in grounds between
the signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedances as much as
possible.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at Pin 3 (AGND) or as close as possible to the
ADC. Pin 12 (DGND) and all other analog grounds should
be connected to this single analog ground point. No other
digital grounds should be connected to this analog ground
point. Low impedance analog and digital power supply
common returns are essential to low noise operation of
the ADC and the foil width for these tracks should be as
wide as possible. In applications where the ADC data
outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get
errors in conversion results. These errors are due to
feedthrough from the microprocessor to the successive
approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to isolate the ADC data bus.
1
ANALOG
INPUT
CIRCUITRY
–
The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion.
Internal Clock
The A/D converter has an internal clock that eliminates the
need of synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.6µs. No external adjustments are required, and
with the typical acquisition time of 250ns, throughput
performance of 500ksps is assured.
Power Shutdown
The LTC1278 provides a shutdown feature that will save
power when the ADC is in inactive periods. To power down
the ADC, Pin 18 (SHDN) needs to be driven low. When in
power shutdown mode, the LTC1278 will not start a
conversion even though the CONVST goes low. All the
DIGITAL
SYSTEM
LTC1278
AIN
AGND
+
DIGITAL INTERFACE
3
10µF
VREF
AVDD
DVDD
DGND
2
24
17
12
0.1µF
10µF
GROUND CONNECTION
TO DIGITAL CIRCUITRY
0.1µF
ANALOG GROUND PLANE
LTC1278 F10
Figure 10. Power Supply Grounding Practice
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
RD
BUSY
CS
D
CONVST
SHDN
Q
CONVERSION
START (RISING
EDGE TRIGGER)
FLIP
FLOP
CLEAR
LTC1278 F11
Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN
13
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power is off except the Internal Reference which is still
active and provides 2.42V output voltage to the other
circuitry. In this mode the ADC draws 8.5mW instead of
75mW (for minimum power, the logic inputs must be
within 600mV of the supply rails). The wake-up time from
the power shutdown to active state is 350ns.
In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.
In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVST and RD are tied together. The MPU
starts conversion and read the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic “0” for CONVST will start a conversion after the ADC
has been selected (i.e., CS is low). Once initiated it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.
In Slow memory mode the processor takes RD (= CONVST)
low and starts the conversion. BUSY goes low forcing the
processor into a WAIT state. The previous conversion
result appears on the data outputs. When the conversion
is complete, the new conversion results appear on the
data outputs; BUSY goes high releasing the processor,
and the processor takes RD (= CONVST) back high and
reads the new conversion data.
Figures 12 through 16 show several different modes of
operation. In modes 1a and 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow low going CONVST pulse. Mode
1b shows high going CONVST pulse.
In ROM mode, the processor takes RD (= CONVST) low
which starts a conversion and reads the previous conversion
result. After the conversion is complete, the processor can
read the new result (which will initiate another conversion).
tCONV
CS = RD = 0
t4
SAMPLE N + 1
SAMPLE N
CONVST
t5
BUSY
t6
DATA (N-1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1278 F12
Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST =
)
tCONV
CS = RD = 0
t11
SAMPLE N
SAMPLE N + 1
t5
t5
CONVST
BUSY
t6
DATA
DATA (N-1)
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB0
LTC1278 F13
Figure 13. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled. (CONVST =
14
)
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t11
CS = 0
tCONV
t4
SAMPLE N + 1
SAMPLE N
CONVST
t5
BUSY
t7
t9
t10
RD
t8
DATA N
DB11 TO DB0
DATA
DATA (N + 1)
DB11 TO DB0
LTC1278 F14
Figure 14. Mode 2. CONVST Starts a Conversion. Data is Read by RD
tCONV
CS = 0
SAMPLE N
SAMPLE N + 1
RD = CONVST
t5
t9
BUSY
t8
t6
DATA (N – 1)
DB11 TO DB0
DATA
DATA N
DB11 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11-DB0
LTC1278 F15
Figure 15. Slow Memory Mode
tCONV
CS = 0
SAMPLE N
SAMPLE N + 1
RD = CONVST
t5
t9
BUSY
t8
DATA
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB0
LTC1278 F16
Figure 16. ROM Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1278
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Dimensions in inches (millimeters) unless otherwise noted.
N Package
24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265*
(32.131)
MAX
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
0.255 ± 0.015*
(6.477 ± 0.381)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
(
0.125
(3.175)
MIN
+0.035
0.325 –0.015
+0.889
8.255
–0.381
0.065
(1.651)
TYP
)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N24 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package
24-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.598 – 0.614*
(15.190 – 15.600)
24
23
22
21
20
19
18
17
16
15
14
13
0.291 – 0.299**
(7.391 – 7.595)
0.093 – 0.104
(2.362 – 2.642)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.037 – 0.045
(0.940 – 1.143)
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
0.050
(1.270)
TYP
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
TYP
0.016 – 0.050
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
S24 (WIDE) 0996
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER
LTC1274/LTC1277
LTC1279
LTC1400
LTC1409
LTC1415
LTC1419
16
DESCRIPTION
12-Bit, 10mW, 100ksps A/D Converters with 1µA Shutdown
12-Bit, 600ksps Sampling A/D Converter with Shutdown
12-Bit, 400ksps Serial A/D Converter
12-Bit, 800ksps Sampling A/D Converter with Shutdown
12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
14-Bit, 800ksps Sampling A/D Converter with Shutdown
Linear Technology Corporation
COMMENTS
Complete with Clock Reference
70dB SINAD at Nyquist, Low Power
Complete High Speed 12-Bit ADC in SO-8
Fast, Complete Low Power ADC
Single 5V Supply, Low Power: 55mW
81.5dB SINAD, Low Power: 150mW
1278fa LT/GP 0998 REV A 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1994