Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LPV801, LPV802 SNOSCZ3 – AUGUST 2016 1 Features 3 Description • • • • • • • • • • • • The LPV801 (single) and LPV802 (dual) comprise a family of ultra-low-power operational amplifiers for “Always ON” sensing applications in wireless and low power wired equipment. With 8kHz of bandwidth from 320nA of quiescent current, the LPV80x amplifiers minimize power consumption in equipment such as CO detectors, smoke detectors and motion detecting security systems where operational battery-life is critical. 1 Nanopower Supply Current: 320 nA/channel (typ) Offset Voltage: 3.5 mV (max) Good TcVos: 1.5 µV/°C (typ) Unity Gain-Bandwidth: 8 kHz Unity-Gain Stable Low Input Bias Current : 0.1pA (typ) Wide Supply Range: 1.6 V to 5.5 V Rail-to-Rail Output No Output Reversals EMI Protection Temperature Range: –40°C to 125°C Industry Standard Packages: – Single in 5-pin SOT-23 – Dual in 8-pin VSSOP 2 Applications • • • • • • • Gas Detectors such as CO and O2 Motion Detectors Using PIR Sensors Ionization Smoke Alarms Thermostats Remote Sensors, IoT Active RFID Readers and Tags Portable Medical Equipment In addition to being ultra-low-power, the LPV80x amplifiers have CMOS input stages with typically femto-amp bias currents which reduces errors commonly introduced in transimpedance amplifier (TIA) configurations with megaohm feedback resistors and high source impedance sensing applications. The LPV80x amplifiers also feature a negative-rail sensing input stage and a rail-to-rail output stage that is capable of swinging within millivolts of the rails, maintaining the widest dynamic range possible. EMI protection is designed into the LPV80x in order to reduce system sensitivity to unwanted RF signals from mobile phones, WiFi, radio transmitters and tag readers. The LPV80x amplifiers operate with a total supply voltage as low as 1.6V, ensuring continuous performance in low battery situations over the extended temperature range of –40ºC to 125ºC. The single and dual channel versions are available in industry standard 5-pin SOT-23 and 8-pin VSSOP packages respectively. Device Information (1) PART NUMBER PACKAGE BODY SIZE LPV801 SOT-23 (5) 2.90 mm x 1.60 mm LPV802 VSSOP (8) 3.00 mm × 3.00 mm (1) Nanopower Electrochemical Sensor Amplifier For all available packages, see the orderable addendum at the end of the datasheet. Nanopower PIR Motion Sensor Amplifier CE RE WE VREF + LPV802a + IR CF LPV802a Output to Comparator VREF + LPV802b RF RLoad VREF VOUT + LPV802b 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice. PRODUCT PREVIEW LPV801/LPV802 320 nA Nanopower Operational Amplifiers LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. 8 8.1 Application Information............................................ 15 8.2 Typical Application: Three Terminal CO Gas Sensor Amplifier ................................................................... 15 8.3 Do's and Don'ts ...................................................... 18 9 Power Supply Recommendations...................... 18 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Example .................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description ............................................ 13 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Application and Implementation ........................ 15 13 13 13 13 Device Support .................................................... Receiving Notification of Documentation Updates Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 PRODUCT PREVIEW 4 Revision History 2 DATE REVISION NOTES June 2016 * Initial release Product Preview Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 5 Pin Configuration and Functions LPV802 8-Pin VSSOP DGK Package Top View LPV801 5-Pin SOT-23 DBV Package Top View OUT A OUT 1 V- 2 +IN 3 5 1 8 V+ 7 OUT B A V+ -IN A 2 B 4 +IN A 3 6 -IN B V- 4 5 +IN B -IN Pin Functions: LPV801 DBV I/O DESCRIPTION NUMBER OUT 1 O Output -IN 2 I Inverting Input +IN 3 I Non-Inverting Input V- 4 P Negative (lowest) power supply V+ 5 P Positive (highest) power supply PRODUCT PREVIEW PIN NAME Pin Functions: LPV802 DGK PIN I/O DESCRIPTION NAME NUMBER OUT A 1 O Channel A Output -IN A 2 I Channel A Inverting Input +IN A 3 I Channel A Non-Inverting Input V- 4 P Negative (lowest) power supply +IN B 5 I Channel B Non-Inverting Input -IN B 6 I Channel B Inverting Input OUT B 7 O Channel B Output V+ 8 P Positive (highest) power supply Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 3 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.3 6 V Common mode (V-) - 0.3 (V+) + 0.3 V Differential (V-) - 0.3 (V+) + 0.3 V -10 10 mA Continuous Continuous Operating temperature –40 125 °C Storage temperature, Tstg –65 150 °C 150 °C Supply voltage, Vs = (V+) - (V-) Voltage Input pins Input pins (2) (3) Current Output short current (4) Junction temperature (1) (2) (3) PRODUCT PREVIEW (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Not to exceed -0.3V or +6.0V on ANY pin, referred to VInput terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current-limited to 10 mA or less. Short-circuit to Vs/2, one amplifer per package. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage (V+ – V–) 1.6 5.5 V Specified temperature -40 125 °C 6.4 Thermal Information THERMAL METRIC (1) LPV801 DBV 5 PINS LPV802 DGK 8 PINS 184.2 θJA Junction-to-ambient thermal resistance 177.4 θJCtop Junction-to-case (top) thermal resistance 133.9 75.3 θJB Junction-to-board thermal resistance 36.3 105.5 ψJT Junction-to-top characterization parameter 23.6 13.5 ψJB Junction-to-board characterization parameter 35.7 103.9 (1) 4 UNIT ºC/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 6.5 Electrical Characteristics TA = 25°C, VS = 1.8V to 5 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX VS = 1.8V, 3.3V, and 5V, VCM = V- 0.55 ±3.5 VS = 1.8V, 3.3V, and 5V, VCM = (V+) – 0.9 V 0.55 ±3.5 UNIT OFFSET VOLTAGE VOS Input offset voltage ΔVOS/ΔT Input offset drift VCM = V- PSRR Power-supply rejection ratio VS = 1.8V to 5V, VCM = V- mV TA = –40°C to 125°C 1.5 1.6 µV/°C 60 µV/V 4.1 V INPUT VOLTAGE RANGE VCM Common-mode voltage range VS = 5 V CMRR Common-mode rejection ratio (V–) ≤ VCM ≤ (V+) – 0.9 V, VS= 5V 0 80 98 dB INPUT BIAS CURRENT IB Input bias current VS = 1.8V 100 IOS Input offset current VS = 1.8V 100 fA Differential 8 Common mode PRODUCT PREVIEW INPUT IMPEDANCE pF 3.8 NOISE En Input voltage noise ƒ = 0.1 Hz to 10 Hz 25 en Input voltage noise density ƒ = 100 Hz 340 ƒ = 1 kHz 420 Open-loop voltage gain (V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL = 100 kΩ 135 VOH Voltage output swing from positive rail VS = 1.8V, RL = 100 kΩ to V+/2 VOL Voltage output swing from negative rail VS = 1.8V, RL = 100 kΩ to V+/2 ISC Short-circuit current Short to VS/2 ZO Open loop output impedance ƒ = 1 KHz, IO = 0 A µVp-p nV/√Hz OPEN-LOOP GAIN AOL dB OUTPUT 10 6 mV 4 10 4.7 mA 94.5 kΩ 8 kHz FREQUENCY RESPONSE GBP Gain-bandwidth product SR Slew rate (10% to 90%) CL = 20 pF, RL = 10 MΩ, VS = 5V G = 1, Rising Edge, CL = 20 pF, VS = 5V 1.8 G = 1, Falling Edge, CL = 20 pF, VS = 5V 1.7 V/ms POWER SUPPLY IQ-LPV801 Quiescent Current, Per Channel VCM = V-, IO = 0, VS = 3.3 V 450 550 nA IQ-LPV802 Quiescent Current, Per Channel VCM = V-, IO = 0, VS = 3.3 V 320 415 nA (1) LPV801 Specifications are Preliminary until released. Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 5 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com 6.6 Typical Characteristics at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 600 Supply Current per Channel (nA) Supply Current per Channel (nA) 600 +125°C 500 400 +25°C 300 200 -40°C 100 0 2 2.5 3 3.5 4 4.5 5 Supply Voltage (V) +25°C 300 200 -40°C 100 5.5 1.5 2 2.5 3 3.5 4 4.5 5 Supply Voltage (V) RL=No Load 5.5 C002 VCM = V+ RL=No Load Figure 1. Supply Current vs. Supply Voltage, Low VCM Figure 2. Supply Current vs. Supply Voltage, High VCM 800 800 +125°C +25°C -40°C 700 600 Supply Current per Channel (nA) PRODUCT PREVIEW Supply Current per Channel (nA) 400 C001 VCM = V- 500 400 300 200 100 125°C 25°C -40°C 700 600 500 400 300 200 100 0 0 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Common Mode Voltage (V) VS= 1.8V VCM = V+ -0.2 2.0 800 RL= No Load 200 2.6 3.0 3.5 C002 RL= No Load +25°C 600 300 2.1 +125°C 800 400 1.7 Figure 4. Supply Current vs. Common Mode Voltage, 3.3V 1000 500 1.2 VS= 3.3V Offset Voltage (µV) 600 0.7 Common Mode Voltage (V) +125°C +25°C -40°C 700 0.3 C002 Figure 3. Supply Current vs. Common Mode Voltage, 1.8V Supply Current per Channel (nA) +125°C 0 1.5 -40°C 400 200 0 ±200 ±400 ±600 100 ±800 0 ±1000 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 Common Mode Voltage (V) VS= 5V Submit Documentation Feedback -0.3 0 RL= No Load 0.3 0.6 0.9 1.2 Common Mode Voltage (V) C003 Figure 5. Supply Current vs. Common Mode Voltage, 5V 6 500 VS= 1.8V 1.5 1.8 C002 RL= 10MΩ Figure 6. Typical Offset Voltage vs. Common Mode Voltage, 1.8V Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 Typical Characteristics (continued) at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 1000 +25°C 600 Offset Voltage (µV) -40°C 400 +125°C 800 +25°C 600 200 0 ±200 ±400 -40°C 400 200 0 ±200 ±400 ±600 ±600 ±800 ±800 ±1000 ±1000 -0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 Common Mode Voltage (V) 3.3 -0.5 0 0.5 VS= 3.3V RL= 10MΩ Figure 7. Typical Offset Voltage vs. Common Mode Voltage, 3.3V 1 1.5 2 2.5 3 3.5 4 4.5 Common Mode Voltage (V) C002 5 C002 VS= 5V RL= 10MΩ Figure 8. Typical Offset Voltage vs. Common Mode Voltage, 5V 100 1k 80 Input Bias Current (fA) Input Bias Current (pA) 100 10 1 100m 60 40 20 0 ±20 ±40 ±60 10m ±80 ±100 1m ±50 ±25 0 25 50 75 100 Temperature (ƒC) VS= 5V TA = -40 to 125 0.3 0.6 0.9 1.2 1.5 Common Mode Voltage (V) C001 VS= 1.8V VCM = Vs/2 1.8 C001 TA = -40°C Figure 10. Input Bias Current vs. Common Mode Voltage at 40°C Figure 9. Input Bias Current vs. Temperature 1000 500 800 400 600 300 Input Bias Current (pA) Input Bias Current (fA) 0.0 125 400 200 0 ±200 ±400 200 100 0 ±100 ±200 ±600 ±300 ±800 ±400 ±1000 ±500 0.0 0.3 0.6 0.9 1.2 Common Mode Voltage (V) VS= 1.8V 1.5 1.8 TA = 25°C Figure 11. Input Bias Current vs. Common Mode Voltage at 25°C Copyright © 2016, Texas Instruments Incorporated 0.0 0.3 0.6 0.9 1.2 1.5 Common Mode Voltage (V) C004 VS= 1.8V 1.8 C003 TA = 125°C Figure 12. Input Bias Current vs. Common Mode Voltage at 125°C Submit Documentation Feedback 7 PRODUCT PREVIEW Offset Voltage (µV) 1000 +125°C 800 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Typical Characteristics (continued) 100 1000 80 800 60 600 Input Bias Current (fA) Input Bias Current (fA) at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 40 20 0 ±20 ±40 ±60 400 200 0 ±200 ±400 ±600 ±80 ±800 ±100 ±1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Common Mode Voltage (V) VS= 5V 5.0 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common Mode Voltage (V) TA = -40°C VS= 5V Figure 13. Input Bias Current vs. Common Mode Voltage at 40°C 4.5 5.0 C005 TA = 25°C Figure 14. Input Bias Current vs. Common Mode Voltage at 25°C 500 140 PRODUCT PREVIEW 400 120 300 100 200 CMRR (dB) Input Bias Current (pA) 0.5 C002 100 0 ±100 ±200 80 60 40 ±300 20 ±400 ±500 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Common Mode Voltage (V) VS= 5V 4.5 5.0 1 10 100 1k 10k Frequency (Hz) C006 TA = 125°C TA = 25 VS= 5V VCM = Vs/2 Figure 15. Input Bias Current vs. Common Mode Voltage at 125°C C001 RL= 10MΩ CL= 20p AV = +1 ΔVCM = 0.5Vpp Figure 16. CMRR vs Frequency 100 10 90 Output Swing from V+ (V) 80 PSRR (dB) 70 60 50 40 30 20 1 +125°C +25°C -40°C 100m 10m 1m 10 0 1 10 100 1k 10k Frequency (Hz) TA = 25 VS= 5V VCM = Vs/2 RL= 10MΩ CL= 20p AV = +1 Submit Documentation Feedback 1m Output Sourcing Current (A) C002 ΔVCM = 0.5Vpp Figure 17. ±PSRR vs Frequency 8 100k TA = 25 VS= 5V VCM = Vs/2 RL= 10MΩ CL= 20p AV = +1 10m C003 ΔVS = 0.2Vpp Figure 18. Output Swing vs. Sourcing Current, 1.8V Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 Typical Characteristics (continued) at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 10 +125°C +125°C +25°C -40°C 1 Output Swing from V+ (V) Output Swing from V- (V) +25°C -40°C 100m 10m 1m 1m 1m RL= No Load 100m 10m 1m 1m +125°C +25°C -40°C 1 100m 10m 1m 10m 1m RL= No Load Figure 21. Output Swing vs. Sinking Current, 3.3V 10m Output Sourcing Current (A) C005 VS= 3.3V RL= No Load Figure 20. Output Swing vs. Sourcing Current, 3.3V Output Swing from V+ (V) Output Swing from V- (V) +125°C +25°C -40°C 10m C001 VS= 3.3V 10 Output Sinking Current (A) VS= 5V C002 RL= No Load Figure 22. Output Swing vs. Sourcing Current, 5V +125°C +25°C -40°C 1 50 mV/div Output Swing from V- (V) 1m Output Sourcing Current (A) Figure 19. Output Swing vs. Sinking Current, 1.8V 10 10m C006 VS= 1.8V 1 100m 10m Output Sinking Current (A) 10 1 PRODUCT PREVIEW 10 100m 10m 1m 1m VS= 5V 500 us/div 10m Output Sinking Current (A) C002 C004 RL= No Load Figure 23. Output Swing vs. Sinking Current, 5V TA = 25 VS= ±0.9V RL= 10MΩ CL= 20pF Vout = 200mVpp AV = +1 Figure 24. Small Signal Pulse Response, 1.8V Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 9 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Typical Characteristics (continued) 50 mV/div 200 mV/div at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 500 us/div 500 us/div C002 TA = 25 VS= ±2.5V RL= 10MΩ CL= 20pF C002 Vout = 200mVpp AV = +1 TA = 25 VS= ±0.9V Figure 25. Small Signal Pulse Response, 5V RL= 10MΩ CL= 20pF Vout = 1Vpp AV = +1 Figure 26. Large Signal Pulse Response, 1.8V PRODUCT PREVIEW 200 mV/div 500 mV/div V+ Input Output V- 500 us/div 500 us/div C002 RL= 10MΩ CL= 20pF C002 Vout = 2Vpp AV = +1 TA = 25 VS= ±0.9V Figure 27. Large Signal Pulse Response, 5V RL= 10MΩ CL= 20pF Vout = ±0.9Vpp AV = +1 Figure 28. Rail to Rail Input Response, 1.8V 160 V+ 140 125°C 25°C -40°C GAIN 120 Output AOL (dB) 500 mV/div Input 80 90 68 60 PHASE TA = 25 VS= ±2.5V 45 20 23 0 0 1m RL= 10MΩ CL= 20pF 10m 100m 1 10 100 Frequency (Hz) C002 Vout = ±2.5Vpp AV = +1 135 113 ±20 500 us/div 158 100 40 V- 180 TA = -40, 25, 125°C VS= 5V Phase (ƒ) TA = 25 VS= ±2.5V RL= 10MΩ CL= 20pF 1k 10k -23 100k C001 VOUT = 200mVPP VCM = Vs/2 Figure 30. Open Loop Gain and Phase, 5V, 10 MΩ Load Figure 29. Rail to Rail Input Response, 5V 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 Typical Characteristics (continued) at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 140 135 120 100 113 100 113 80 90 80 90 60 68 60 68 PHASE 40 20 23 20 23 0 0 0 0 10m 100m 1 10 100 1k 10k Frequency (Hz) TA = -40, 25, 125°C VS= 3.3V 1m 10m 100m VOUT = 200mVPP VCM = Vs/2 TA = -40, 25, 125°C VS= 5V 100 1k 10k -23 100k C003 RL= 1MΩ CL= 20pF VOUT = 200mVPP VCM = Vs/2 Figure 32. Open Loop Gain and Phase, 5V, 1 MΩ Load Figure 31. Open Loop Gain and Phase, 3.3V, 10 MΩ Load 160 10 Frequency (Hz) C002 RL= 10MΩ CL= 20pF 1 140 135 120 100 113 100 113 80 90 80 90 60 68 GAIN 120 PHASE 40 AOL (dB) 160 158 125°C 25°C -40°C Phase (ƒ) 180 140 125°C 25°C -40°C GAIN 180 158 135 68 60 PHASE 45 40 20 23 20 23 0 0 0 0 ±20 1m 10m 100m 1 10 100 1k 10k -23 100k Frequency (Hz) TA = -40, 25, 125°C VS= 3.3V ±20 1m 10m 100m VOUT = 200mVPP VCM = Vs/2 1 10 100 1k 10k -23 100k Frequency (Hz) C002 RL= 1MΩ CL= 20pF 45 TA = -40, 25, 125°C VS= 5V Figure 33. Open Loop Gain and Phase, 3.3V, 1 MΩ Load C001 RL= 100kΩ CL= 20pF VOUT = 200mVPP VCM = Vs/2 Figure 34. Open Loop Gain and Phase, 5V, 100kΩ Load 158 140 135 120 100 113 100 113 80 90 80 90 60 68 140 125°C 25°C -40°C GAIN 120 PHASE AOL (dB) 160 Phase (ƒ) 180 160 125°C 25°C -40°C GAIN 180 158 135 68 60 PHASE 45 40 20 23 20 23 0 0 0 0 40 ±20 1m 10m 100m 1 10 100 Frequency (Hz) TA = -40, 25, 125°C VS= 3.3V RL= 100kΩ CL= 20pF 1k 10k -23 100k ±20 1m 10m 100m 1 10 100 1k 10k -23 100k Frequency (Hz) C002 VOUT = 200mVPP VCM = Vs/2 Figure 35. Open Loop Gain and Phase, 3.3V, 100kΩ Load Copyright © 2016, Texas Instruments Incorporated 45 TA = -40, 25, 125°C VS= 1.8V RL= 10MΩ CL= 20pF C003 VOUT = 200mVPP VCM = Vs/2 Figure 36. Open Loop Gain and Phase, 1.8V, 10 MΩ Load Submit Documentation Feedback 11 PRODUCT PREVIEW 1m 45 ±20 -23 100k ±20 AOL (dB) 135 45 40 AOL (dB) 158 Phase (ƒ) AOL (dB) PHASE GAIN Phase (ƒ) GAIN 120 180 125°C 25°C -40°C Phase (ƒ) 125°C 25°C -40°C AOL (dB) 160 158 140 Phase (ƒ) 180 160 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Typical Characteristics (continued) at TA = 25°C, VS = 5V, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified. 160 140 AOL (dB) 10k 113 80 90 60 68 PHASE 45 20 23 0 0 ±20 100 100m 1m 1 10 100 1k 10k TA = 25°C C001 VS= 5 V 10m RL= 10MΩ 1 10 100 1k 10k C003 RL= 1MΩ CL= 20pF VOUT = 200mVPP VCM = Vs/2 Figure 38. Open Loop Gain and Phase, 1.8V, 1 MΩ Load 10000 160 125°C 25°C -40°C GAIN 120 1000 AOL (dB) PRODUCT PREVIEW 140 100 10 100 1k 90 68 60 PHASE 45 20 23 0 0 TA = 25 VS= 5V RL= 1MΩ CL= 20pF 10m 100m 10k C001 VCM = Vs/2 AV = +1 135 80 1m Frequency (Hz) 158 113 ±20 1 180 100 40 10 100m -23 100k Frequency (Hz) TA = -40, 25, 125°C VS= 1.8V Figure 37. Open Loop Output Impedance 9ROWDJH 1RLVH Q9¥5W+] 100m 100k Frequency (Hz) 135 100 40 1k 158 1 10 100 1k 10k Frequency (Hz) TA = -40, 25, 125°C VS= 1.8V Phase (ƒ) ZO (Ÿ GAIN 120 100k 180 125°C 25°C -40°C Phase (ƒ) 1M RL= 100kΩ CL= 20pF -23 100k C003 VOUT = 200mVPP VCM = Vs/2 Figure 40. Open Loop Gain and Phase, 1.8V, 100kΩ Load Figure 39. Voltage Noise vs Frequency 120 LPV802, -20dBm LPV802, -10dBm LPV802, 0dBm EMIRR (dB) Voltage (2µV/div) 100 80 60 40 20 0 Time (1 sec/div) 10 100 Frequency (MHz) C004 TA = 25 VS= 5V RL= 1MΩ CL= 20pF VCM = Vs/2 AV = +1 Figure 41. 0.1 to 10Hz Peak to Peak Noise 12 Submit Documentation Feedback TA = 25 VS= 3.3V RL= 1MΩ CL= 20pF 1000 C001 VCM = Vs/2 AV = +1 Figure 42. EMIRR Performance Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 7 Detailed Description 7.1 Overview The LPV80x is unity-gain stable and can operate on a single supply, making it highly versatile and easy to use. Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics curves. 7.3 Feature Description The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifer amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp VOUT is given by Equation 1: VOUT = AOL (IN+ – IN–) where • AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 100,000 Volts per microvolt). (1) 7.4 Device Functional Modes 7.4.1 Negative-Rail Sensing Input The input common-mode voltage range of the LPV80x extends from (V-) to (V+) – 0.9 V. In this range, low offset can be expected with a minimum of 80dB CMRR. Operation of the LPV80x beyond (V+) - 0.9V is possible, however, the offset voltage is not specified. Because of this, the LPV80x is protected from output "inversions" or "reversals" as long as the input common mode voltage range stays within the input pin Absolute Maximum Ratings range. 7.4.2 Rail to Rail Output Stage The LPV80x output voltage swings 3 mV from rails at 3.3 V supply, which provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. The LPV80x Maximum Output Voltage Swing graph defines the maximum swing possible under a particular output load. 7.4.3 Design Optimization for Nanopower Operation When designing for ultralow power, choose system feedback components carefully. To minimize quiecent current consumption, select large-value feedback resistors. Any large resistors will react with stray capacitance in the circuit and the input capacitance of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A feedback capacitor may be required to assure stability and limit overshoot or gain peaking. When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements. Use film or ceramic capacitors since large electolytics may have large static leakage currents in the nanoamps. Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 13 PRODUCT PREVIEW 7.2 Functional Block Diagram LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Device Functional Modes (continued) 7.4.4 Driving Capacitive Load The LPV80x is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth. However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp might start oscillating. In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 43. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. The recommended value for RISO is 30-50kΩ. - RISO VOUT VIN + CL PRODUCT PREVIEW Figure 43. Resistive Isolation Of Capacitive Load 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LPV80x is a ultra-low power operational amplifier that provides 8 kHz bandwidth with only 320nA typical quiescent current, and near precision drift specifications at a low cost. These rail-to-rail input and output amplifiers are specifically designed for battery-powered applications. The input common-mode voltage range extends to the negative supply rail and the output swings to within millivolts of the rails, maintaining a wide dynamic range. 8.2 Typical Application: Three Terminal CO Gas Sensor Amplifier R1 10 k PRODUCT PREVIEW C1 0.1µF Potentiostat (Bias Loop) CE RE CO Sensor R2 10 NŸ 2.5V U1 + VREF WE Transimpedance Amplifier (I to V conversion) ISENS RF Riso 49.9 k RL VREF + U2 VTIA C2 1µF Figure 44. Three Terminal Gas Sensor Amplifer Schematic 8.2.1 Design Requirements Figure 44 shows a simple micropower potentiostat circuit for use with three terminal unbiased CO sensors, though it is applicable to many other type three terminal gas sensors or electrochemical cells. The basic sensor has three electrodes; The Sense or Working Electrode (“WE”), Counter Electrode (“CE”) and Reference Electrode (“RE”). A current flows between the CE and WE proportional to the detected concentration. The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes must be maintained at the same potential by adjusting the bias on CE. Through the Potentiostat circuit formed by U1, the servo feedback action will maintain the RE pin at a potential set by VREF. R1 is to maintain stability due to the large capacitence of the sensor. C1 and R2 form the Potentiostat integrator and set the feedback time constant. U2 forms a transimpedance amplifer ("TIA") to convert the resulting sensor current into a proportional voltage. The transimpedance gain, and resulting snesitivity, is set by RF according to Equation 2 . VTIA = (-I * RF) + VREF (2) RL is a load resistor of which the value is normally specified by the sensor manufacturer (typically 10 ohms). The potential at WE is set by the applied VREF. Riso provides capacitive isolation and, combined with C2, form the output filter and ADC reservoir capacitor to drive the ADC. Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 15 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com Typical Application: Three Terminal CO Gas Sensor Amplifier (continued) 8.2.2 Detailed Design Procedure For this example, we will be using a CO sensor with a sensitivity of 69nA/ppm. The supply votlage and maximum ADC input voltage is 2.5V, and the maximum concentration is 300ppm. First the VREF voltage must be determined. This voltage is a compromise between maximum headroom and resolution, as well as allowance for "footroom" for the minimum swing on the CE terminal, since the CE terminal generally goes negative in relation to the RE potential as the concentration (sensor current) increases. Bench measuements found the difference between CE and RE to be 180mV at 300ppm for this particular sensor. To allow for negative CE swing "footroom" and voltage drop across the 10k resistor, 300mV was chosen for VREF. Therefore +300mV will be used as the minimum VZERO to add some headroom. VZERO = VREF = +300mV where • • VZERO is the zero concentration voltage VREF is the reference voltage (300mV) (3) Next we calculate the maximum sensor current at highest expected concentration: ISENSMAX = IPERPPM * ppmMAX = 69nA * 300ppm = 20.7uA PRODUCT PREVIEW where • • • ISENSMAX is the maximum expected sensor current IPERPPM is the manufacturer specified sensor current in Amps per ppm ppmMAX is the maximum required ppm reading (4) Now find the available output swing range above the reference voltage available for the measurement: VSWING = VOUTMAX – VZERO = 2.5V – 0.3V = 2.2V where • • VSWING is the expected change in output voltage VOUTMAX is the maximum amplifer output swing (usually near V+) (5) Now we calculate the transimpedance resistor (RF) value using the maximum swing and the maximum sensor current: RF = VSWING / ISENSMAX = 2.2V / 20.7µA = 106.28 kΩ (we will use 110 kΩ for a common value) 16 Submit Documentation Feedback (6) Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 Typical Application: Three Terminal CO Gas Sensor Amplifier (continued) 8.2.3 Application Curve 2.50 Vc Vw 2.25 Vtia 2.00 Vdif Measured Voltage (V) 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 15 30 45 60 75 90 105 120 135 150 Time (sec) C007 Figure 45. Monitored Voltages when exposed to 200ppm CO Figure 45 shows the resulting circuit voltages when the sensor was exposed to 200ppm step of carbon monoxide gas. VC is the monitored CE pin voltage and clearly shows the expected CE voltage dropping below the WE voltage, VW, as the concentration increases. VTIA is the output of the transimpedance amplifer U2. VDIFF is the calculated difference between VREF and VTIA, which will be used for the ppm calculation. 20 300 18 250 Concentration (ppm) Sensor Current (uA) 16 14 12 10 8 6 4 200 150 100 50 2 0 0 0 15 30 45 60 75 90 105 120 135 150 Time (sec) 0 15 30 45 Figure 46. Calculated Sensor Current 60 75 90 105 120 135 150 Time (sec) C002 C003 Figure 47. Calculated ppm Figure 46 shows the calculated sensor current using the formula in Equation 7 : ISENSOR = VDIFF / RF = 1.52V / 110 kΩ = 13.8uA (7) Equation 8 shows the resulting conversion of the sensor current into ppm. ppm = ISENSOR / IPERPPM = 13.8µA / 69nA = 200 (8) Total supply current for the amplifier section is less than 700 nA, minus sensor current. Note that the sensor current is sourced from the amplifier output, which in turn comes from the amplifier supply voltage. Therefore, any continuous sensor current must also be included in supply current budget calculations. Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 17 PRODUCT PREVIEW 0.00 LPV801, LPV802 SNOSCZ3 – AUGUST 2016 www.ti.com 8.3 Do's and Don'ts Do properly bypass the power supplies. Do add series resistance to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs. Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed the supplies. Limit the current to 1mA or less (1KΩ per volt). 9 Power Supply Recommendations The LPV80x is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C temperature range. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 6 V can permanently damage the device. PRODUCT PREVIEW For proper operation, the power supplies bust be properly decoupled. For decoupling the supply lines it is suggested that 100 nF capacitors be placed as close as possible to the operational amplifier power supply pins. For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor between V+ and ground, and one capacitor between V– and ground. Low bandwidth nanopower devices do not have good high frequency (> 1 kHz) AC PSRR rejection against highfrequency switching supplies and other 1 kHz and above noise sources, so extra supply filtering is recommended if kilohertz or above noise is expected on the power supply lines. 10 Layout 10.1 Layout Guidelines The V+ pin should be bypassed to ground with a low ESR capacitor. The optimum placement is closest to the V+ and ground pins. Care should be taken to minimize the loop area formed by the bypass capacitor connection between V+ and ground. The ground pin should be connected to the PCB ground plane at the pin of the device. The feedback components should be placed as close to the device as possible to minimize strays. 10.2 Layout Example Figure 48. SOT-23 Layout Example (Top View) 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated LPV801, LPV802 www.ti.com SNOSCZ3 – AUGUST 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm TI FilterPro Filter Design software, http://www.ti.com/tool/filterpro 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LPV801 Click here Click here Click here Click here Click here LPV802 Click here Click here Click here Click here Click here 11.4 Trademarks All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 19 PRODUCT PREVIEW 11.3 Related Links PACKAGE OPTION ADDENDUM www.ti.com 10-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LPV801DBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125 LPV801DBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 LPV802DGKR PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125 LPV802DGKT PREVIEW VSSOP DGK 8 250 TBD Call TI Call TI -40 to 125 PLPV801DBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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