Freescale Semiconductor Technical Data Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer The MC100ES6220 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6220 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. MC100ES6220 Rev 4, 04/2005 MC100ES6220 LOW VOLTAGE DUAL 1:10 DIFFERENTIAL ECL/PECL CLOCK FANOUT BUFFER Features • • • • • • • • • • • Two independent 1:10 differential clock fanout buffers 130 ps maximum device skew SiGe technology Supports DC to 1 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL compatible differential clock inputs Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics Supports industrial temperature range Pin and function compatible to the MC100EP220 52-lead Pb-free Package Available Functional Description TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 1336A-01 The MC100ES6220 is designed for low skew clock distribution systems and supports clock frequencies up to 1 GHz. The device consists of two independent clock fanout buffers. The CLKA and CLKB inputs can be driven by ECL or PECL compatible signals. The input signal of each clock buffer is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6220 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6220 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6220 supports positive (PECL) and negative (ECL) supplies. The MC100ES6220 is pin and function compatible to the MC100EP220. © Freescale Semiconductor, Inc., 2005. All rights reserved. QA1 QA1 VCC QB1 QB1 QB0 QA9 QB0 QA9 25 QB2 QA5 42 24 QB3 QA4 43 23 QB3 QA4 44 22 QB4 QA9 QA9 QA3 45 21 QB4 QA3 46 20 QB5 QB0 QB0 QA2 47 19 QB5 QA2 48 18 QB6 QA1 49 17 QB6 QA1 50 16 QB7 QA0 51 15 QB7 QA0 52 1 14 9 10 11 12 13 VCC 6 7 8 QB8 QB8 5 QB9 QB9 4 CLKB VEE 3 CLKB VCC QB9 QB9 2 CLKA VBB QB8 QB8 MC100ES6220 CLKA CLKB CLKB VEE QA8 41 QB1 QB1 VCC QA8 QB2 QA5 QA8 QA8 Fanout Buffer B QA7 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 CLKA CLKA VEE QA7 VCC VEE VCC QA6 QA6 QA0 QA0 VCC Fanout Buffer A VBB Figure 1. MC100ES6220 Logic Diagram Figure 2. 52-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin I/O Type Function CLKA, CLKA Input ECL/PECL Differential reference clock signal input for fanout buffer A CLKB, CLKB Input ECL/PECL Differential reference clock signal input for fanout buffer B QA[0-9], QA[0-9] Output ECL/PECL Differential clock outputs of fanout buffer A QB[0-9], QB[0-9] Output ECL/PECL Differential clock outputs of fanout buffer B VEE(1) Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL and PECL operation 1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). MC100ES6220 2 Advanced Clock Drivers Devices Freescale Semiconductor Table 2. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.6 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V ±20 mA VOUT IIN IOUT TS TFUNC DC Input Current ±50 mA –65 125 °C TA = –40 TJ = +110 °C DC Output Current Storage Temperature Functional Temperature Range Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. General Specifications Symbol Characteristics Min Typ Max VCC – 2(1) Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 4000 V CDM ESD Protection (Charged Device Model) 2000 V LU Latch-Up Immunity 200 mA CIN Input Capacitance θJA,θJC, θJB TJ Thermal Resistance (junction-to-ambient, junction-to-board, junction-to-case) Operating Junction Temperature(2) (continuous operation) MTBF = 9.1 years 4.0 pF See Table 8. Thermal Resistance °C/W 0 Condition V 110 Inputs °C 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MC100ES6220 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6220 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 4. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to +110°C) Symbol Characteristics Min Typ Max Unit Condition 0.1 1.3 V Differential operation 1.0 VCC – 0.3 V Differential operation ±150 µA VIN = VIL or VIN = VIH Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals) VPP VCMR IIN Differential Input Voltage(1) Differential Cross Point Input Voltage(2) Current(1) Clock Inputs (PECL single ended signals) VIH Input Voltage High VCC – 1.165 VCC – 0.880 V VIL Input Voltage Low VCC – 1.810 VCC – 1.475 V ±150 µA VIN = VIL or VIN = VIH IIN Input Current(3) PECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) VOH Output High Voltage VCC – 1.1 VCC – 1.005 VCC – 0.7 V IOH = –30 mA(4) VOL Output Low Voltage VCC – 1.9 VCC – 1.705 VCC – 1.4 V IOL = –5 mA(4) 80 130 mA VCC – 1.20 V Supply current and VBB IEE(5) VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage VCC – 1.42 VEE pins IBB = 0.3 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 Ω to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷Rload + IEE. Table 5. ECL DC Characteristics (VEE = –2.5 V ± 5% or VEE = –3.3 V ± 5%, VCC = GND, TJ = 0°C to +110°C) Symbol Characteristics Min Typ Max Unit Condition 1.3 V Differential operation Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN Differential Input Voltage(1) 0.1 (2) Differential Cross Point Voltage VEE + 1.0 Input Current(1) –0.3 V Differential operation ±150 µA VIN = VIL or VIN = VIH V Clock Inputs (ECL single ended signals) VIH Input Voltage High –1.165 –0.880 VIL Input Voltage Low –1.810 –1.475 V IIN Input Current(3) ±150 µA VIN = VIL or VIN = VIH ECL Clock Outputs (QA0–A9, QA0–A9, QB0–B9, QB0–B9) VOH Output High Voltage –1.1 –1.005 –0.7 V IOH = –30 mA(4) VOL Output Low Voltage –1.9 –1.705 –1.4 V IOL = –5 mA(4) 80 130 mA –1.20 V Supply Current and VBB IEE(5) VBB Maximum Quiescent Supply Current without Output Termination Current Output Reference Voltage –1.42 VEE pins IBB = 0.3 mA 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Input have internal pullup/pulldown resistors which affect the input current. 4. Termination 50 Ω to VTT. 5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷ Rload + IEE. MC100ES6220 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 6. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or (PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1) Symbol Characteristics Min Typ Max Unit Condition 0.3 1.3 V 1.1 VEE + 1.1 VCC – 0.3 –0.3 V V 0 1000 MHz Differential Propagation Delay CLKx to Qx0-9 285 550 ps Differential Differential Output Voltage (peak-to-peak) 400 Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals) VPP VCMR fCLK Differential Input Voltage(2) (peak-to-peak) Differential Input Crosspoint Voltage(3) PECL ECL Input Frequency PECL/ECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9) tPD VO(P-P) tsk(O) Output-to-Output Skew tsk(PP) Output-to-Output Skew (part-to-part) tJIT(CC) Output Cycle-to-Cycle Jitter 600 60 RMS (1σ) (4) tSK(P) Output Pulse Skew DCO Output Duty Cycle tr, tf Output Rise/Fall Time fREF < 0.1 GHz fREF < 1.0 GHz 49.65 46.5 50 50 50 mV 130 ps Differential 200 ps Differential 1 ps 35 ps 50.35 53.5 % % DCREF = 50% DCREF = 50% 350 ps 20% to 80% 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH – tpHL |. Differential Pulse Generator Z = 50 Ω Z = 50 Ω Z = 50 Ω RT = 50 Ω DUT MC100ES6220 RT = 50 Ω VTT VTT Figure 3. MC100ES6220 AC Test Reference CLKN VPP = 0.8 V VCMR = VCC – 1.3 V CLKN QX QX tPD (CLKN to QX) Figure 4. MC100ES6220 AC Reference Measurement Waveform MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 5 APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6220 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6220, the MC100ES6220 is specified, characterized and tested for the junction temperature range of TJ = 0°C to +110°C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja ⋅ Ptot Assuming a thermal resistance (junction to ambient) of 17°C/W (2s2p board, 200 ft/min airflow, see Table 8) and a typical power consumption of 1049 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6220 is approximately TA + 18°C, and the minimum ambient temperature in this example case calculates to –18°C (the maximum ambient temperature is 92°C. See Table 7). Exceeding the minimum junction temperature specification of the MC100ES6220 does not have a significant impact on the device functionality. However, the continuous use the MC100ES6220 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the application note AN1545 for a power consumption calculation guideline. Maintaining Lowest Device Skew The MC100ES6220 guarantees low output-to-output bank skew of 100 ps and a part-to-part skew of max. 200 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6220 is a mixed analog/digital product. The differential architecture of the MC100ES6220 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. VCC VCC 33...100 nF 0.1 nF MC100ES6220 Figure 5. VCC Power Supply Bypass Table 7. Ambient Temperature Ranges (Ptot = 1049 mW) Rthja (2s2p board) TA, min(1) TA, max Natural convection 20°C/W –21°C 89°C 100 ft/min 18°C/W –19°C 91°C 200 ft/min 17°C/W –18°C 92°C 400 ft/min 16°C/W –17°C 93°C 800 ft/min 15°C/W –16°C 94°C 1. The MC100ES6220 device function is guaranteed from TA = –40°C to TJ = 110°C. MC100ES6220 6 Advanced Clock Drivers Devices Freescale Semiconductor APPLICATIONS INFORMATION all units mm package standoff 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. all units mm 0.2 1.0 1.0 0.2 4.8 Using the Thermally Enhanced Package of the MC100ES6220 The MC100ES6220 uses a thermally enhanced exposed pad (EP) 52 lead LQFP package. The package is molded so that the lead frame is exposed at the surface of the package bottom side. The exposed metal pad will provide the low thermal impedance that supports the power consumption of the MC100ES6220 high-speed bipolar integrated circuit and eases the power management task for the system design. A thermal land pattern on the printed circuit board and thermal vias are recommended in order to take advantage of the enhanced thermal capabilities of the MC100ES6220. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal path. In multilayer board designs, thermal vias thermally connect the exposed pad to internal copper planes. Number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. A nine thermal via array, arranged in a 3 x 3 array and using a 1.2 mm pitch in the center of the thermal land is a requirement for MC100ES6220 applications on multi-layer boards. The recommended thermal land design comprises a 3 x 3 thermal via array as shown in Figure 6, providing an efficient heat removal path. 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 7. Recommended Solder Mask Openings For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided: 4.8 Table 8. Thermal Resistance(1) 4.8 Thermal via array (3x3), 1.2 mm pitch, 0.3 mm diameter Exposed pad land pattern Figure 6. Recommended thermal land pattern The via diameter is should be approx. 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via resulting in voids during the solder process must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for exposed pad package is equivalent to standard surface mount packages. Figure 7 shows a recommend solder mask opening with respect to the recommended 3 x 3 thermal via array. Because a large solder mask opening may result in a poor release, the opening should be subdivided as shown in Figure 7. For the nominal ConvectionL FPM RTHJA(2) °C/W RTHJA(3) °C/W Natural 20 48 100 18 47 200 17 46 400 16 43 800 15 41 RTHJC °C/W RTHJB(4) °C/W 4(5) 29(6) 16 1. Applicable for a 3 x 3 thermal via array. 2. Junction to ambient, four conductor layer test board (2S2P), per JES51-7 and JESD 51-5. 3. Junction to ambient, single layer test board, per JESD51-3. 4. Junction to board, four conductor layer test board (2S2P) per JESD 51-8. 5. Junction to exposed pad. 6. Junction to top of package. It is recommended that users employ thermal modeling analysis to assist in applying the general recommendations to their particular application. The exposed pad of the MC100ES6220 package does not have an electrical low impedance path to the substrate of the integrated circuit and its terminals. The thermal land should be connected to GND through connection of internal board layers. MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 7 PACKAGE DIMENSIONS 4X 4X 13 TIPS 0.2 H A-B D 0.2 C A-B D D PIN 1 INDEX (0.2) 7 40 52 1 39 A 10 6 B 0.20 R 0.08 0.75 0.45 (1) 7˚ 0˚ 4 5 6 0.25 GAUGE PLANE 0.20 0.05 12 13 0˚ MIN 0.20 R 0.08 1.5 1.3 0.05 VIEW AA 6 4 27 X 14 26 5 X=A, B OR D CL 6 B 6 4 10 6 48X B 12 4 0.65 VIEW Y H 4X 1.7 MAX (12˚) VIEW AA 8 BASE METAL (0.3) 52X 0.1 C 8 J C SEATING PLANE 0.40 52X 0.22 5 M 0.08 C A-B D 4X (12˚) J PLATING 0.20 0.09 0.16 0.07 0.35 0.20 8 8 SECTION B-B NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSION TO BE DETERMINED AT SEATING PLANE C. 5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. THIS DIMENSION IS MAXIMUM PLSTIC BODY SIZE DIMENSION INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 4.78 4.58 4.78 4.58 EXPOSED PAD VIEW Y VIEW J-J CASE 1336A-01 ISSUE O 52-LEAD LQFP PACKAGE MC100ES6220 8 Advanced Clock Drivers Devices Freescale Semiconductor NOTES MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 9 NOTES MC100ES6220 10 Advanced Clock Drivers Devices Freescale Semiconductor NOTES MC100ES6220 Advanced Clock Drivers Devices Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 [email protected] MC100ES6220 Rev. 4 04/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. All rights reserved.