TI LM5041A Lm5041a cascaded pwm controller Datasheet

LM5041A
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SNVS350B – MARCH 2005 – REVISED MARCH 2013
LM5041A Cascaded PWM Controller
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FEATURES
DESCRIPTION
•
•
The LM5041A PWM controller contains all of the
features necessary to implement either current-fed or
voltage-fed push-pull or bridge power converters.
These “Cascaded” topologies are well suited for
multiple output and higher power applications. The
LM5041A’s four control outputs include: the buck
stage controls (HD and LD) and the push-pull control
outputs (PUSH and PULL). Push-pull outputs are
driven at 50% nominal duty cycle at one half of the
switching frequency of the buck stage and can be
configured for either an overlap time (for current-fed
applications) or a both-off time (for voltage-fed
applications). Push-pull stage MOSFETs can be
driven directly from the internal gate drivers while the
buck stage requires an external driver such as the
LM5102. The LM5041A includes a high-voltage startup regulator that operates over a wide input range of
15V to 100V. The PWM controller is designed for
high-speed capability including an oscillator
frequency range up to 1 MHz and total propagation
delays of less than 100ns. Additional features include:
line Under-Voltage Lockout (UVLO), soft-start, an
error amplifier, precision voltage reference, and
thermal shutdown.
1
•
•
•
•
•
•
•
•
•
•
Internal Start-up Bias Regulator
Programmable Line Under-Voltage Lockout
(UVLO) with Adjustable Hysteresis
Current Mode Control
Internal Error Amplifier with Reference
Cycle-by-cycle Over-Current Protection
Leading Edge Blanking
Programmable Push-Pull Overlap or Dead
Time
Internal 1.5A Push-Pull Gate Drivers
Programmable Soft-Start
Programmable Oscillator with Sync Capability
Precision Reference
Thermal Shutdown
APPLICATIONS
•
•
•
•
Telecommunication Power Converters
Industrial Power Converters
Multi-Output Power Converters
+42V Automotive Systems
The two differences between the LM5041 and the
LM5041A are: No second level current limit in the 'A'
version No softstart (SS) shutdown comparator in the
'A' version.
PACKAGES
•
•
TSSOP-16
WSON-16 (5 mm × 5 mm) Thermally Enhanced
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM5041A
SNVS350B – MARCH 2005 – REVISED MARCH 2013
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Typical Application Circuit
VOUT
33V - 76V
VDD
HB
VCC
VIN
HD
HI
HO
HS
LD
LM5041A
LI
RT
LM5102
2
VSS
LO
RT1 RT2
PUSH
FEED
BACK
PULL
FB
Figure 1. Simplified Cascaded Push-Pull Power Converter
Connection Diagram
1
2
3
4
5
6
7
8
VIN
UVLO
FB
RT
COMP
15
14
TIME
13
REF
SS
HD
CS
LD
AGND
VCC
PGND
PUSH
16
12
11
10
9
PULL
Figure 2. 16-Lead TSSOP or WSON
See PW or NHQ0016A Package
2
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PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
APPLICATION INFORMATION
1
VIN
Source Input Voltage
Input to start-up regulator. Input range 15V to 100V.
2
FB
Feedback Signal
Inverting input for the internal error amplifier. The noninverting input is connected to a 0.75V reference.
3
COMP
Output of the Internal Error Amplifier
There is an internal 5kΩ resistor pull-up on this pin. The
error amplifier provides an active sink.
4
REF
Precision 5 volt reference output
Maximum output current: 10mA. Locally decouple with a
0.1µF capacitor. Reference stays low until the line UV and
the VCC UV are satisfied.
5
HD
Main Buck PWM control output
Buck switch PWM control output. The maximum duty cycle
clamp for this output corresponds to an off time of typically
240ns per cycle. The LM5101 or LM5102 Buck stage gate
driver can be used to level shift and drive the Buck switch.
6
LD
Sync Switch control output
Sync Switch control output. Inversion of HD output. The
LM5101 or LM5102 lower drive can be used to drive the
synchronous rectifier switch.
7
VCC
Output from the internal high voltage start-up
regulator. Regulated to 9 volts.
If an auxiliary winding raises the voltage on this pin above
the regulation setpoint, the internal start-up regulator will
shutdown, reducing the IC power dissipation.
8
PUSH
Output of the push-pull drivers
Output of the push-pull gate driver. Output capability of
1.5A peak .
9
PULL
Output of the push-pull drivers
Output of the push-pull gate driver. Output capability of
1.5A peak.
10
PGND
Power ground
Connect directly to analog ground.
11
AGND
Analog ground
Connect directly to power ground.
12
CS
Current sense input
Current sense input to the PWM comparator (CM control).
There is a 50ns leading edge blanking on this pin. Using
separate dedicated comparator, if CS exceeds 0.5V the
outputs will go into cycle by cycle current limit.
13
SS
Soft-start control
An external capacitor and an internal 10uA current source,
set the soft-start ramp.
14
TIME
Push-Pull overlap and dead time control
An external resistor (RSET) sets the overlap time or dead
time for the push-pull outputs. A resistor connected
between TIME and GND produces overlap. A resistor
connected between TIME and REF produces dead time.
15
RT / SYNC
Oscillator timing resistor pin and sync
An external resistor sets the oscillator frequency. This pin
will also accept an external oscillator.
Line Under-Voltage Shutdown
An external divider from the power converter source sets
the shutdown levels. Threshold of operation equals 2.5V.
Hysteresis is set by a switched internal current source
(20µA).
Die substrate
The exposed die attach pad on the WSON package should
be connected to a PCB thermal pad at ground potential.
For additional information on using the No Pull Back
WSON package, please refer to LLP Application Note AN1187 (SNOA401).
16
WSON
DAP
UVLO
SUB
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Block Diagram
9V SERIES
REGULATOR
VIN
VCC
5V
REFERENCE
VCC
ENABLE
VREF
UVLO
UVLO
+
-
2.5V
LOGI
C
UVLO
HYSTERESIS
(20 PA)
45 PA
CLK
HD
5V
SLOPE COMP
RAMP
GENERATOR
COMP
0.75V
5k
+
FB
-
S
PWM
100k
Q
LD
+
R
1.4V
50k
Q
LOGIC
SS
PGND
CS
0.5V
2k
+
-
CLK + LEB
AGND
10 PA
SS
SS
TIME
VCC
DRIVE
R
OSC
CLK
RT / SYNC
OSCILLATOR
DIVIDE BY 2
OVERLAP
OR
DEAD TIME
CONTROL
PUSH
VCC
DRIVE
R
PULL
Figure 3. Simplified Block Diagram
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VIN to GND
100V
VCC to GND
16V
All Other Inputs to GND
-0.3 to 7V
Junction Temperature
150°C
Storage Temperature Range
-65°C to +150°C
ESD Rating
2 kV
Lead Temperature (3)
(1)
Wave
4 seconds
260°C
Infrared
10 seconds
240°C
Vapor Phase
75 seconds
219°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
For detailed information on soldering plastic TSSOP and WSON packages, visit www.ti.com/packaging.
(2)
(3)
Operating Ratings (1)
VIN
15 to 90V
Junction Temperature
(1)
-40°C to +125°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated (1)
Symbol
Parameter
Conditions
Min
Typ
Max
9.3
Units
Startup Regulator
VCC Reg
I-VIN
VCC Regulation
open circuit
8.7
9
VCC Current Limit
See (2)
15
25
V
Startup Regulator
Leakage (external Vcc
Supply)
VIN = 100V
145
500
µA
Shutdown Current (Iin)
UVLO = 0V, VCC = open
350
450
µA
mA
VCC Supply
VCC Under-voltage
Lockout Voltage (positive
going Vcc)
VCC Under-voltage
Hysteresis
Supply Current (ICC)
VCC Reg 400mV
VCC Reg - 275mV
1.7
2.1
2.6
V
3
4
mA
CL = 0
V
Error Amplifier
GBW
(1)
(2)
Gain Bandwidth
3
MHz
DC Gain
80
dB
Input Voltage
VFB = COMP
COMP Sink Capability
VFB = 1.5V, COMP= 1V
0.735
0.75
4
8
0.765
V
mA
All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Device thermal limitations may limit usable range.
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5
5.15
V
25
50
mV
Reference Supply
VREF
Ref Voltage
IREF = 0 mA
Ref Voltage Regulation
IREF = 0 to 10mA
4.85
Ref Current Limit
15
20
mA
40
ns
Current Limit
ILIM Delay to Output
CS Step from 0 to 0.6V
Time to Onset of OUT
Transition (90%), CL = 0
Cycle by Cycle Threshold
Voltage
0.45
Leading Edge Blanking
Time
0.5
0.55
V
50
ns
mA
CS Sink Current (clocked) CS = 0.3V
2
5
Soft-start Current Source
7
10
13
µA
Soft-start to COMP Offset
0.35
0.55
0.75
V
180
175
200
220
225
kHz
515
600
685
kHz
3
3.5
V
Soft-Start
Oscillator
Frequency1
(RT = 26.7KΩ)
TJ = 25°C
Frequency2
(RT = 7.87KΩ)
Sync threshold
PWM Comparator
Delay to Output
COMP set to 2V CS stepped
0 to 0.4V, Time to onset of
OUT transition low
Max Duty Cycle
TS = Oscillator Period
Min Duty Cycle
COMP = 0V
25
ns
(Ts-240ns)/Ts)
COMP to PWM
Comparator Gain
%
0
%
0.32
COMP Open Circuit
Voltage
FB = 0V
4.1
4.8
5.5
V
COMP Short Circuit
Current
FB = 0V, COMP = 0V
0.6
1
1.4
mA
Slope Compensation
Slope Comp Amplitude
Delta increase at PWM
Comparator to CS
110
mV
UVLO Shutdown
6
Under-voltage Shutdown
2.44
2.5
2.56
V
Under-voltage Shutdown
Hysteresis Current
Source
16
20
24
µA
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Buck Stage Outputs
Output High level
5 (VREF)
V
Output High Saturation
IOUT = 10mA, REF = VOUT
0.5
1
Output Low Saturation
IOUT = −10mA
0.5
1
V
Rise Time
CL = 100pF
10
ns
Fall Time
CL = 100pF
10
ns
V
Push-Pull Outputs
Overlap Time
RSET = 20kΩ Connected to
GND, 50% to 50%
Transitions
60
90
120
ns
Dead Time
RSET = 20kΩ Connected to
REF, 50% to 50%
Transitions
65
95
125
ns
Output High Saturation
IOUT = 50mA, VCC - VOUT
0.25
0.5
V
Output Low Saturation
IOUT = 100mA
0.5
1
V
Rise Time
CL = 1nF
20
ns
Fall Time
CL = 1nF
20
ns
Thermal Shutdown Temp.
165
°C
Thermal Shutdown
Hysteresis
25
°C
TSSOP Package
125
°C/W
WSON Package
32
°C/W
Thermal Shutdown
TSD
Thermal Resistance
θJA
Junction to Ambient
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Typical Performance Characteristics
VCC and VIN vs VIN
VCC vs ICC
10
20
VIN
8
VIN = 15V
6
VCC (V)
VCC AND VIN (V)
15
VCC
10
4
5
2
0
0
5
0
15
10
20
0
5
10
15
20
25
ICC (mA)
VIN (V)
Figure 4.
Figure 5.
SS Pin Current vs Temp
Frequency vs RT
13
1000
FREQUENCY (kHz)
SS CURRENT (PA)
12
11
10
9
8
100
7
-25
25
75
125
10000
1000
TEMPERATURE ( C)
Figure 6.
Figure 7.
Dead Time vs RSET
500
500
400
400
DEAD TIME (ns)
OVERLAP TIME (ns)
Overlap Time vs RSET
300
200
100
300
200
100
0
0
10
30
50
70
90
110
10
30
50
70
90
110
RSET (k:)
RSET (k:)
Figure 8.
8
100000
RT (:)
o
Figure 9.
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Typical Performance Characteristics (continued)
Dead Time vs Temp
120
130
110
120
DEAD TIME (ns)
OVERLAP TIME (ns)
Overlap Time vs Temp
100
RSET = 20k:
90
80
70
110
RSET = 20k:
100
90
80
70
60
-25
25
75
-25
125
o
25
75
125
o
TEMPERATURE ( C)
TEMPERATURE ( C)
Figure 10.
Figure 11.
Error Amplifier Gain Phase
Figure 12.
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DETAILED OPERATING DESCRIPTION
The LM5041A PWM controller contains all of the features necessary to implement either current-fed or voltagefed push-pull or bridge power converters. These “Cascaded” topologies are well suited for multiple output and
higher power applications. The LM5041A’s four control outputs include: the buck stage controls (HD and LD) and
the push-pull control outputs (PUSH and PULL). Push-pull outputs are driven at 50% nominal duty cycle at one
half of the switching frequency of the buck stage and can be configured for either an overlap time (for current-fed
applications) or a both-off time (for voltage-fed applications). Push-pull stage MOSFETs can be driven directly
from the internal gate drivers while the buck stage requires an external driver such as the LM5102. The
LM5041A includes a high-voltage start-up regulator that operates over a wide input range of 15V to 100V. The
PWM controller is designed for high-speed capability including an oscillator frequency range up to 1 MHz and
total propagation delays of less than 100ns. Additional features include: line Under-Voltage Lockout (UVLO), softstart, an error amplifier, precision voltage reference, and thermal shutdown.
High Voltage Start-Up Regulator
The LM5041A contains an internal high-voltage start-up regulator, thus the input pin (Vin) can be connected
directly to the line voltage. The regulator output is internally current limited to 15mA. When power is applied, the
regulator is enabled and sources current into an external capacitor connected to the Vcc pin. The recommended
capacitance range for the Vcc regulator is 0.1uF to 100uF. When the voltage on the Vcc pin reaches the
regulation point of 9V and the internal voltage reference (REF) reaches its regulation point of 5V, the controller
outputs are enabled. The Buck stage outputs will remain enabled until Vcc falls below 7V or the line UnderVoltage Lockout detector indicates that Vin is out of range. The push-pull outputs continue switching until the
REF pin voltage falls below approximately 3V. In typical applications, an auxiliary transformer winding is
connected through a diode to the Vcc pin. This winding must raise the Vcc voltage above 9.3V to shut off the
internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the
controller's power dissipation. The recommended capacitance range for the Vref regulator output is 0.1uF to
10uF.
The external VCC capacitor must be sized such that the capacitor maintains a VCC voltage greater than 7V during
the initial start-up. During a fault mode when the converter auxiliary winding is inactive, external current draw on
the VCC line should be limited so the power dissipated in the start-up regulator does not exceed the maximum
power dissipation of the controller.
An external start-up or other bias rail can be used instead of the internal start-up regulator by connecting the VCC
and the VIN pins together and feeding the external bias voltage into the two pins.
Line Under-Voltage Detector
The LM5041A contains a line Under-Voltage Lockout (UVLO) circuit. An external set-point resistor divider from
VIN to ground sets the operational range of the converter. The divider must be designed such that the voltage at
the UVLO pin will be greater than 2.5V when VIN is in the desired operating range. If the Under-Voltage threshold
is not met, all functions of the controller are disabled and the controller will enter a low-power state with input
current <300µA. ULVO hysteresis is accomplished with an internal 20µA current source that is switched on or off
into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is
activated to instantly raise the voltage at the UVLO pin. When the UVLO pin falls below the 2.5V threshold, the
current source is turned off causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to
implement a remote enable / disable function. By shorting the UVLO pin to ground, the converter can be
disabled.
Buck Stage Control Outputs
The LM5041A Buck switch maximum duty cycle clamp ensures that there will be sufficient off time each cycle to
recharge the bootstrap capacitor used in the high side gate driver. The Buck switch remains off, and the sync
switch remains on, for at least 250ns per switching cycle. The Buck stage control outputs (LD and HD) are
CMOS buffers with logic levels of 0 to 5V.
During any fault state or Under-Voltage off state, the buck stage control outputs will default to HD low and LD
high.
10
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Push-Pull Outputs
The push pull outputs operate continuously at a nominal 50% duty cycle. A distinguishing feature of the
LM5041A is the ability to accurately configure either dead time (both-off) or overlap time (both-on) on the
complementary push-pull outputs. The overlap/dead time magnitude is controlled by a resistor connected to the
TIME pin on the controller. The TIME pin holds one end of the resistor at 2.5V and the other end of the resistor
should be connected to either REF for dead time control setting or to GND for overlap control. The polarity of the
current in the TIME is detected by the LM5041A The magnitude of the overlap/dead time can be calculated as
follows:
Overlap Time (ns) = (3.66 x RSET) + 7
Overlap Time in ns, RSET connected to GND, RSET in kΩ
Dead Time (ns) = (3.69 x RSET) + 21
Dead Time in ns, RSET connected to REF, RSET in kΩ
Recommended RSET programming range: 10kΩ to 100kΩ
Current-fed designs require a period of overlap to insure there is a continuous path for the buck inductor current.
Voltage-fed designs require a period of dead time to insure there is no time when the push-pull transformer acts
as a shorted turn to the low impedance sourcing node. The push-pull outputs alternate continuously under all
conditions provided REF the voltage is greater than 3V.
K1 * RSET
PUSH
DEADTIME
WAVEFORMS
K1 * RSET
PULL
K2 * RSET
PUSH
OVERLAP
WAVEFORMS
K2 * RSET
PULL
Figure 13.
PWM Comparator
The PWM comparator compares the slope compensated current ramp signal to the loop error voltage from the
internal error amplifier (COMP pin). This comparator is optimized for speed in order to achieve minimum
controllable duty cycles. The comparator polarity is such that 0V on the COMP pin will produce zero duty cycle in
the buck stage.
Error Amplifier
An internal high gain wide-bandwidth error amplifier is provided within the LM5041A. The amplifier’s non-inverting
input is tied to a 0.75V reference. The inverting input is connected to the FB pin. In non-isolated applications the
power converter output is connected to the FB pin via the voltage setting resistors. Loop compensation
components are connected between the COMP and FB pins. For most isolated applications the error amplifier
function is implemented on the secondary side of the converter and the internal error amp is not used. The
internal error amplifier is configured as an open drain output and can be disabled by connecting the FB pin to
ground. An internal 5kΩ pull-up resistor between the 5V reference and COMP can be used as the pull-up for an
opto-coupler in isolated applications.
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Current Limit/Current Sense
The LM5041A provides cycle-by-cycle over-current protection. If the voltage at the CS comparator (CS pin
voltage plus slope comp voltage) exceeds 0.5V the present buck stage duty cycle is terminated (cycle by cycle
current limit). A small RC filter located near the controller is recommended to filter current sense signals at the
CS pin. An internal MOSFET discharges the external CS pin for an additional 50ns at the beginning of each
cycle to reduce the leading edge spike that occurs when the buck stage MOSFET is turned on.
The LM5041A current sense and PWM comparators are very fast, and may respond to short duration noise
pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated
with the CS filter must be placed close to the device and connected directly to the pins of the controller (CS and
GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the
sense resistor, which should also be located close to the IC. A resistor may be used for current sensing instead
of a transformer, located in the push-pull transistor sources, but a low inductance type of resistor is required.
When designing with a sense resistor, all of the noise sensitive low power grounds should be connected together
around the IC and a single connection should be made to the high current power ground (sense resistor ground
point).
Oscillator and Sync Capability
The LM5041A oscillator is set by a single external resistor connected between the RT pin and GND. To set a
desired oscillator frequency (F), the necessary RT resistor can be calculated from:
RT =
(1/F) - 235 x 10-9
:
182 x 10-12
(1)
The buck stage will switch at the oscillator frequency and each push-pull output will switch at half the oscillator
frequency in a push-pull configuration. The LM5041A can also be synchronized to an external clock. The external
clock must have a higher frequency than the free running frequency set by the RT resistor. The clock signal
should be capacitively coupled into the RT pin with a 100pF capacitor. A peak voltage level greater than 3V is
required for detection of the sync pulse. The sync pulse width should be set in the 15 to 150ns range by the
external components. The RT resistor is always required, whether the oscillator is free running or externally
synchronized. The voltage at the RT pin is internally regulated to 2V. The RT resistor should be located very
close to the device and connected directly to the pins of the IC (RT and GND).
Slope Compensation
The PWM comparator compares the current sense signal to the voltage at the COMP pin. The output stage of
the internal error amplifier generally drives the COMP pin. At duty cycles greater than 50 percent, current mode
control circuits are subject to sub-harmonic oscillation. By adding an additional fixed ramp signal (slope
compensation) to the current sense ramp, oscillations can be avoided. The LM5041A integrates this slope
compensation by buffering the internal oscillator ramp and summing a current ramp generated by the oscillator
internally with the current sense signal. Additional slope compensation may be provided by increasing the source
impedance of the current sense signal.
Soft-start and Shutdown
The soft-start feature allows the power converter to gradually reach the initial steady state operating point,
thereby reducing start-up stresses and surges. At power on, a 10uA current is sourced out of the soft-start pin
(SS) to charge an external capacitor. The capacitor voltage will ramp up slowly and will limit the maximum duty
cycle of the buck stage. In the event of a fault as indicated by VCC Under-voltage, line Under-voltage the output
drivers are disabled and the soft-start capacitor is discharged to 0.7V. When the fault condition is no longer
present, a soft-start sequence will begin again and buck stage duty cycle will gradually increase as the soft-start
capacitor is charged.
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 165 degrees Celsius, the controller is forced into a
low-power standby state, disabling the output drivers and the bias regulator. This feature is provided to prevent
catastrophic failures from accidental device overheating.
12
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5041A
LM5041A
www.ti.com
SNVS350B – MARCH 2005 – REVISED MARCH 2013
Typical Application
VOUT
T1
L1
33V - 76V
VDD
VDD
HB
VCC
VIN
HB
HD
HI
HO
HO
+
HI
T1
HS
HS
LD
LI
+
LI
LO
LM5102
LM5041A
VSS
LO
LM5100
RT2
RT1
PUSH
PULL
COMP
FEED
BACK
Figure 14. Simplified Cascaded Half-Bridge
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5041A
13
LM5041A
SNVS350B – MARCH 2005 – REVISED MARCH 2013
www.ti.com
Application Circuit: Input 35-80V, Output 2.5V, 50A
14
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5041A
LM5041A
www.ti.com
SNVS350B – MARCH 2005 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM5041A
15
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5041AMTC/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5041A
MTC
LM5041AMTCX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5041A
MTC
LM5041ASD/NOPB
ACTIVE
WSON
NHQ
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5041ASD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5041AMTCX/NOPB
TSSOP
PW
16
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
LM5041ASD/NOPB
WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5041AMTCX/NOPB
LM5041ASD/NOPB
TSSOP
PW
16
2500
367.0
367.0
35.0
WSON
NHQ
16
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
www.ti.com
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