TI CC2480A1RTCR Z-accel 2.4 ghz zigbee processor Datasheet

CC2480
Z-Accel 2.4 GHz ZigBee® Processor
Accelerate your ZigBee Development
Applications
• ZigBee™ systems
• Home/Building automation
• Industrial control and monitoring
• Low power wireless sensor networks
• Set-top boxes and remote controls
• Automated Meter Reading
Description
The CC2480 (formerly known as CCZACC06)
is a cost-effective, low power, Z-Accel ZigBee
Processor
that
provides
full
ZigBee
functionality with a minimal development effort.
CC2480 supports TI’s SimpleAPI. SimpleAPI
has only 10 API calls to learn, which drastically
simplifies the development of ZigBee
applications.
Z-Accel is a solution where TI’s ZigBee stack,
Z-Stack, runs on a ZigBee Processor and the
application runs on an external microcontroller.
The CC2480 handles all the timing critical and
processing intensive ZigBee protocol tasks,
and leaves the resources of the application
microcontroller free to handle the application.
Z-Accel makes it easy to add ZigBee to new or
existing products at the same time as it
provides great flexibility in choice of
microcontroller.
CC2480 interfaces any microcontroller through
an SPI or UART interface. There is no need to
learn a new microcontroller or new tools.
CC2480 can for example be combined with an
MSP430.
Key Features
• Simple integration of ZigBee into any
design
• Running the mature and stable ZigBee
2006 compliant TI Z-Stack
• SPI
or
UART
interface
to
any
microcontroller running the application
• Simple API and full ZigBee API supported
• Can implement any type of ZigBee device:
Coordinator, Router or End Device
• Automatically enters low power mode (<0.5
uA) in idle periods when configured as End
Device
• Radio
o Fully integrated and robust IEEE
802.15.4-compliant 2.4 GHz DSSS
RF transceiver
o Excellent receiver sensitivity and
best in class robustness to
interferers
• Power Supply
o Wide supply voltage range (2.0V –
3.6V)
o Low current consumption (RX: 27
mA, TX: 27 mA) and fast transition
times.
• External System
o Very few external components
o RoHS compliant 7x7mm QLP48
package
• Peripherals and Supporting Functions
o Port expander with 4 general I/O
pins, two with increased sink/source
capability
o Battery monitor and temperature
sensor
o 7-12 bits ADC with two channels
o Robust power-on-reset and brownout-reset circuitry
• Tools and Development
o Packet sniffer PC software
o Reference designs
CC2480 Data Sheet SWRS074A
Page 1 of 43
CC2480
Table Of Contents
APPLICATIONS .............................................................................................................................................. 1
DESCRIPTION ................................................................................................................................................ 1
KEY FEATURES ............................................................................................................................................. 1
TABLE OF CONTENTS ................................................................................................................................. 2
1
ABBREVIATIONS................................................................................................................................ 4
2
REFERENCES ...................................................................................................................................... 5
3
ABSOLUTE MAXIMUM RATINGS .................................................................................................. 6
4
OPERATING CONDITIONS............................................................................................................... 6
5
ELECTRICAL SPECIFICATIONS .................................................................................................... 7
5.1 GENERAL CHARACTERISTICS ................................................................................................................ 8
5.2 RF RECEIVE SECTION ........................................................................................................................... 9
5.3 RF TRANSMIT SECTION ......................................................................................................................... 9
5.4 32 MHZ CRYSTAL OSCILLATOR .......................................................................................................... 10
5.5 32.768 KHZ CRYSTAL OSCILLATOR .................................................................................................... 10
5.6 32 KHZ RC OSCILLATOR..................................................................................................................... 11
5.7 16 MHZ RC OSCILLATOR ................................................................................................................... 11
5.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ................................................................................... 12
5.9 ANALOG TEMPERATURE SENSOR ........................................................................................................ 12
5.10 ADC ................................................................................................................................................... 12
5.11 CONTROL AC CHARACTERISTICS........................................................................................................ 14
5.12 SPI AC CHARACTERISTICS ................................................................................................................. 15
5.13 PORT OUTPUTS AC CHARACTERISTICS ............................................................................................... 15
5.14 DC CHARACTERISTICS ........................................................................................................................ 15
6
PIN AND I/O PORT CONFIGURATION ........................................................................................ 17
7
CIRCUIT DESCRIPTION ................................................................................................................. 19
8
APPLICATION CIRCUIT ................................................................................................................. 20
8.1 INPUT / OUTPUT MATCHING ................................................................................................................. 20
8.2 BIAS RESISTORS .................................................................................................................................. 20
8.3 CRYSTAL ............................................................................................................................................. 20
8.4 VOLTAGE REGULATORS ...................................................................................................................... 20
8.5 POWER SUPPLY DECOUPLING AND FILTERING...................................................................................... 21
9
PERIPHERALS ................................................................................................................................... 23
9.1 RESET ................................................................................................................................................. 23
9.2 I/O PORTS ............................................................................................................................................ 23
9.3 ADC ................................................................................................................................................... 25
9.4 RANDOM NUMBER GENERATOR ......................................................................................................... 27
9.5 USART............................................................................................................................................... 28
10
RADIO .................................................................................................................................................. 29
10.1 IEEE 802.15.4 MODULATION FORMAT ............................................................................................... 30
10.2 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION ....................................................... 31
10.3 FRAME FORMAT .................................................................................................................................. 31
10.4 SYNCHRONIZATION HEADER ............................................................................................................... 32
10.5 MAC PROTOCOL DATA UNIT ............................................................................................................... 32
10.6 FRAME CHECK SEQUENCE ................................................................................................................... 32
10.7 LINEAR IF AND AGC SETTINGS .......................................................................................................... 33
10.8 CLEAR CHANNEL ASSESSMENT........................................................................................................... 33
10.9 VCO AND PLL SELF-CALIBRATION .................................................................................................... 33
10.10 INPUT / OUTPUT MATCHING ................................................................................................................ 33
10.11 SYSTEM CONSIDERATIONS AND GUIDELINES ...................................................................................... 34
10.12 PCB LAYOUT RECOMMENDATION ...................................................................................................... 35
10.13 ANTENNA CONSIDERATIONS ............................................................................................................... 35
CC2480 Data Sheet SWRS074A
Page 2 of 43
CC2480
11
VOLTAGE REGULATORS............................................................................................................... 36
11.1 VOLTAGE REGULATORS POWER-ON.................................................................................................... 36
12
PACKAGE DESCRIPTION (QLP 48) .............................................................................................. 37
12.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 48)...................................................................... 38
12.2 PACKAGE THERMAL PROPERTIES......................................................................................................... 38
12.3 SOLDERING INFORMATION .................................................................................................................. 38
12.4 TRAY SPECIFICATION .......................................................................................................................... 38
12.5 CARRIER TAPE AND REEL SPECIFICATION ............................................................................................ 38
13
ORDERING INFORMATION........................................................................................................... 40
14
GENERAL INFORMATION ............................................................................................................. 41
14.1 DOCUMENT HISTORY .......................................................................................................................... 41
15
ADDRESS INFORMATION .............................................................................................................. 41
16
TI WORLDWIDE TECHNICAL SUPPORT ................................................................................... 41
CC2480 Data Sheet SWRS074A
Page 3 of 43
CC2480
1
Abbreviations
ADC
Analog to Digital Converter
LSB
Least Significant Byte
AES
Advanced Encryption Standard
MAC
Medium Access Control
AGC
Automatic Gain Control
MISO
Master In Slave Out
API
Application Programming Interface
MOSI
Master Out Slave In
ARIB
Association of Radio Industries and
Businesses
MPDU
MAC Protocol Data Unit
MSB
Most Significant Byte
BOD
Brown Out Detector
MUX
Multiplexer
BOM
Bill of Materials
NA
Not Available
CCA
Clear Channel Assessment
NC
Not Connected
CFR
Code of Federal Regulations
O-QPSK
Offset - Quadrature Phase Shift Keying
CPU
Central Processing Unit
PA
Power Amplifier
CRC
Cyclic Redundancy Check
PCB
Printed Circuit Board
CSMA-CA
Carrier Sense Multiple Access with
Collision Avoidance
PER
Packet Error Rate
CW
Continuous Wave
PHY
Physical Layer
DAC
Digital to Analog Converter
PLL
Phase Locked Loop
DC
Direct Current
PM{0-3}
Power Mode 0-3
DNL
Differential Nonlinearity
POR
Power On Reset
DSM
Delta Sigma Modulator
PWM
Pulse Width Modulator
DSSS
Direct Sequence Spread Spectrum
QLP
Quad Leadless Package
EM
Evaluation Module
RAM
Random Access Memory
ENOB
Effective Number of bits
RC
Resistor-Capacitor
ESD
Electro Static Discharge
RCOSC
RC Oscillator
ESR
Equivalent Series Resistance
RF
Radio Frequency
ETSI
European Telecommunications
Standards Institute
RoHS
Restriction on Hazardous Substances
RSSI
Receive Signal Strength Indicator
EVM
Error Vector Magnitude
RX
Receive
FCC
Federal Communications Commission
SCK
Serial Clock
FCF
Frame Control Field
SFD
Start of Frame Delimiter
FCS
Frame Check Sequence
SHR
Synchronization Header
I/O
Input / Output
SINAD
Signal-to-noise and distortion ratio
I/Q
In-phase / Quadrature-phase
SPI
Serial Peripheral Interface
IEEE
Institute of Electrical and Electronics
Engineers
SRAM
Static Random Access Memory
IF
Intermediate Frequency
ST
Sleep Timer
INL
Integral Nonlinearity
T/R
Tape and reel
ISM
Industrial, Scientific and Medical
T/R
Transmit / Receive
JEDEC
Joint Electron Device Engineering
Council
TBD
To Be Decided / To Be Defined
THD
Total Harmonic Distortion
KB
1024 bytes
TI
Texas Instruments
kbps
kilo bits per second
TX
Transmit
LFSR
Linear Feedback Shift Register
UART
LNA
Low-Noise Amplifier
Universal Asynchronous
Receiver/Transmitter
LO
Local Oscillator
USART
Universal Synchronous/Asynchronous
Receiver/Transmitter
LQI
Link Quality Indication
VGA
Variable Gain Amplifier
LSB
Least Significant Bit / Byte
XOSC
Crystal Oscillator
CC2480 Data Sheet SWRS074A
Page 4 of 43
CC2480
2
[1]
References
IEEE std. 802.15.4 - 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY)
specifications for Low Rate Wireless Personal Area Networks (LR-WPANs).
http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf
[2]
CC2480 Interface Specification
http://www.ti.com/lit/pdf/swra175
CC2480 Data Sheet SWRS074A
Page 5 of 43
CC2480
3
Absolute Maximum Ratings
Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.
Table 1: Absolute Maximum Ratings
Parameter
Min
Max
Units
Supply voltage, VDD
–0.3
3.9
V
Voltage on any digital pin
–0.3
VDD+0.3,
max 3.9
V
Voltage on the 1.8V pins (pin no.
22, 25-40 and 42)
–0.3
2.0
V
10
dBm
150
°C
Device not programmed
260
°C
According to IPC/JEDEC J-STD-020C
<500
V
On RF pads (RF_P, RF_N, AVDD_RF1,
and AVDD_RF2), according to Human
Body Model, JEDEC STD 22, method A114
700
V
All other pads, according to Human Body
Model, JEDEC STD 22, method A114
200
V
According to Charged Device Model,
JEDEC STD 22, method C101
Input RF level
Storage temperature range
–50
Reflow soldering temperature
ESD
Condition
All supply pins must have the same voltage
Caution! ESD sensitive device. Precaution should be used
when handling the device in order to prevent
permanent damage.
4
Operating Conditions
The operating conditions for CC2480 are listed in Table 2.
Table 2: Operating Conditions
Parameter
Min
Max
Unit
Operating ambient temperature
range, TA
-40
85
°C
Operating supply voltage
2.0
3.6
V
CC2480 Data Sheet SWRS074A
Condition
The supply pins to the radio part must be driven
by the 1.8 V on-chip regulator
Page 6 of 43
CC2480
5
Electrical Specifications
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 3: Electrical Specifications
Parameter
Min
Typ
Max
Unit
Condition
mA
Digital regulator on. 16 MHz RCOSC running. No radio,
crystals, or peripherals active.
Low CPU activity: no flash access (i.e. only cache hit), no
RAM access.
Current Consumption
CPU Active Mode, 16 MHz,
low CPU activity
4.3
CPU Active Mode, 16 MHz,
medium CPU activity
5.1
mA
Digital regulator on. 16 MHz RCOSC running. No radio,
crystals, or peripherals active.
1
Medium CPU activity: normal flash access , minor RAM
access.
CPU Active Mode, 16 MHz,
high CPU activity
5.7
mA
Digital regulator on. 16 MHz RCOSC running. No radio,
crystals, or peripherals active.
High CPU activity: normal flash access, extensive RAM
access and heavy CPU load.
CPU Active Mode, 32 MHz,
low CPU activity
9.5
mA
32 MHz XOSC running. No radio or peripherals active.
Low CPU activity : no flash access (i.e. only cache hit),
no RAM access
CPU Active Mode, 32 MHz,
medium CPU activity
10.5
mA
32 MHz XOSC running. No radio or peripherals active.
1
Medium CPU activity: normal flash access , minor RAM
access.
CPU Active Mode, 32 MHz,
high CPU activity
12.3
mA
32 MHz XOSC running. No radio or peripherals active.
1
High CPU activity: normal flash access , extensive RAM
access and heavy CPU load.
CPU Active and RX Mode
26.7
mA
CPU running at full speed (32MHz), 32MHz XOSC
running, radio in RX mode, -50 dBm input power. No
peripherals active. Low CPU activity.
CPU Active and TX Mode, 0dBm
26.9
mA
CPU running at full speed (32MHz), 32MHz XOSC
running, radio in TX mode, 0dBm output power. No
peripherals active. Low CPU activity.
Power mode 1
190
µA
Digital regulator on, 16 MHz RCOSC and 32 MHz crystal
oscillator off. 32.768 kHz XOSC, POR and ST active.
RAM retention.
Power mode 2
0.5
µA
Digital regulator off, 16 MHz RCOSC and 32 MHz crystal
oscillator off. 32.768 kHz XOSC, POR and ST active.
RAM retention.
Power mode 3
0.3
µA
No clocks. RAM retention. POR active.
Peripheral Current
Consumption
Adds to the figures above if the peripheral unit is
activated
Sleep Timer
0.2
µA
Including 32.753 kHz RCOSC.
ADC
1.2
mA
When converting.
Flash write
3
mA
Estimated value
Flash erase
3
mA
Estimated value
1
Normal Flash access means that the code used exceeds the cache storage so cache misses will
happen frequently.
CC2480 Data Sheet SWRS074A
Page 7 of 43
CC2480
5.1
General Characteristics
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 4: General Characteristics
Parameter
Min
Typ
Max
Unit
Condition/Note
Wake-Up and Timing
Power mode 1 Æ power
mode 0
4.1
µs
Digital regulator on, 16 MHz RCOSC and
32 MHz crystal oscillator off. Start-up of
16 MHz RCOSC.
Power mode 2 or 3 Æ power
mode 0
120
µs
Digital regulator off, 16 MHz RCOSC and
32 MHz crystal oscillator off. Start-up of
regulator and 16 MHz RCOSC.
Active Æ TX or RX
32MHz XOSC initially OFF.
Voltage regulator initially OFF
525
µs
Time from enabling radio part in power
mode 0, until TX or RX starts. Includes
start-up of voltage regulator and crystal
oscillator in parallel. Crystal ESR=16Ω.
Active Æ TX or RX
Voltage regulator initially OFF
320
µs
Time from enabling radio part in power
mode 0, until TX or RX starts. Includes
start-up of voltage regulator.
Radio part already enabled.
Time until RX or TX starts.
Active Æ RX or TX
192
µs
RX/TX turnaround
192
µs
Radio part
RF Frequency Range
2400
2483.5
MHz
Programmable in 1 MHz steps, 5 MHz
between channels for compliance with
[1]
Radio bit rate
250
kbps
As defined by [1]
Radio chip rate
2.0
MChip/s
As defined by [1]
CC2480 Data Sheet SWRS074A
Page 8 of 43
CC2480
5.2
RF Receive Section
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 5: RF Receive Parameters
Parameter
Receiver sensitivity
Min
Typ
Max
-92
Unit
dBm
Condition/Note
PER = 1%, as specified by [1]
Measured in 50 Ω single endedly through a balun.
[1] requires –85 dBm
Saturation (maximum input
level)
10
dBm
PER = 1%, as specified by [1]
Measured in 50 Ω single endedly through a balun.
[1] requires –20 dBm
Adjacent channel rejection
+ 5 MHz channel spacing
41
dB
Wanted signal -88dBm, adjacent modulated channel
at +5 MHz, PER = 1 %, as specified by [1].
[1] requires 0 dB
Adjacent channel rejection
- 5 MHz channel spacing
30
dB
Wanted signal -88dBm, adjacent modulated channel
at -5 MHz, PER = 1 %, as specified by [1].
[1] requires 0 dB
Alternate channel rejection
+ 10 MHz channel spacing
55
dB
Wanted signal -88dBm, adjacent modulated channel
at +10 MHz, PER = 1 %, as specified by [1]
[1] requires 30 dB
Alternate channel rejection
- 10 MHz channel spacing
53
dB
Wanted signal -88dBm, adjacent modulated channel
at -10 MHz, PER = 1 %, as specified by [1]
[1] requires 30 dB
Channel rejection
≥ + 15 MHz
55
dB
≤ - 15 MHz
53
dB
-6
dB
+ 5 MHz from band edge
+ 10 MHz from band edge
+ 20 MHz from band edge
+ 50 MHz from band edge
-42
-29
-26
-22
dBm
dBm
dBm
dBm
- 5 MHz from band edge
- 10 MHz from band edge
- 20 MHz from band edge
- 50 MHz from band edge
-31
-36
-24
-25
dBm
dBm
dBm
dBm
Co-channel rejection
Wanted signal @ -82 dBm. Undesired signal is an
802.15.4 modulated channel, stepped through all
channels from 2405 to 2480 MHz. Signal level for
PER = 1%. Values are estimated.
Wanted signal @ -82 dBm. Undesired signal is
802.15.4 modulated at the same frequency as the
desired signal. Signal level for PER = 1%.
Blocking / Desensitization
Wanted signal 3 dB above the sensitivity level, CW
jammer, PER = 1%. Measured according to EN 300
440 class 2.
Spurious emission
30 – 1000 MHz
1 – 12.75 GHz
Frequency error tolerance
−64
−75
±140
dBm
dBm
Conducted measurement in a 50 Ω single ended
load. Complies with EN 300 328, EN 300 440 class
2, FCC CFR47, Part 15 and ARIB STD-T-66.
ppm
Difference between centre frequency of the received
RF signal and local oscillator frequency.
[1] requires minimum 80 ppm
Symbol rate error tolerance
±900
ppm
Difference between incoming symbol rate and the
internally generated symbol rate
[1] requires minimum 80 ppm
5.3
RF Transmit Section
Measured on Texas Instruments CC2480 EM reference design with TA=25°C, VDD=3.0V, and
nominal output power unless stated otherwise.
CC2480 Data Sheet SWRS074A
Page 9 of 43
CC2480
Table 6: RF Transmit Parameters
Parameter
Min
Typ
Nominal output
power
Max
Unit
0
dBm
Condition/Note
Delivered to a single ended 50 Ω load through a balun.
[1] requires minimum –3 dBm
Harmonics
nd
-50.7
dBm
rd
-55.8
dBm
harmonic
-54.2
dBm
5 harmonic
-53.4
dBm
2 harmonic
3 harmonic
4
th
th
Spurious emission
Measurement conducted with 100 kHz resolution bandwidth on
spectrum analyzer. Output Delivered to a single ended 50 Ω load
through a balun.
Maximum output power.
Texas Instruments CC2480 EM reference design complies with
EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STDT-66.
Transmit on 2480MHz under FCC is supported by duty-cycling
30 - 1000 MHz
-47
dBm
1– 12.75 GHz
-43
dBm
1.8 – 1.9 GHz
-58
dBm
5.15 – 5.3 GHz
-56
dBm
The peak conducted spurious emission is -47 dBm @ 192 MHz
which is in an EN 300 440 restricted band limited to -54 dBm. All
radiated spurious emissions are within the limits of
ETSI/FCC/ARIB. Conducted spurious emission (CSE) can be
reduced with a simple band pass filter connected between
matching network and RF connector (1.8 pF in parallel with 1.6
nH reduces the CSE by 20 dB), this filter must be connected to
good RF ground.
EVM
11
%
Measured as defined by [1]
[1] requires max. 35 %
Optimum load
impedance
5.4
Ω
60
+ j164
Differential impedance as seen from the RF-port (RF_P and
RF_N) towards the antenna2.
32 MHz Crystal Oscillator
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 7: 32 MHz Crystal Oscillator Parameters
Parameter
Min
Crystal frequency
Crystal frequency
accuracy
requirement
Typ
Max
Unit
32
- 40
Condition/Note
MHz
40
ppm
Ω
Including aging and temperature dependency, as specified by [1]
ESR
6
16
60
C0
1
1.9
7
pF
Simulated over operating conditions
CL
10
13
16
pF
Simulated over operating conditions
Start-up time
5.5
212
Simulated over operating conditions
µs
32.768 kHz Crystal Oscillator
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
2
This is for 2440MHz
CC2480 Data Sheet SWRS074A
Page 10 of 43
CC2480
Table 8: 32.768 kHz Crystal Oscillator Parameters
Parameter
Min
Crystal frequency
Crystal frequency
accuracy
requirement
Typ
Max
32.768
–40
Unit
Condition/Note
kHz
40
ppm
kΩ
Including aging and temperature dependency, as specified by [1]
ESR
40
130
C0
0.9
2.0
pF
Simulated over operating conditions
CL
12
16
pF
Simulated over operating conditions
Start-up time
400
ms
Value is simulated.
5.6
Simulated over operating conditions
32 kHz RC Oscillator
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 9: 32 kHz RC Oscillator parameters
Parameter
Min
Calibrated frequency
Typ
Max
32.753
Unit
Condition/Note
kHz
The calibrated 32 kHz RC Oscillator frequency
is the 32 MHz XTAL frequency divided by 977
Frequency accuracy after
calibration
±0.2
%
Value is estimated.
Temperature coefficient
+0.4
% / °C
Frequency drift when temperature changes
after calibration. Value is estimated.
Supply voltage coefficient
+3
%/V
Frequency drift when supply voltage changes
after calibration. Value is estimated.
Initial calibration time
1.7
ms
When the 32 kHz RC Oscillator is enabled,
calibration is continuously done in the
background as long as the 32 MHz crystal
oscillator is running.
5.7
16 MHz RC Oscillator
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 10: 16 MHz RC Oscillator parameters
Parameter
Min
Typ
Max
Unit
Condition/Note
The calibrated 16 MHz RC Oscillator
frequency is the 32 MHz XTAL frequency
divided by 2
Frequency
16
MHz
Uncalibrated frequency
accuracy
±18
%
Calibrated frequency
accuracy
±0.6
Start-up time
Temperature coefficient
Supply voltage coefficient
Initial calibration time
50
±1
%
10
µs
-325
ppm / °C
Frequency drift when temperature changes
after calibration
28
ppm / mV
Frequency drift when supply voltage changes
after calibration
µs
When the 16 MHz RC Oscillator is enabled it
will be calibrated continuously when the
32MHz crystal oscillator is running.
CC2480 Data Sheet SWRS074A
Page 11 of 43
CC2480
5.8
Frequency Synthesizer Characteristics
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 11: Frequency Synthesizer Parameters
Parameter
Min
Typ
Max
Unit
Condition/Note
Phase noise
Unmodulated carrier
−116
−117
−118
PLL lock time
5.9
192
dBc/Hz
dBc/Hz
dBc/Hz
At ±1.5 MHz offset from carrier
At ±3 MHz offset from carrier
At ±5 MHz offset from carrier
µs
The startup time until RX/TX turnaround. The crystal
oscillator is running.
Analog Temperature Sensor
Measured on Texas Instruments CC2480 EM reference design with TA=25°C and VDD=3.0V
unless stated otherwise.
Table 12: Analog Temperature Sensor Parameters
Parameter
Min
Typ
Max
Unit
Condition/Note
Output voltage at –40°C
0.648
V
Value is estimated
Output voltage at 0°C
0.743
V
Value is estimated
Output voltage at +40°C
0.840
V
Value is estimated
Output voltage at +80°C
0.939
V
Value is estimated
Temperature coefficient
2.45
mV/°C
Fitted from –20°C to +80°C on estimated values.
°C
From –20°C to +80°C when assuming best fit for
absolute accuracy on estimated values: 0.743V at
0°C and 2.45mV / °C.
°C
From –20°C to +80°C when using 2.45mV / °C,
after 1-point calibration at room temperature.
Values are estimated. Indicated min/max with 1point calibration is based on simulated values for
typical process parameters
Absolute error in calculated
temperature
Error in calculated
temperature, calibrated
–8
-2
0
Current consumption
increase when enabled
2
280
µA
5.10 ADC
Measured with TA=25°C and VDD=3.0V. Note that other data may result when using Texas
Instruments’ CC2480 EM reference design.
Table 13: ADC Characteristics
Parameter
Min
Input voltage
Max
Unit
Condition/Note
VDD
V
VDD is voltage on AVDD_SOC pin
197
kΩ
Simulated using 4 MHz clock speed.
2.97
V
Peak-to-peak, defines 0dBFS
0
Input resistance, signal
3
Full-Scale Signal
3
Typ
Measured with 300 Hz Sine input and VDD as reference.
CC2480 Data Sheet SWRS074A
Page 12 of 43
CC2480
Parameter
ENOB
Min
3
5.7
Single ended input
ENOB
Typ
Error! Bookmark not defined.
Useful Power Bandwidth
Unit
bits
Condition/Note
7-bits setting.
7.5
9-bits setting.
9.3
10-bits setting.
10.8
12-bits setting.
6.5
Differential input
Max
bits
7-bits setting.
8.3
9-bits setting.
10.0
10-bits setting.
11.5
12-bits setting.
0-20
kHz
7-bits setting
-75.2
dB
12-bits setting, -6dBFS
-86.6
dB
12-bits setting, -6dBFS
70.2
dB
12-bits setting
79.3
dB
12-bits setting
-Single ended input
78.8
dB
12-bits setting, -6dBFS
-Differential input
88.9
dB
12-bits setting, -6dBFS
CMRR, differential input
<-84
dB
12- bit setting, 1 kHz Sine (0dBFS), limited by ADC
resolution
Crosstalk, single ended input
<-84
dB
12- bit setting, 1 kHz Sine (0dBFS), limited by ADC
resolution
-3
mV
Mid. Scale
3
THD
-Single ended input
-Differential input
Signal To Non-Harmonic Ratio
3
-Single ended input
-Differential input
Spurious Free Dynamic Range
Offset
3
Gain error
0.68
%
3
0.05
LSB
12-bits setting, mean
0.9
LSB
12-bits setting, max
4.6
LSB
12-bits setting, mean
DNL
INL
3
13.3
LSB
12-bits setting, max
SINAD
35.4
dB
7-bits setting.
Single ended input
46.8
dB
9-bits setting.
(-THD+N)
57.5
dB
10-bits setting.
66.6
dB
12-bits setting.
SINAD
40.7
dB
7-bits setting.
Differential input
51.6
dB
9-bits setting.
(-THD+N)
61.8
dB
10-bits setting.
70.8
dB
12-bits setting.
20
µs
7-bits setting.
36
µs
9-bits setting.
68
µs
10-bits setting.
132
µs
12-bits setting.
1.2
mA
3
Error! Bookmark not defined.
Conversion time
Power Consumption
CC2480 Data Sheet SWRS074A
Page 13 of 43
CC2480
5.11 Control AC Characteristics
TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated.
Table 14: Control Inputs AC Characteristics
Parameter
System clock,
fSYSCLK
Min
Typ
16
Max
Unit
Condition/Note
32
MHz
System clock is 32 MHz when crystal oscillator is used.
System clock is 16 MHz when calibrated 16 MHz RC
oscillator is used.
tSYSCLK= 1/ fSYSCLK
RESET_N low
width
250
ns
See item 1, Figure 1. This is the shortest pulse that is
guaranteed to be recognized as a complete reset pin
request. Note that shorter pulses may be recognized but
will not lead to complete reset of all modules within the
chip.
Interrupt pulse
width
tSYSCLK
ns
See item 2, Figure 1.This is the shortest pulse that is
guaranteed to be recognized as an interrupt request. In
PM2/3 the internal synchronizers are bypassed so this
requirement does not apply in PM2/3.
1
RESET_N
GPIOx
2
2
GPIOx
Figure 1: Control Inputs AC Characteristics
CC2480 Data Sheet SWRS074A
Page 14 of 43
CC2480
5.12 SPI AC Characteristics
TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated.
Table 15: SPI AC Characteristics
Parameter
Min
Typ
Max
Unit
Condition/Note
SSN low to SCK
2*tSYSCLK
See item 5 Figure 2
SCK to SSN high
30
ns
See item 6 Figure 2
SCK period
100
ns
See item 1 Figure 2
SCK duty cycle
50%
SI setup
10
ns
See item 2 Figure 2
SI hold
10
ns
See item 3 Figure 2
ns
See item 4 Figure 2, load = 10 pF
SCK to SO
25
Figure 2: SPI AC Characteristics
5.13 Port Outputs AC Characteristics
TA= 25°C, VDD=3.0V if nothing else stated.
Table 16: Port Outputs AC Characteristics
Parameter
Min
Typ
GPIO/USART output
rise time
(SC=0/SC=1)
3.15/
1.34
fall time
(SC=0/SC=1)
3.2/
1.44
Max
Unit
Condition/Note
ns
Load = 10 pF
Timing is with respect to 10% VDD and 90% VDD levels.
Values are estimated
Load = 10 pF
Timing is with respect to 90% VDD and 10% VDD.
Values are estimated
5.14 DC Characteristics
The DC Characteristics of CC2480 are listed in Table 17 below.
TA=25°C, VDD=3.0V if nothing else stated.
Table 17: DC Characteristics
CC2480 Data Sheet SWRS074A
Page 15 of 43
CC2480
Digital Inputs/Outputs
Min
Typ
Logic "0" input voltage
Max
30
Unit
Condition
%
Of VDD supply (2.0 – 3.6 V)
%
Of VDD supply (2.0 – 3.6 V)
Logic "1" input voltage
70
Logic "0" input current per pin
NA
12
nA
Input equals 0V
Logic "1" input current
NA
12
nA
Input equals VDD
Total logic “0” input current all pins
70
nA
Total logic “1” input current all pins
70
nA
I/O pin pull-up and pull-down
resistor
20
CC2480 Data Sheet SWRS074A
kΩ
Page 16 of 43
CC2480
6
Pin and I/O Port Configuration
The CC2480 pinout is shown in Figure 3 with details in Table 18.
Figure 3: Pinout top view
Note: The exposed die attach pad must be connected to a solid ground plane as this is the
ground connection for the chip.
CC2480 Data Sheet SWRS074A
Page 17 of 43
CC2480
Table 18: Pinout overview
Pin
1
Pin name
GND
NC
Pin type
Ground
N/A
Description
The exposed die attach pad must be connected to a solid ground plane
2
3
4
5
6
7
NC
GPIO3
GPIO2
SRDY
MRDY
DVDD
N/A
Digital I/O
Digital I/O
Digital Output
Digital Input
Power (Digital)
General I/O pin 3
General I/O pin 2
Slave ready. Mandatory for SPI, optional for UART.
Master ready. Optional for SPI and UART.
2.0V-3.6V digital power supply for digital I/O
8
9
10
11
12
13
GPIO1
GPIO0
RESET_N
CFG0
CFG1
SO/RX
Digital I/O
Digital I/O
Digital input
Digital Input
Digital Input
Digital Input
General I/O pin 1 – increased drive capability
General I/Opin 0 – increased drive capability
Reset, active low
Configuration input 0
Configuration input 1
SPI slave output or UART RX data
14
15
16
17
18
19
SI/TX
SS/CT
C/RT
A0
A1
XOSC_Q2
Digital Output
Digital I/O
Digital Input
Analog Input
Analog Input
Analog I/O
SPI slave input or UART TX data
SPI slave select (in) or UART CTS (out)
SPI clock or UART RTS
ADC input A0
ADC input A1
32 MHz crystal oscillator pin 2
20
21
22
23
24
AVDD_SOC
XOSC_Q1
RBIAS1
AVDD_RREG
RREG_OUT
Power (Analog)
Analog I/O
Analog I/O
Power (Analog)
Power output
2.0V-3.6V analog power supply connection
32 MHz crystal oscillator pin 1, or external clock input
External precision bias resistor for reference current
2.0V-3.6V analog power supply connection
1.8V Voltage regulator power supply output. Only intended for supplying the analog
1.8V part (power supply for pins 25, 27-31, 35-40).
25
AVDD_IF1
Power (Analog)
1.8V Power supply for the receiver band pass filter, analog test module, global bias
and first part of the VGA
External precision resistor, 43 kΩ, ±1 %
1.8V Power supply for phase detector, charge pump and first part of loop filter
26
RBIAS2
Analog output
27
AVDD_CHP
Power (Analog)
28
29
30
31
32
VCO_GUARD
AVDD_VCO
AVDD_PRE
AVDD_RF1
RF_P
Power (Analog)
Power (Analog)
Power (Analog)
Power (Analog)
RF I/O
Connection of guard ring for VCO (to AVDD) shielding
1.8V Power supply for VCO and last part of PLL loop filter
1.8V Power supply for Prescaler, Div-2 and LO buffers
1.8V Power supply for LNA, front-end bias and PA
Positive RF input signal to LNA during RX. Positive RF output signal from PA during
TX
33
34
TXRX_SWITCH
RF_N
Power (Analog)
RF I/O
35
36
37
AVDD_SW
AVDD_RF2
AVDD_IF2
Power (Analog)
Power (Analog)
Power (Analog)
Regulated supply voltage for PA
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
1.8V Power supply for LNA / PA switch
1.8V Power supply for receive and transmit mixers
1.8V Power supply for transmit low pass filter and last stages of VGA
38
39
40
41
42
43
AVDD_ADC
DVDD_ADC
AVDD_DGUARD
AVDD_DREG
DCOUPL
32K_XOSC_Q2
Power (Analog)
Power (Digital)
Power (Digital)
Power (Digital)
Power (Digital)
Analog I/O
1.8V Power supply for analog parts of ADCs and DACs
1.8V Power supply for digital parts of ADCs
Power supply connection for digital noise isolation
2.0V-3.6V digital power supply for digital core voltage regulator
1.8V digital power supply decoupling. Do not use for supplying external circuits.
32.768 kHz XOSC
44
45
46
47
48
32K_XOSC_Q1
NC
NC
DVDD
NC
Analog I/O
N/A
N/A
Power (Digital)
N/A
32.768 kHz XOSC
2.0V-3.6V digital power supply for digital I/O
CC2480 Data Sheet SWRS074A
Page 18 of 43
CC2480
7
Circuit Description
DIGITAL
ANALOG
XOSC_Q2
XOSC_Q1
32 MHz
CRYSTAL OSC
HIGH SPEED
RC-OSC
POWER ON RESET
BROWN OUT
32.768 kHz
CRYSTAL OSC
32 kHz RC-OSC
SLEEP TIMER
RESET
CLOCK MUX &
CALIBRATION
SLEEP MODE CONTROLLER
RESET_N
128 KB
FLASH
GPIO3
GPIO2
GPIO1
GP
I/O
8051 CPU
CORE
DMA
MEMORY
ARBITRATOR
GPIO0
8 KB
SRAM
IRQ
CTRL
A1
A0
∆Σ ADC
AUDIO / DC
2 CHANNELS
AES
ENCRYPTION
&
DECRYPTION
FLASH
WRITE
DEMODULATOR
AGC
MODULATOR
SRDY
SI/TX
SO/RX
USART
FREQUENCY
SYNTHESIZER
MRDY
RECEIVE
CHAIN
SS/CT
C/RT
RF_P
TRANSMIT
CHAIN
IEEE 802.15.4 MAC TIMER
32K_XOSC_Q1
DCOUPL
FIFO AND FRAME CONTROL
32K_XOSC_Q2
VDD (2.0 - 3.6 V)
ON-CHIP VOLTAGE
REGULATOR
MIXED
RF_N
Figure 4: CC2480 Block Diagram
A block diagram of CC2480 is shown in Figure
4. The modules can be roughly divided into
one of three categories: CPU-related modules,
modules related to power and clock
distribution, and radio-related modules. CC2480
features an IEEE 802.15.4 compliant radio
based on the leading CC2420 transceiver. See
Section 10 for details.
CC2480 Data Sheet SWRS074A
Page 19 of 43
CC2480
8
Application Circuit
Few external components are required for the
operation of CC2480. A typical application
circuit is shown in Figure 5. Typical values and
8.1
Input / output matching
The RF input/output is high impedance and
differential. The optimum differential load for
the RF port is 60 + j164 Ω4.
When using an unbalanced antenna such as a
monopole, a balun should be used in order to
optimize performance. The balun can be
implemented using low-cost discrete inductors
and capacitors. The recommended balun
shown, consists of C341, L341, L321 and
L331 together with a PCB microstrip
transmission line (λ/2-dipole), and will match
the RF input/output to 50 Ω. An internal T/R
switch circuit is used to switch between the
4
This is for 2440MHz.
8.2
description of external components are shown
in Table 19.
LNA (RX) and the PA (TX). See Input/output
matching section on page 33 for more details.
If a balanced antenna such as a folded dipole
is used, the balun can be omitted. If the
antenna also provides a DC path from
TXRX_SWITCH pin to the RF pins, inductors
are not needed for DC bias.
Figure 5 shows a suggested application circuit
using a differential antenna. The antenna type
is a standard folded dipole. The dipole has a
virtual ground point; hence bias is provided
without degradation in antenna performance.
Also
refer
to
the
section
Antenna
Considerations on page 35.
Bias resistors
The bias resistors are R221 and R261. The
bias resistor R221 is used to set an accurate
bias current for the 32 MHz crystal oscillator.
8.3
Crystal
An external 32 MHz crystal, XTAL1, with two
loading capacitors (C191 and C211) is used
for the 32 MHz crystal oscillator. See page 10
for details. The load capacitance seen by the
32 MHz crystal is given by:
CL =
1
1
1
+
C191 C 211
CL =
+ C parasitic
XTAL2 is an optional 32.768 kHz crystal, with
two loading capacitors (C441 and C431), used
for the 32.768 kHz crystal oscillator. The
32.768 kHz crystal oscillator is used in
applications where you need both very low
8.4
sleep current consumption and accurate wake
up times. The load capacitance seen by the
32.768 kHz crystal is given by:
1
1
1
+
C 441 C 431
+ C parasitic
A series resistor may be used to comply with
the ESR requirement.
Voltage regulators
The on chip voltage regulators supply all 1.8 V
power supply pins and internal power supplies.
C241 and C421 are required for stability of the
regulators.
CC2480 Data Sheet SWRS074A
Page 20 of 43
CC2480
8.5
Power supply decoupling and filtering
Proper power supply decoupling must be used
for optimum performance. The placement and
size of the decoupling capacitors and the
power supply filtering are very important to
achieve the best performance in an
application. TI provides a compact reference
design that should be followed very closely.
Refer
to
the
section
PCB
Recommendation on page 35.
C431
C441
C421
2.0 - 3.6V Power Supply
39
38
AVDD_ADC
AVDD_IF2 37
40
DVDD_ADC
43
32K_XOSC_Q2
41
44
32K_XOSC_Q1
AVDD_DREG
45
NC
NC
AVDD_DGUARD
46
NC
DVDD 47
48
NC
1
DCOUPL 42
XTAL2
optional
2
NC
3
GPIO3
RF_N 34
4
GPIO2
TXRX_SWITCH 33
5
SRDY
6
AVDD_SW 35
L331
CC2480
AVDD_RF1 31
7
DVDD
8
GPIO1
AVDD_VCO 29
9
GPIO0
VCO_GUARD 28
AVDD_PRE 30
10 RESET_N
AVDD_CHP 27
11 CFG0
λ/4
λ/4
or
R261
RBIAS2 26
RREG_OUT 24
AVDD_IF1 25
L331
XTAL1
R221
C241
C191
L321
Folded Dipole PCB
Antenna
RBIAS1 22
AVDD_RREG 23
XOSC_Q1 21
19
17
18
20
A1
16
14
A0
C/RT
SI/TX
SS/CT 15
SO/RX 13
XOSC_Q2
CFG1
AVDD_SOC
12
L341 C341
Figure 5:
CC2480
Applicatio
n Circuit.
(Digital I/O
and ADC
interface
not
connected
).
Decouplin
g
capacitors
not shown.
L321
RF_P 32
Q L P 4 8
7 x 7
MRDY
Antenna
(50 Ohm)
AVDD_RF2 36
Layout
C211
CC2480 Data Sheet SWRS074A
Page 21 of 43
CC2480
Table 19: Overview of external components (excluding supply decoupling capacitors)
Component
Description
Single Ended 50Ω Output
Differential Antenna
C191
32 MHz crystal load capacitor
33 pF, 5%, NP0, 0402
33 pF, 5%, NP0, 0402
C211
32 MHz crystal load capacitor
27 pF, 5%, NP0, 0402
27 pF, 5%, NP0, 0402
C241
Load capacitance for analogue power
supply voltage regulators
220 nF, 10%, 0402
220 nF, 10%, 0402
C421
Load capacitance for digital power supply
voltage regulators
1 µF, 10%, 0402
1 µF, 10%, 0402
C341
DC block to antenna and match
Note: For RF connector a LP filter can be
connected between this C, the antenna
and good ground in order to remove
conducted spurious emission by using
1.8pF in parallel with 1.6nH
5.6 pF, 5%, NP0, 0402
Not used
32.768 kHz crystal load capacitor (if lowfrequency crystal is needed in application)
15 pF, 5%, NP0, 0402
15 pF, 5%, NP0, 0402
L321
Discrete balun and match
6.8 nH, 5%,
Monolithic/multilayer, 0402
12 nH 5%,
Monolithic/multilayer, 0402
L331
Discrete balun and match
22 nH, 5%,
Monolithic/multilayer, 0402
27 nH, 5%,
Monolithic/multilayer, 0402
L341
Discrete balun and match
1.8 nH, +/-0.3 nH,
Monolithic/multilayer, 0402
Not used
R221
Precision resistor for current reference
generator to system-on-chip part
56 kΩ, 1%, 0402
56 kΩ, 1%, 0402
R261
Precision resistor for current reference
generator to RF part
43 kΩ, 1%, 0402
43 kΩ, 1%, 0402
XTAL1
32 MHz Crystal
32 MHz crystal,
ESR < 60 Ω
32 MHz crystal,
ESR < 60 Ω
XTAL2
Optional 32.768 kHz watch crystal (if lowfrequency crystal is needed in application)
32.768 kHz crystal,
Epson MC 306.
32.768 kHz crystal,
Epson MC 306.
C431, C441
1.8 pF, Murata COG 0402,
GRM15
1.6 nH, Murata 0402,
LQG15HS1N6S02
CC2480 Data Sheet SWRS074A
Page 22 of 43
CC2480
9
Peripherals
In the following sub-sections the useraccessible CC2480 peripheral modules are
described
in
detail.
9.1
Reset
The CC2480 has four reset sources. The
following events generate a reset:
The initial conditions after a reset are as
follows:
•
•
•
•
•
Forcing RESET_N input pin low
A power-on reset condition
A brown-out reset condition
A
firmware-generated
(SYS_RESET_REQ [2])
9.1.1
•
reset
I/O pins are configured as inputs with pullup
See the CC2480 Interface Specification [2]
for a description of the interaction between
CC2480 and the host processor after
reset.
Power On Reset and Brown Out Detector
The CC2480 includes a Power On Reset (POR)
providing correct initialization during device
power-on. Also includes is a Brown Out
Detector (BOD) operating on the regulated
1.8V digital power supply only, The BOD will
protect the memory contents during supply
voltage variations which cause the regulated
1.8V power to drop below the minimum level
required by flash memory and SRAM.
state until the supply voltage reaches above
the Power On Reset and Brown Out voltages.
Figure 6 shows the POR/BOD operation with
the 1.8V (typical) regulated supply voltage
together with the active low reset signals
BOD_RESET and POR_RESET shown in the
bottom of the figure (note that signals are not
available, just for illustration of events).
When power is initially applied to the CC2480
the Power On Reset (POR) and Brown Out
Detector (BOD) will hold the device in reset
1.8V REGULATED
VOLT
UNREGULATED
BOD RESET ASSERT
POR RESET DEASSERT RISING VDD
POR RESET ASSERT FALLING VDD
0
POR OUTPUT
BOD RESET
POR RESET
X
X
X
X
X
X
Figure 6 : Power On Reset and Brown Out Detector Operation
9.2
I/O ports
The CC2480 has digital input/output pins that
have the following key features:
•
•
•
General purpose I/O or peripheral I/O
Pull-up or pull-down capability on inputs
External interrupt capability
Two of the I/O pins have external interrupts
that can be used to wake up the device from
sleep modes.
CC2480 Data Sheet SWRS074
Page 23 of 43
CC2480
9.2.1
Unused I/O pins
Unused I/O pins should have a defined level
and not be left floating. One way to do this is to
leave the pin unconnected and configured with
9.2.2
Low I/O Supply Voltage
In applications where the digital I/O power
supply voltage pin DVDD is below 2.6 V, the
SC bit should be set to 1 in order to obtain
output DC characteristics specified in section
9.2.3
pull-up resistor. This is also the state of all pins
after reset.
5.14. See the CC2480 user guide [2] for a
description of how to do this.
General Purpose I/O
See the CC2480 user guide [2] for a description
of how to configure and use the GPIO pins.
The output drive strength is 4 mA on all
outputs, except for the two high-drive outputs,
GPIO0 and GPIO1, which each have ~20 mA
output drive strength.
When used as an input, the general purpose
I/O port pins can be configured to have a pull-
up, pull-down or tri-state mode of operation. By
default, after a reset, inputs are configured as
inputs with pull-up. Please note that GPIO0
and GPIO1 do not have pull-up or pull-down
capabilities.
In power modes PM2 and PM3 the I/O pins
retain the I/O mode and output value (if
applicable) that was set when PM2/3 was
entered
CC2480 Data Sheet SWRS074
Page 24 of 43
CC2480
9.3
ADC
9.3.1
ADC Introduction
The ADC supports up to 12-bit analog-todigital conversion. The ADC includes an
analog multiplexer with up to two individually
configurable channels and reference voltage
generator.
The main features of the ADC are as follows:
•
•
•
•
•
Selectable decimation rates which also
sets the resolution (7 to 12 bits).
Two individual input channels, singleended or differential
Internal voltage reference
Temperature sensor input
Battery measurement capability
A1
A0
VDD/3
input
mux
TMP_SENSOR
Sigma-delta
modulator
Decimation
filter
Int 1.25V
Clock generation and
control
Figure 7: ADC block diagram.
9.3.2
ADC Operation
This section describes the general setup and
operation of the ADC.
9.3.2.1
ADC Core
The ADC includes an ADC capable of
converting an analog input into a digital
representation with up to 12 bits resolution.
9.3.2.2
ADC Inputs
The signals from input pins A0 and A1 are
used as single-ended ADC inputs. The ADC
automatically performs a sequence of
conversions when the SYS_ADC_READ
command is issued.
In addition to the input pins A0-1, the output of
an on-chip temperature sensor can be
9.3.2.3
The ADC uses a selectable positive reference
voltage.
selected as an input to
temperature measurements.
the
ADC
for
It is also possible to select a voltage
corresponding to AVDD_SOC/3 as an ADC
input. This input allows the implementation of
e.g. a battery monitor in applications where
this
feature
is
required.
ADC conversion sequences
The CC2480 has two ADC channels that are
connected to external pins. Additionally, the
ADC can measure the chip voltage and
temperature.
The ADC conversions are done channel by
channel incrementally.
In the case where differential inputs are
selected, the differential inputs consist of the
input pair A0-1. Note that no negative supply
can be applied to these pins, nor a supply
larger than VDD (unregulated power). It is the
difference between the pairs that are
converted in differential mode.
The two external pin inputs A0 and A1 can be
used as single-ended or differential inputs.
CC2480 Data Sheet SWRS074
Page 25 of 43
CC2480
In addition to the input pins A0-1, the output of
an on-chip temperature sensor can be
selected as an input to the ADC for
temperature measurements.
9.3.2.4
ADC Operating Modes
This section describes the operating modes
and initialization of conversions.
The ADC uses an internal voltage reference
for single-ended conversions.
9.3.2.5
The decimation rate (and thereby also the
resolution and time required to complete a
conversion and sample rate) is configurable
from 7-12 bits.
ADC Conversion Results
The digital conversion result is represented in
two's complement form. The result is always
positive. This is because the result is the
difference between ground and input signal
which
is
always
posivitely
signed
(Vconv=Vinp-Vinn, where Vinn=0V). The
maximum value is reached when the input
amplitude is equal VREF, the internal voltage
reference.
9.3.2.6
It is also possible to select a voltage
corresponding to AVDD_SOC/3 as an ADC
input. This input allows the implementation of
e.g. a battery monitor in applications where
this feature is required.
For differential configurations the difference
between the pins is converted and this
difference can be negatively signed. For 12-bit
resolution the digital conversion result is 2047
when the analog input, Vconv, is equal to
VREF, and the conversion result is -2048
when the analog input is equal to –VREF.
ADC Reference Voltage
The positive reference voltage for analog-todigital conversions is an internally generated
1.25V voltage.
9.3.2.7
ADC Conversion Timing
The ADC is run on the 32MHz system clock,
which is divided by 8 to give a 4 MHz clock.
The time required to perform a conversion
depends on the selected decimation rate.
When the decimation rate is set to for instance
128, the decimation filter uses exactly 128 of
the 4 MHz clock periods to calculate the result.
When a conversion is started, the input
multiplexer is allowed 16 4 MHz clock cycles to
settle in case the channel has been changed
since the previous conversion. The 16 clock
cycles settling time applies to all decimation
rates. Thus in general, the conversion time is
given by:
Tconv = (decimation rate + 16) x 0.25 µs.
CC2480 Data Sheet SWRS074
Page 26 of 43
CC2480
9.4
Random Number Generator
9.4.1
Introduction
The random number
following features.
•
generator has
the
The random number generator is a 16-bit
Linear Feedback Shift Register (LFSR) with
polynomial X + X + X + 1 (i.e. CRC16).
It uses different levels of unrolling depending
on the operation it performs. The basic version
(no unrolling) is shown in Figure 8.
16
Generate pseudo-random bytes which can
be read by the external microprocessor.
15
in_bit
+
14
13
12
11
10
9
8
7
6
5
4
15
3
2
2
+
1
0
+
Figure 8: Basic structure of the Random Number Generator
9.4.2
Semi random sequence generation
The operation is to clock the LFSR once (13x
unrolling)
each
time
the
external
microprocessor reads the random value. This
leads to the availability of a fresh pseudorandom byte from the LSB end of the LFSR.
CC2480 Data Sheet SWRS074
Page 27 of 43
CC2480
9.5
USART
The USART is a serial communications
interface that can be operated in either
9.5.1
UART mode
For asynchronous serial interfaces, the UART
mode is provided. In the UART mode the
interface uses a two-wire or four-wire interface
consisting of the pins RXD, TXD and optionally
RTS and CTS. The UART mode of operation
is as follows:
•
Baud rate: 115200.
•
Hardware (RTS/CTS) flow control.
9.5.2
8N1 byte format.
•
DCE signal connection.
The UART mode provides full duplex
asynchronous
transfers,
and
the
synchronization of bits in the receiver does not
interfere with the transmit function. A UART
byte transfer consists of a start bit, eight data
bits, a parity bit, and one stop bit.
•
SPI slave.
•
Clock speed up to 4 MHz.
•
•
Clock polarity 0 and clock phase 0 on
CC2480 .
Bit order: MSB first.
SPI Slave Operation
An SPI byte transfer in slave mode is
controlled by the external system. The data on
the SI input is shifted into the receive register
controlled by the serial clock SCK which is an
9.5.3
•
SPI Mode
This section describes the SPI mode of
operation for synchronous communication. In
SPI mode, the USART communicates with an
external system through a 3-wire or 4-wire
interface. The interface consists of the pins SI,
SO, SCK and SS_N. The SPI mode is as
follows:
9.5.2.1
asynchronous UART mode or in synchronous
SPI mode.
input in slave mode. At the same time the byte
in the transmit register is shifted out onto the
SO output.
SSN Slave Select Pin
When the USART is operating in SPI mode,
configured as an SPI slave, a 4-wire interface
is used with the Slave Select (SSN) pin as an
input to the SPI (edge controlled). At falling
edge of SSN the SPI slave is active and
receives data on the SI input and outputs data
on the SO output. At rising edge of SSN, the
SPI slave is inactive and will not receive data.
Note that the SO output is not tri-stated after
rising edge on SSn. This could be achieved
using an external buffer. Also note that release
of SSn (rising edge) must be aligned to end of
byte recived or sent. If released in a byte the
next received byte will not be received
properly as information about previous byte is
present in SPI system.
CC2480 Data Sheet SWRS074
Page 28 of 43
CC2480
10 Radio
AUTOMATIC GAIN CONTROL
ADC
DIGITAL
DEMODULATOR
ADC
- Digital RSSI
- Gain Control
- Image Suppression
- Channel Filtering
- Demodulation
- Frame
synchronization
LNA
RADIO
REGISTER
BANK
Register bus
FFCTRL
CSMA/CA
STROBE
PROCESSOR
FREQ
SYNTH
0
90
RADIO DATA
INTERFACE
CONTROL
LOGIC
TXRX SWITCH
SFR bus
TX POWER CONTROL
DAC
Power
Control
PA
Σ
DIGITAL
MODULATOR
IRQ
HANDLING
- Data spreading
- Modulation
DAC
Figure 9: CC2480 Radio Module
A simplified block diagram of the IEEE
802.15.4 compliant radio inside CC2480 is
shown in Figure 9. The radio core is based on
the industry leading CC2420 RF transceiver.
CC2480 features a low-IF receiver. The
received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in
quadrature (I and Q) to the intermediate
frequency (IF). At IF (2 MHz), the complex I/Q
signal is filtered and amplified, and then
digitized by the RF receiver ADCs.
The RF signal is amplified in the power
amplifier (PA) and fed to the antenna.
The internal T/R switch circuitry makes the
antenna interface and matching easy. The RF
connection is differential. A balun may be used
for single-ended antennas. The biasing of the
PA and LNA is done by connecting
TXRX_SWITCH to RF_P and RF_N through an
external DC path.
The CC2480 transmitter is based on direct upconversion. The preamble and start of frame
delimiter are generated in hardware. Each
symbol (4 bits) is spread using the IEEE
802.15.4 spreading sequence to 32 chips and
output to the digital-to-analog converters
(DACs).
The frequency synthesizer includes a
completely on-chip LC VCO and a 90 degrees
phase splitter for generating the I and Q LO
signals to the down-conversion mixers in
receive mode and up-conversion mixers in
transmit mode. The VCO operates in the
frequency range 4800 – 4966 MHz, and the
frequency is divided by two when split into I
and Q signals.
An analog low pass filter passes the signal to
the quadrature (I and Q) up-conversion mixers.
An on-chip voltage regulator delivers the
regulated 1.8 V supply voltage.
CC2480 Data Sheet SWRS074
Page 29 of 43
CC2480
10.1 IEEE 802.15.4 Modulation Format
This section is meant as an introduction to the
2.4 GHz direct sequence spread spectrum
(DSSS) RF modulation format defined in IEEE
802.15.4. For a complete description, please
refer to [1].
The modulation and spreading functions are
illustrated at block level in Figure 10 [1]. Each
byte is divided into two symbols, 4 bits each.
The least significant symbol is transmitted first.
Transmitted
bit-stream
(LSB first)
Bit-toSymbol
For multi-byte fields, the least significant byte
is transmitted first.
Each symbol is mapped to one out of 16
pseudo-random sequences, 32 chips each.
The symbol to chip mapping is shown in Table
20. The chip sequence is then transmitted at 2
MChips/s, with the least significant chip (C0)
transmitted first for each symbol.
Symbolto-Chip
O-QPSK
Modulator
Modulated
Signal
Figure 10: Modulation and spreading functions [1]
The modulation format is Offset – Quadrature
Phase Shift Keying (O-QPSK) with half-sine
chip shaping. This is equivalent to MSK
modulation. Each chip is shaped as a half-
sine, transmitted alternately in the I and Q
channels with one half chip period offset. This
is illustrated for the zero-symbol in Figure 11.
Table 20: IEEE 802.15.4 symbol-to-chip mapping [1]
Symbol
Chip sequence (C0, C1, C2, … , C31)
0
1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0
1
1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0
2
0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0
3
0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1
4
0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1
5
0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0
6
1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1
7
1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1
8
1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1
9
1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1
10
0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1
11
0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0
12
0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0
13
0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1
14
1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0
15
1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0
CC2480 Data Sheet SWRS074
Page 30 of 43
CC2480
TC
I-phase
1
Q-phase
0
1
0
1
1
0
1
1
0
1
1
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
1
1
0
1
0
2TC
Figure 11: I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs
10.2 Demodulator, Symbol Synchronizer and Data Decision
The block diagram for the CC2480 demodulator
is shown in Figure 12. Channel filtering and
frequency offset compensation is performed
digitally. The signal level in the channel is
estimated to generate the RSSI level. Data
filtering is also included for enhanced
performance.
Soft decision is used at the chip level, i.e. the
demodulator does not make a decision for
each chip, only for each received symbol. Despreading is performed using over-sampling
symbol correlators. Symbol synchronization is
achieved by a continuous start of frame
delimiter (SFD) search.
With the ±40 ppm frequency accuracy
requirement from [1], a compliant receiver
must be able to compensate for up to 80 ppm
or 200 kHz. The CC2480 demodulator tolerates
up to 300 kHz offset without significant
degradation of the receiver performance.
The CC2480 demodulator also handles symbol
rate errors in excess of 120 ppm without
performance degradation. Resynchronization
is performed continuously to adjust for error in
the incoming symbol rate.
I / Q Analog
IF signal
ADC
Digital
IF Channel
Filtering
Frequency
Offset
Compensation
RSSI
Generator
Digital
Data
Filtering
RSSI
Symbol
Correlators and
Synchronisation
Data
Symbol
Output
Average
Correlation
Value (may be
used for LQI)
Figure 12: Demodulator Simplified Block Diagram
10.3 Frame Format
CC2480 has hardware support for parts of the
IEEE 802.15.4 frame format. This section
gives a brief summary to the IEEE 802.15.4
frame format, and describes how CC2480 is
set up to comply with this.
Figure 13 [1] shows a schematic view of the
IEEE 802.15.4 frame format. Similar figures
describing specific frame formats (data
frames, beacon frames, acknowledgment
frames and MAC command frames) are
included in [1].
CC2480 Data Sheet SWRS074
Page 31 of 43
CC2480
Bytes:
1
0 to 20
2
Frame
Data
Address
Control Field
Sequence
Information
(FCF)
Number
MAC Header (MHR)
MAC
Layer
1
1
Start of frame
Frame
Delimiter
Length
(SFD)
Synchronisation Header
PHY Header
(SHR)
(PHR)
Bytes:
PHY
Layer
n
2
Frame Check
Sequence
(FCS)
MAC Footer
(MFR)
Frame payload
MAC Payload
5 + (0 to 20) + n
MAC Protocol
Data Unit
(MPDU)
PHY Service Data Unit
(PSDU)
4
Preamble
Sequence
11 + (0 to 20) + n
PHY Protocol Data Unit
(PPDU)
Figure 13: Schematic view of the IEEE 802.15.4 Frame Format [1]
10.4 Synchronization header
The synchronization header (SHR) consists of
the preamble sequence followed by the start of
frame delimiter (SFD). In [1], the preamble
sequence is defined to be four bytes of 0x00.
The SFD is one byte, set to 0xA7.
A
synchronization
header
is
transmitted first in all transmit modes.
In receive
sequence
frequency
used
always
mode CC2480 uses the preamble
for symbol synchronization and
offset adjustments. The SFD is
for
byte
synchronization.
10.5 MAC protocol data unit
The FCF, data sequence number and address
information follows the length field as shown in
Figure 13. Together with the MAC data
payload and Frame Check Sequence, they
form the MAC Protocol Data Unit (MPDU).
The format of the FCF is shown in Figure 14.
Please refer to [1] for details.
Bits: 0-2
3
4
5
6
7-9
10-11
12-13
14-15
Frame
Type
Security
Enabled
Frame
Pending
Acknowledge
request
Intra
PAN
Reserved
Destination
addressing
mode
Reserved
Source
addressing
mode
Figure 14: Format of the Frame Control Field (FCF) [1]
10.6 Frame check sequence
The CC2480 hardware implementation is
shown in Figure 15. Please refer to [1] for
further details.
A 2-byte frame check sequence (FCS) follows
the last MAC payload byte as shown in Figure
13. The FCS is calculated over the MPDU, i.e.
the length field is not part of the FCS.
In transmit mode the FCS is appended at the
correct position defined by the length field.
The FCS polynomial is [1]:
x16 + x12 + x5 + 1
The most significant bit in the last byte of each
frame is set high if the CRC of the received
frame is correct and low otherwise.
Data
input
(LSB
first)
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
Figure 15: CC2480 Frame Check Sequence (FCS) hardware implementation [1]
CC2480 Data Sheet SWRS074
Page 32 of 43
CC2480
10.7 Linear IF and AGC Settings
CC2480 is based on a linear IF chain where the
signal amplification is done in an analog VGA
(variable gain amplifier). The gain of the VGA
is digitally controlled.
The AGC (Automatic Gain Control) loop
ensures that the ADC operates inside its
dynamic range by using an analog/digital
feedback loop.
10.8 Clear Channel Assessment
The clear channel assessment signal is based
on the measured RSSI value and a
programmable threshold. The clear channel
assessment function is used to implement the
CSMA-CA functionality specified in [1]. CCA is
valid when the receiver has been enabled for
at least 8 symbol periods.
10.9 VCO and PLL Self-Calibration
10.9.1
VCO
The VCO is completely integrated and
operates at 4800 – 4966 MHz. The VCO
frequency is divided by 2 to generate
10.9.2
frequencies in the desired band (2400-2483.5
MHz).
PLL self-calibration
The VCO's characteristics will vary with
temperature, changes in supply voltages, and
the desired operating frequency.
In order to ensure reliable operation the VCO’s
bias current and tuning range are
automatically calibrated every time the RX
mode or TX mode is enabled.
10.10 Input / Output Matching
The RF input / output is differential (RF_N and
RF_P). In addition there is supply switch output
pin (TXRX_SWITCH) that must have an
external DC path to RF_N and RF_P.
In RX mode the TXRX_SWITCH pin is at
ground and will bias the LNA. In TX mode the
TXRX_SWITCH pin is at supply rail voltage and
will properly bias the internal PA.
The RF output and DC bias can be done using
different topologies. Some are shown in Figure
5 on page 21.
Component values are given in Table 19 on
page 22. If a differential antenna is
implemented, no balun is required.
If a single ended output is required (for a
single ended connector or a single ended
antenna), a balun should be used for optimum
performance.
CC2480 Data Sheet SWRS074
Page 33 of 43
CC2480
10.11 System Considerations and Guidelines
10.11.1
SRD regulations
International regulations and national laws
regulate the use of radio receivers and
transmitters. SRDs (Short Range Devices) for
license free operation are allowed to operate
in the 2.4 GHz band worldwide. The most
10.11.2
Frequency hopping and multi-channel systems
The 2.4 GHz band is shared by many systems
both in industrial, office and home
environments. CC2480 uses direct sequence
spread spectrum (DSSS) as defined by [1] to
10.11.3
important regulations are ETSI EN 300 328
and EN 300 440 (Europe), FCC CFR-47 part
15.247 and 15.249 (USA), and ARIB STD-T66
(Japan).
spread the output power, thereby making the
communication link more robust even in a
noisy environment.
Crystal accuracy and drift
A crystal accuracy of ±40 ppm is required for
compliance with IEEE 802.15.4 [1]. This
accuracy must also take ageing and
temperature drift into consideration.
total frequency offset between the transmitter
and receiver. This could e.g. relax the
accuracy requirement to 60 ppm for each of
the devices.
A crystal with low temperature drift and low
aging could be used without further
compensation. A trimmer capacitor in the
crystal oscillator circuit (in parallel with C191 in
Figure 5) could be used to set the initial
frequency accurately.
Optionally in a star network topology, the fullfunction device (FFD) could be equipped with
a more accurate crystal thereby relaxing the
requirement on the reduced-function device
(RFD). This can make sense in systems where
the reduced-function devices ship in higher
volumes than the full-function devices.
For non-IEEE 802.15.4 systems, the robust
demodulator in CC2480 allows up to 140 ppm
10.11.4
Communication robustness
CC2480 provides very good adjacent, alternate
and co channel rejection, image frequency
suppression and blocking properties. The
CC2480 performance is significantly better than
the requirements imposed by [1]. These are
10.11.5
Communication security
The hardware encryption and authentication
CC2480 enable secure
operations
in
communication, which is required for many
applications. Security operations require a lot
10.11.6
of data processing, which is costly in an 8-bit
microcontroller system. The hardware support
within CC2480 enables a high level of security
with minimum CPU processing requirements.
Low cost systems
As the CC2480 provides 250 kbps multichannel performance without any external
filters, a very low cost system can be made
(e.g. two layer PCB with single-sided
component mounting).
10.11.7
highly important parameters for reliable
operation in the 2.4 GHz band, since an
increasing number of devices/systems are
using this license free frequency band.
A differential antenna will eliminate the need
for a balun, and the DC biasing can be
achieved in the antenna topology.
Battery operated systems
In low power applications, the CC2480 should
be placed in the low-power modes PM2 or
PM3 when not active. Ultra low power
consumption may be achieved since the
voltage regulators are turned off.
CC2480 Data Sheet SWRS074
Page 34 of 43
CC2480
10.12 PCB Layout Recommendation
In the Texas Instruments reference design, the
top layer is used for signal routing, and the
open areas are filled with metallization
connected to ground using several vias. The
area under the chip is used for grounding and
must be well connected to the ground plane
with several vias.
The ground pins should be connected to
ground as close as possible to the package
pin using individual vias. The de-coupling
capacitors should also be placed as close as
possible to the supply pins and connected to
the ground plane by separate vias. Supply
power filtering is very important.
The external components should be as small
as possible (0402 is recommended) and
surface mount devices must be used.
If using any external high-speed digital
devices, caution should be used when placing
these in order to avoid interference with the
RF circuitry.
It is strongly advised that this reference layout
is followed very closely in order to obtain the
best performance.
The schematic, BOM and layout Gerber files
for the reference designs are all available from
the TI website.
10.13 Antenna Considerations
CC2480 can be used together with various
types of antennas. A differential antenna like a
dipole would be the easiest to interface not
needing a balun (balanced to un-balanced
transformation network).
The length of the λ/2-dipole antenna is given
by:
L = 14250 / f
where f is in MHz, giving the length in cm. An
antenna for 2450 MHz should be 5.8 cm. Each
arm is therefore 2.9 cm.
Other commonly used antennas for shortrange communication are monopole, helical
and loop antennas. The single-ended
monopole and helical would require a balun
network between the differential output and
the antenna.
Monopole antennas are resonant antennas
with a length corresponding to one quarter of
the electrical wavelength (λ/4). They are very
easy to design and can be implemented
simply as a “piece of wire” or even integrated
into the PCB.
the antenna. Many vendors offer
antennas intended for PCB mounting.
such
Helical antennas can be thought of as a
combination of a monopole and a loop
antenna. They are a good compromise in size
critical applications. Helical antennas tend to
be more difficult to optimize than the simple
monopole.
Loop antennas are easy to integrate into the
PCB, but are less effective due to difficult
impedance matching because of their very low
radiation resistance.
For low power applications the differential
antenna is recommended giving the best
range and because of its simplicity.
The antenna should be connected as close as
possible to the IC. If the antenna is located
away from the RF pins the antenna should be
matched to the feeding transmission line
(50Ω).
The length of the λ/4-monopole antenna is
given by:
L = 7125 / f
where f is in MHz, giving the length in cm. An
antenna for 2450 MHz should be 2.9 cm.
Non-resonant monopole antennas shorter than
λ/4 can also be used, but at the expense of
range. In size and cost critical applications
such an antenna may very well be integrated
into the PCB.
Enclosing the antenna in high dielectric
constant material reduces the overall size of
CC2480 Data Sheet SWRS074
Page 35 of 43
CC2480
11 Voltage Regulators
The CC2480 includes two low drop-out voltage
regulators. These are used to provide a 1.8 V
power supply to the CC2480 analog and digital
power supplies.
Note: It is recommended that the voltage
regulators are not used to provide power to
external circuits. This is because of limited
power sourcing capability and due to noise
considerations. External circuitry can be
powered if they can be used when internal
power consumption is low and can be set I PD
mode when internal power consumption I high.
The analog voltage regulator input pin
AVDD_RREG is to be connected to the
unregulated 2.0 to 3.6 V power supply. The
regulated 1.8 V voltage output to the analog
parts, is available on the RREG_OUT pin. The
digital regulator input pin AVDD_DREG is also
to be connected to the unregulated 2.0 to 3.6
V power supply. The output of the digital
regulator is connected internally within the
CC2480 to the digital power supply.
The voltage regulators require external
components as described in section 8 on page
20.
11.1 Voltage Regulators Power-on
When the analog voltage regulator is poweredon before use of the radio, there will be a
delay before the regulator is enabled.
The digital voltage regulator is disabled when
the CC2480 is placed in low power modes to
reduce power consumption.
CC2480 Data Sheet SWRS074
Page 36 of 43
CC2480
12 Package Description (QLP 48)
All dimensions are in millimeters, angles in degrees. NOTE: The CC2480 is available in RoHS leadfree package only. Compliant with JEDEC MS-020.
Table 21: Package dimensions
Quad Leadless Package (QLP)
QLP 48
Min
Max
D
D1
E
E1
6.9
6.65
6.9
6.65
7.0
6.75
7.0
6.75
7.1
6.85
7.1
6.85
e
b
L
D2
E2
0.18
0.3
5.05
5.05
0.4
5.10
5.10
0.5
5.15
5.15
0.5
0.30
The overall package height is 0.85 +/- 0.05
All dimensions in mm
Figure 16: Package dimensions drawing
CC2480 Data Sheet SWRS074
Page 37 of 43
CC2480
12.1 Recommended PCB layout for package (QLP 48)
Figure 17: Recommended PCB layout for QLP 48 package
Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes
distributed symmetrically in the ground pad under the package. See also the CC2480 EM reference
design
12.2 Package thermal properties
Table 22: Thermal properties of QLP 48 package
Thermal resistance
Air velocity [m/s]
0
Rth,j-a [K/W]
25.6
12.3 Soldering information
The recommendations for lead-free solder reflow in IPC/JEDEC J-STD-020C should be followed.
12.4 Tray specification
Table 23: Tray specification
Tray Specification
Package
Tray Width
Tray Height
Tray Length
Units per Tray
QLP 48
135.9mm ± 0.25mm
7.62mm ± 0.13mm
322.6mm ± 0.25mm
260
12.5 Carrier tape and reel specification
Carrier tape and reel is in accordance with EIA Specification 481.
CC2480 Data Sheet SWRS074
Page 38 of 43
CC2480
Table 24: Carrier tape and reel specification
Tape and Reel Specification
Package
Tape Width
Component
Pitch
Hole
Pitch
Reel
Diameter
Units per Reel
QLP 48
16mm
12mm
4mm
13 inches
2500
CC2480 Data Sheet SWRS074
Page 39 of 43
CC2480
13 Ordering Information
Table 25: Ordering Information
Ordering part number
Description
MOQ
CC2480A1RTC
CC2480, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per
tray, ZigBee 2006 Network Processor.
260
CC2480A1RTCR
CC2480, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs
per reel, ZigBee 2006 Network Processor.
2,500
eZ430-RF2480
CC2480 Demonstration Board based on the eZ430-RF platform
1
MOQ = Minimum Order Quantity
T&R = tape and reel
CC2480 Data Sheet SWRS074
Page 40 of 43
CC2480
14 General Information
14.1 Document History
Table 26: Document History
Revision
Date
Description/Changes
1.0
2008-04-02
First data sheet for released product.
15 Address Information
Texas Instruments Norway AS
Gaustadalléen 21
N-0349 Oslo
NORWAY
Tel: +47 22 95 85 44
Fax: +47 22 95 85 46
Web site: http://www.ti.com/lpw
16 TI Worldwide Technical Support
Internet
TI Semiconductor Product Information Center Home Page:
TI Semiconductor KnowledgeBase Home Page:
support.ti.com
support.ti.com/sc/knowledgebase
Product Information Centers
Americas
Phone:
Fax:
Internet/Email:
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CC2480 Data Sheet SWRS074
Page 41 of 43
CC2480
Japan
Fax
Internet/Email
International
Domestic
International
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0120-81-0036
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CC2480 Data Sheet SWRS074
Page 42 of 43
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CC2480A1RTCR
Package Package Pins
Type Drawing
VQFN
RTC
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
7.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.4
1.6
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Dec-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CC2480A1RTCR
VQFN
RTC
48
2500
378.0
70.0
346.0
Pack Materials-Page 2
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