NWK914D
NWK914D
PHY/PMD High Speed Copper Media Transceiver
Preliminary Information
MAC or
Repeater
Controller
IC
MII
Interface
TDAT4
52
51
50
49
48
47
46
45
44
43
42
41
40
N/C
N/C
RXPLLGND
LFRB
LFRA
RXPLLV CC
RXVCC
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
TTLGND
TEST
TESTIP
N10/100
LBEN
TDLV CC
TXOE
TXPLLV CC
LFTA
LFTB
TXPLLGND
BGAPGND
SUBGND
14
15
16
17
18
19
20
21
22
23
24
25
26
FEATURES
■ Compatible with IEEE-802.3 Standards
■ Operates over 100 Meters of STP and Category 5
UTP cable
■ Five Bit TTL Level Symbol Interface
■ Integrated Clock and Data Recovery
■ Supports Full-duplex Operation
■ Integral 10 Mb/s Buffer for Dual 10 Mb/s & 100 Mb/s
Applications
■ Adaptive Equalization
■ 25MHz to 125MHz Transmit Clock Multiplier
■ Programmable TX Output Current
■ Base Line Wander Correction
TTLGND
N/C
N/C
RXC
SDT
RDLV CC
RXGND
RXIP
RXIN
RXVCC 1
EQSEL
10TXIN
10TXIP
TXVCC
TXON
TXOP
TXGND
TXREF
BGAPVCC
The NWK914D is a Physical Layer device designed for
use in 100BASE-TX applications. The NWK914D has
integrated the 100mb/s transceiver, clock and data recovery
and NRZI conversion circuitry. It is designed for use in cost
effective NIC adapter cards and 100BASE-TX repeater and
switch applications.
The device connects through a 5 bit symbol interface
directly with any MAC controller that includes the PCS layer,
resulting in a simple and cost effective solution. It will also
interface with a PCS device such as the NWK935 to form a
complete 100BASE-TX Physical Layer for connection to the
IEEE 802.3 standard MII interface.
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
TXC
TTLVCC
REFCLK
TDAT0
TDAT1
TDAT2
TDAT3
DS4829 - 1.1 December 1997
GP52
Fig.1 Pin connections - top view
■ Single +5V supply
■ 52 Pin PQFP package
ORDERING INFORMATION
NWK914D/CG/GP1N
Symbol
Interface
NWK935
100 PCS
NWK914D
Isolation
Magnetics
RJ-45
Fig.2 Simplified system diagram
1
NWK914D
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Operation at absolute maximum ratings is not implied.
Exposure to stresses outside those listed could cause
permanent damage to the device.
DC Supply voltage (VCC)
Storage temperature (tst)
ESD
DC supply voltages (VCC)
+5V ±5%
Operating temperature (TA) 0°C to +70°C (+25°C typ.)
750mW (typ.)
Power dissipation (P D)
-0.5 to +7V
-65 to +150°C
2kV HBM
ELECTRICAL CHARACTERISTICS
Recommended operating conditions apply except where stated.
Symbol
Min.
Value
Typ.
Max.
Units
Total VCC supply current
TTL high level I/P voltage
TTL low level I/P voltage
TTL high level I/P current
TTL low level I/P current
ICC
VIH
VIL
IIH
IIL
2
-
150
-
0.8
20
–400
mA
V
V
µA
µA
EQSEL high level I/P voltage
EQSEL low level I/P voltage
EQSEL floating level I/P
VIH
VIL
VIZ
4.2
-
VCC/2
0.8
-
V
V
V
EQSEL high level I/P current
EQSEL low level I/P current
IIH
IIL
-
-
1400
–1400
µA
µA
VIH = VCC
VIL = 0V
TTL high level O/P voltage
TTL low level O/P voltage
VOH
VOL
2.4
-
-
0.5
V
V
IOH = 20µA
IOL = 4mA
TTL high level O/P current
TTL low level O/P current
IOH
IOL
-
-
–200
4
µA
mA
Transmit O/P current
pins TXOP, TXON
-
40
-
mA
Differential RX I/P
signal voltage
-
1.4
-
Vp-p
RX I/P common mode voltage
-
VCC/2
-
V
RX I/Ps floating
-
24
-
kΩ
-
50
-
%
wrt normalized output of
equalizer
-
3.8
-
V
kHz
Characteristic
Conditions
DC characteristics
RX I/P impedance
Signal detect threshold
VTH
Low voltage shutdown
PLL characteristics
3dB bandwidth
-
50
-
Damping factor
-
2
-
Peaking
-
-
.005
Overshoot
-
-
5
%
Static error
-
±0.5
-
ns
Jitter
-
-
0.5
ns
-
125
-
dB
VCO characteristics
Centre frequency
Deviation
Gain
2
@125MHz
-
±40
-
MHz
-
70
-
MHz/V
MHz
device only
VIH = VCC
VIL = 0.4V
RREF = 1300Ω
100Mb/s data
measured on device pins
100Mb/s data, 0mCable
NWK914D
TTLVCC
LFTA
LFTB
TIMES FIVE
CLOCK
MULTIPLIER
REFCLK
TXC
RXPLLVCC TXPLLVCC
125
MHz
TXOE
TXREF
10TXIN
TDLVCC
10TX IP
N10/100
RDLVCC
CURRENT
REFERENCE
LOW VOLTAGE
SHUT DOWN
10
Mb/s
TXVCC
TDAT0
TDAT1
SHIFTER &
TDAT2
NRZ to NRZI
B AND GAP
VOLTAGE
REFERENCE
TDAT3
NRZI
to
MLT-3
TDAT4
BGAPVCC
DIVIDE
CLOCK
by FIVE
BGAPGND
TXOP
100
Mb/s
TXON
TXGND
CLOCK
RECOVERY
PLL,125MHZ
TTL
RXC
LBEN
RDAT0
RDAT1
SHIFTER &
RDAT2
COMPARATORS
MLT-3 to NRZI
NRZI to NRZ
ADAPTIVE
EQUALIZER
3
LEVEL
EQSEL
RXIP
RDAT3
RXIN
RDAT4
RXVCC 2
TTL
SIGNAL
DETECT
RXV CC1
RXGND
SUBGND
TTLGND1 TTLGND2
LFRA
LFRB
SDT
RXPLLGND TXPLLGND TESTIP
TEST
Fig.3 System block diagram
FUNCTIONAL DESCRIPTION
The functional blocks within the device are shown in Fig. 3.
These are described below:-
Transmit Section
Times Five Clock Multiplier 25MHz to 125MHz
This circuit consists of a phase lock loop (PLL) that is
operating at 125MHz, centre frequency. The 125MHz is
divided by 5 to produce a 25MHz clock which is phase
compared with a 25MHz crystal clock reference frequency
which is input on pin REFCLK. The 25MHz clock (pin TXC)
is then sent to the PCS layer to clock in in the 5 bit nibble
data. Pins LFTA and LFTB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
A control current is derived from the clock multiplier and
is used by the receive clock recovery circuit to centre the
PLL when no input data is present.
Five Bit Nibble to 125MHz Shifter
Data is input to the transmit side in 5 bit wide parallel
form on pins TDAT0 through TDAT4. This NRZ data is
clocked in on the positive edge of the 25MHz clock pin TXC.
The parallel data is first loaded into a 5 bit wide register prior
to being loaded into a 5 bit PISO where it is converted into
a serial data stream. The last stage of the shifter incorporates
a converter to change the data from NRZ to NRZI.
NRZ to MLT3 Encoder
The serial data from the shifter then passes through an
encoder which converts the NRZI binary data into the three
level MLT-3 format for transmission by the 'TXO' outputs.
Transmit Line Drivers
There are two on-chip Line Drivers both of which share
the output pins TXOP and TXON. The N10/100 pin is used
to control which driver is active and allowed to drive the line.
When held high the MLT-3 data is output by the 100Mb/s
driver. This driver consists of differential current source
outputs with programmable sink capability, designed to
drive a nominal output impedance of 50Ω.
Output current is set by the value of an external resistor
(R REF) between pin 'TXREF' and 'TXGND'.
This resistor defines an internal reference current derived
from an on-chip bandgap reference.
Final output current at the 'TXO' outputs is a multiple of
this current and is defined as:I
TXO(mA)
= 52/RREF(kΩ)
Transition times of the 'TXO' outputs are matched and
internally limited to approx. 2.5ns to reduce EMI emissions.
3
NWK914D
When N10/100 is held low the 10Mb/s driver is selected.
This 10Mb/s driver consists of a differential analog buffer
designed to take a fully cable conditioned 10Mb/s signal
from the filter output of existing 10BASE-T electronics. The
10BASE-T signal is input on pins 10TXIN and 10TXIP. The
output current of the buffer is determined by the same
external RREF resistor on pin TXREF as used for the 100Mb/
s driver.
The unselected driver is switched to a tristated power
save mode. A low voltage shutdown circuit turns off both TX
drivers when V CC voltage falls to a level below the specified
minimum.
Base Line Wander Correction
MLT-3 codes have significant low frequency components
in their spectrum which are not transmitted through the
transformers that couple the line to the board. This results in
'Base Line Wander', which can significantly reduce the
noise immunity of the receiver.
The purpose ot the correction circuit is to restore these
low frequency components through the use of a feedback
arrangement. The circuit will also correct any DC offset that
may exist on the receive signal.
Signal Detector
When operating in single 100Mb/s applications a 1:1
turn ratio magnetics will be used and therefore to attain the
desired line driving current of 40mA out of the secondary a
TXO output drive of 40mA is required. Using the above
formula it will be found that 1.3Ω is the nearest prefered
value to that required to give the 40mA.
A signal detect circuit is provided which continuously
monitors the amplitude of the input signal being received on
pins RXIP and RXIN. After the input signal reaches the
specified level which the equalizer can correctly equalize,
SDT is asserted high. Conversely if the signal level falls
below a limit for reliable operation then SDT will go low.
In the case of dual 10Mb/s and 100Mb/s applications a
2:1 turn ratio magnetics is recommended. The use of 2:1
magnetics enables a greater efficiency to be gained from
the 10Mb/s driver by using a lower output current. At the
same time this lower current is also true of the 100Mb/s
output where now only a 20mA drive is required. An RREF
value of 2.6KΩ is used to set this current. Internal current
ratioing within the device will ensure that the correct drive
current is chosen depending upon whether the drives are in
10Mb/s or 100Mb/s mode as selected by pin N10/100.
Comparators MLT-3 to NRZ Decoder
The RREF value can be adjusted to compensate for
different magnetics and board layouts. The object is to
achieve an output level of 2V p-p measured at the RJ45
socket in compliance with 802.3.
When the TXOE pin is held low the TXdrivers are tristated regardless of the mode selected by the N10/100 pin.
Receiver Section
The equalized MLT-3 data is then passed to a set of
window comparators which are used to determine the signal
level. The comparator outputs are OR’ed together to
reconstitute the NRZI data.
PLL Clock Recovery
This function consists of a 125MHz PLL that is locked to
the incoming data stream. The PLL is first centred to the
transmit clock multiplier using an internal analog reference
signal. Once a valid input signal is present, the PLL will lock
to, and thus extract the clock from, the incoming data
stream. Pins LFRA and LFRB are provided to set the VCO
characteristics. The recommended loop filter components
are shown in Fig.6.
125MHz Shifter to Parallel Data
Equalizer
The 125Mb/s serial data stream with an accompanying
phase related 125MHz clock is output from the PLL.
The equalizer circuit is necessary to compensate for
signal degradation due to cable losses, however overequalization must be avoided to prevent excessive overshoots
resulting in errors during the reception of MLT-3 data. Three
operating modes are therefore provided.
This data stream is clocked into the serial to parallel
register using the 125MHz clock. This data is then latched
prior to being clocked out on pins RDAT0 to RDAT4. A
25MHz clock, derived from the 125MHz PLL by a divide by
5, is used to clock the parallel data and is output to pin RXC.
These three operating modes are controlled by the state
of tristate input 'EQSEL' and are described below:-
Loopback Logic
1) Auto Equalization ('EQSEL' floating)
Fully automatic equalization is achieved through the
use of a feedback loop driven by a control signal derived
from the signal amplitude. This provides adaptive control
and prevents over-modulation of the signal when short
cable lengths are used.
2) Full Equalization ('EQSEL' low)
In this mode, full equalization is applied to the input
signal irrespective of amplitude.
3) No Equalization ('EQSEL high)
The equalization circuit is disabled completely during
this mode.
4
Pin ‘LBEN’ controls loopback operation. A low level on
this pin defines normal operation, a high level defines
loopback mode. In loopback mode, the transmit data is
internally routed to the receive circuitry, SDT is forced high
and the TXOP and TXON outputs are disabled.
Test Pins and No-Connects
Two pins are provided on the product to aid testing in
production. These pins TEST(38), and TESTIP(37) must be
left unconnected for normal operation in application circuits.
Additionally, there are four No-Connect pins (2,3,7,8)
which also mustt be left unconnected for normal operation.
NWK914D
AC CHARACTERISTICS
Recommended operating conditions apply except where stated.
Waveform
Timing
Characteristic
Min.
Value
Typ.
Max.
-
2.5
-
ns
Units
Conditions
AC characteristics
100Mb/s TX driver outputs rise/fall times
pins TXOP, TXON
REFCLK frequency
1
-
25
-
MHz
REFCLK tolerance
2
-
100
-
ppm
REFCLK M/S ratio
3
40:60
-
60:40
%
REFCLK to TXC
propagation delay
4
5
-
13
ns
TDAT0 → 4 to TXC setup time
5
12
-
-
ns
TDAT0 → 4 to TXC hold time
6
0
-
-
ns
RDAT0 → 4 valid to RXC +Ve edge
7
10
-
-
ns
RXC to RDAT0 → 4 invalid
8
10
-
-
ns
RXC M/S ratio
9
45:55
-
55:45
%
5
-
15
ns
REFCLK to SDT transition
100Ω differential load
measured at RJ45
Tx PLL in lock
NOTE: Conditions for AC Characteristics:
All AC measurementsare made at aVth + 1.5V and with TTL output loaded with 25pf
4
REFCLK
1
2
3
TXC
5
TDAT
0→4
VALID
DATA
6
VALID
DATA
TXO
bit 4
bit 3
bit 2
bit 1
bit 0
bit 4
Fig.4 Transmit timing waveform
9
RXC
5
RDAT
0→4
8
VALID
DATA
Fig.5 Receive timing waveform
5
NWK914D
Pin Name
Pin Type
Pin Number
SYMBOL Interface
RXC
TTLOP
4
SDT
TTLOP
5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TXC
TTLIP
TTLIP
TTLIP
TTLIP
TTLIP
TTLOP
40
41
42
43
44
47
RDAT0
RDAT1
RDAT2
RDAT3
RDAT4
TTLOP
TTLOP
TTLOP
TTLOP
TTLOP
48
49
50
51
52
25MHz recovered receive clock. This is aligned with and used to clock
out the 5 bit parallel receive data to the PCS layer.
Signal detect output. This output is high when an input signal of sufficient
amplitude is detected on the RXI inputs.
The 100BASE-TX transmit input bit 4
The 100BASE-TX transmit input bit 3
The 100BASE-TX transmit input bit 2
The 100BASE-TX transmit input bit 1
The 100BASE-TX transmit input bit 0
25MHz transmit clock. This is aligned with and used to clock in the 5 bit parallel
100BASE-TX transmit data from the PCS layer.
The 100BASE-TX receive output bit 0
The 100BASE-TX receive output bit 1
The 100BASE-TX receive output bit 2
The 100BASE-TX receive output bit 3
The 100BASE-TX receive output bit 4
analog input
analog input
analog output
analog output
15
16
22
23
+ Differential receive signal input from magnetics
– Differential receive signal input from magnetics
– Differential transmit line driver outputs to magnetics
+ Differential transmit line driver outputs to magnetics
10BASE-T Interface
10TXIN
analog input
10TXIP
analog input
19
20
The filtered 10BASE-T transmit input (–)
The filtered 10BASE-T transmit input (+)
Control Pins
N10/100
TTLIP
36
3 level IP
18
LBEN
TTLIP
35
TXOE
TTLIP
33
test
test
37
38
2,3,7,8
10/100 mode selection. A low selects the 10BASE-T mode and enables the
data on pins 10TXIP/N to be outut on the TXOP/N pins. A high selects the
100BASE-TX mode, enabling the 100Mb/s drivers.
Mode select input for equalizer. Normally this pin is left unconnected (floating) for
auto-eq. mode. High selects minimum equalization. Low selects full equalization.
Loopback enable input. A high on this pin selects the loopback mode and low selects
normal operation.
Transmit output enable. A high on this pin selects normal operation. A low on this
pin puts both of the TX drivers in tri-state mode.
Test pin. This pin must be left unconnected for proper operation.
Test pin. This pin must be left unconnected for proper operation.
No connection. This pin must be left unconnected for proper operation.
Network Interface
RXIP
RXIN
TXON
TXOP
EQSEL
TESTIP
TEST
N/C
Component Connections
REFCLK
TTLIP
TXREF
analog input
LFRB
analog
LFRA
analog
LFTB
analog
LFTA
analog
Power
TTLGND
RDLVCC
RXPLLGND
RXPLLVCC
RXVCC2
RXGND
RXVCC1
TXVCC
TXGND
RXVCC
SUBGND
BGAPGND
TXPLLGND
TXPLLVCC
TDLVCC
TXLVCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
45
25
10
11
30
31
1,39
6
9
12
13
14
17
21
24
26
27
28
29
32
34
46
Pin Description
25MHz clock input. An external 25MHz oscillator is input to this pin.
TXOP/N line driver current setting pin. Connects to TXGND through a resistor.
Differential loop filter pin for receive PLL (see fig.6)
Differential loop filter pin for receive PLL (see fig.6)
Differential loop filter pin for transmit clock PLL (see fig.6)
Differential loop filter pin for transmit clock PLL (see fig.6)
GND for TTL logic I/Os
+5V supply to receive logic
GND to receive PLL
+5V supply to receive PLL
+5V supply to adaptive equalizer and QFB circuits
GND to to adaptive equalizer and QFB circuits
+5V supply to MLT-3 to NRZI converter
+5V supply to transmit line driver circuits
GND to transmit line driver circuits
+5V supply to on-chip bandgap reference
Chip substrate GND connection
GND to on-chip bandgap reference
GND to to transmit clock-multiplier PLL
+5V supply to transmit clock-multiplier PLL
+5V supply to transmit logic
+5V supply to TTL logic I/Os
Table 1: Pin descriptions
6
NWK914D
1KΩ
Xtal Osc.
See Table 2 for
these resistor values
.033µF
C2
R1
100pF
TxVcc
R2
C1
R5
LFTB TXREF
LFTA
REFCLK
R6
TXGND
TXOP
CT
0.1µF
PCS
or
MAC
(with
embedded
PCS)
TDAT0-4
5
C4
TXON
NWK914D
TXC
15Ω
RXIP
RXC
R7
R9
5
R8
RXIN
RDAT0-4
LFRA
68Ω
1:1
M
A
G
N
E
T
I
C
S
RJ45
15Ω
LFRB
C3
R3
.01µF
6.2KΩ
Fig.6 Simplified 100BASE-TX system block diagram showing NWK914D external components
REF.
VALUE
TOL.
FUNC.
100pF
0.033µF
.01µF
20%
20%
20%
loop fltr
loop fltr
loop fltr
R1
R2
R3
R5,R6
R7,R8
R9
1KΩ
1300Ω
6.2KΩ
50Ω
15Ω
68Ω
1%
1%
1%
1%
1%
1%
loop fltr
tx ref
loop fltr
xmit
rcv pad
rcv pad
R2
R5,R6
2.6KΩ
200Ω
1%
1%
tx ref
xmit
C1
C2
C3
CT on transformer connects directly to
TX VCC with C4 omitted
NOTES
The NWK914D requires a number of external components
for the device to function correctly and these are shown in
the simplified 100BASE-TX application circuit in Fig.6 and
the component value information given in Table 2.
1:1 magnetics
1:1 magnetics
2:1 magnetics
2:1 magnetics
2:1 magnetics
Table 2: External components
Base Line Wander Correction
TXREF resistor with 1:1 magnetics
EXTERNAL REQUIREMENTS
Note that the values of R2, R5 and R6 vary depending
upon application. When using 1:1 magnetics, use the values
shown in the middle of Table 2 with note "1:1 magnetics".
When using 2:1 magnetics use the values shown in the last
two lines of Table 2. Please refer to the Transmit Line Driver
section on pages 3-4 for more information on these values.
For more detailed Application information please contact
your local Sales Office.
GLOSSARY OF TERMS AND ABREVIATIONS
MAC
MLT-3
NRZ
NRZI
PCS
PHY
PLL
PMD
UTP
RX
STP
TX
UTP
VCO
Media Access Control
Multi Level Transmit -3 levels
Non Return To Zero
Non Return to Zero Inverse
Physical Coding Sublayer
PHYsical Layer
Phase Locked Loop
Physical Media Dependent
Unshielded Twisted Pair
Receive
Shielded Twisted Pair
Transmit
Unshielded Twisted Pair
Voltage Controlled Oscillator
NWK914B
NWK914S
NWK914D
620Ω
improved to 100m
680Ω
improved to 100m
1300Ω
Table 3: Differences between NWK914B, NWK914S and NWK914D
7
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