CS42324
10-In, 6-Out, 2 Vrms Audio CODEC
D/A Features
A/D Features
Dual 24-bit Stereo DACs
Multi-bit Delta-Sigma Modulator
Multi-bit Delta-Sigma Modulator
100 dB Dynamic Range (A-Wtd)
24-bit Conversion
-90 dB THD+N
Up to 96 kHz Sampling Rates
Integrated Line Driver
–
–
95 dB Dynamic Range (A-Wtd)
2 Vrms Output
Single-Ended Outputs
-88 dB THD+N
Up to 96 kHz Sampling Rates
Stereo 5:1 Input Multiplexer
Stereo 7:1 Output Multiplexer
Volume Control with Soft Ramp
–
–
0.5 dB Step Size
Zero Crossing Click-Free Transitions
Selectable Serial Audio Interface Formats
–
–
Left- or Right-Justified, Up to 24-bit
I²S Up to 24-bit
Selectable 50/15 μs De-Emphasis
Digital Volume Control with Soft Ramp
–
0.5 dB Step Size
Selectable Serial Audio Interface Formats
–
Left-Justified
–
I²S
Internal Analog Mute
High-Pass Filter or DC Offset Calibration
Control Output for External Muting
See System Features, General Description, and Ordering information on page 2.
Popguard® Technology
3.3 V
PCM Serial
Interface
Serial Audio
Inputs
Level
Translator
1.8 V to 3.3 V
Volume
Control/Mixer
Multibit
ΔΣ Modulator
Volume
Control/Mixer
Multibit
ΔΣ Modulator
3.3 V
Stereo DAC
Serial Audio
Output
Register Configuration
Volume
Control/High
Pass Filter
Advance Product Information
http://www.cirrus.com
Mute
Stereo Output 1
7:1
MUX
Stereo DAC
Mute
Stereo Output 2
7:1
MUX
Mute
Stereo Output 3
5
5
PCM Serial
Interface
Reset
Level Translator
ADC Overflow
Level
Translator
Interrupt
7:1
MUX
5
2
SPI & I C
Control Data
9 V to12 V
Low-Latency
Decimation
Filter
Internal Voltage
Reference
Multibit
Oversampling
Stereo ADC
Mute 1
Mute 2
Mute 3
Mute
Control
Stereo Input 1
Stereo Input 2
Stereo Input 3
Stereo Input 4
Stereo Input 5
5:1
MUX
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
JANUARY '08
DS721A6
CS42324
System Features
General Description
Direct Interface with 1.8 V to 3.3 V Logic Levels
The CS42324 is a highly integrated stereo audio
CODEC. The CS42324 performs stereo analog-todigital (A/D) and up to four channels of digital-to-analog
(D/A) conversion of up to 24-bit serial values at sample
rates up to 96 kHz.
Supports Asynchronous Serial Port Operation
–
Two Independent Clock Domains
–
ADC, DAC1, and DAC2 can be
Independently Assigned to the Two Clock
Domains
–
Each Serial Port Supports Master or Slave
Operation
Internal Digital Loopback
+3.3 V Analog Power Supply
+3.3 V Digital Power Supply
+9 V to +12 V High-Voltage Power Supply
Hardware or Software Mode Configuration
–
Supports I²C® and SPI™ Software Interface
A 5:1 stereo input multiplexer is included for selecting
between line-level inputs. The output of the input multiplexer is followed by an advanced 3rd-order, multi-bit
delta-sigma modulator and digital filtering/decimation.
Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 96 kHz, in either Slave or
Master Mode.
The D/A converter is based on a 5th-order multi-bit delta-sigma modulator with an ultra-linear low-pass filter
and offers a volume control that operates with a 0.5 dB
step size. It incorporates selectable soft ramp and zero
crossing transition functions to eliminate clicks and
pops.
An integrated 7:1 stereo output multiplexer on each of
the three stereo 2 Vrms line-level outputs is used to select any of the 5 stereo analog inputs, for analog bypass
support, or the outputs of the 2 internal DACs. Each
2 Vrms output can be muted with the selectable analog
mute function.
Standard 50/15 μs de-emphasis is available for a
44.1 kHz sample rate for compatibility with digital audio
programs mastered using the 50/15 μs pre-emphasis
technique.
Integrated digital level translators allow easy interfacing
between the CS42324 and other devices operating over
a wide range of logic levels.
The CS42324 is available in a 48-pin LQFP package in
Commercial (-40°C to +85°C) and Automotive (-40°C to
+105°C) grades. The CDB42324 Customer Demonstration board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
information” on page 71 for complete details.
2
DS721A6
CS42324
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8
1.1 Software Mode ................................................................................................................................. 8
1.2 Hardware Mode .............................................................................................................................. 10
1.3 Digital I/O Pin Characteristics ......................................................................................................... 12
2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13
RECOMMENDED OPERATING CONDITIONS ................................................................................... 13
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 13
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ........................................................... 14
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 15
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 16
ADC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ........................................................... 17
ADC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ............................................................ 18
ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 19
ANALOG PASS-THRU CHARACTERISTICS ...................................................................................... 20
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 21
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 21
SWITCHING CHARACTERISTICS - SERIAL AUDIO .......................................................................... 22
SWITCHING CHARACTERISTICS - SERIAL AUDIO (CONT.) ........................................................... 23
SWITCHING CHARACTERISTICS - SOFTWARE MODE - I²C FORMAT ........................................... 24
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT .......................................... 25
3. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 26
4. APPLICATIONS ................................................................................................................................... 28
4.1 System Clocking ............................................................................................................................. 28
4.1.1 Master Clock ......................................................................................................................... 28
4.1.2 Synchronous / Asynchronous Mode ...................................................................................... 29
4.2 Serial Port Operation ...................................................................................................................... 29
4.2.1 Master Mode ......................................................................................................................... 30
4.2.2 Slave Mode ........................................................................................................................... 30
4.2.3 ADC, DAC1, and DAC2 clock selection ................................................................................ 31
4.2.4 High-Impedance Digital Output ............................................................................................. 31
4.2.5 Digital Interface Formats ....................................................................................................... 32
4.2.6 Synchronization of Multiple Devices ...................................................................................... 32
4.3 Analog-to-Digital Data Path ............................................................................................................ 33
4.3.1 ADC Analog Input Multiplexer ............................................................................................... 33
4.3.2 ADC Description .................................................................................................................... 33
4.3.3 High-Pass Filter and DC Offset Calibration ........................................................................... 34
4.3.4 Digital Attenuation Control ..................................................................................................... 34
4.4 Digital-to-Analog Data Path ............................................................................................................ 34
4.4.1 Digital Volume Control ........................................................................................................... 34
4.4.2 Mono Channel Mixer ............................................................................................................. 34
4.4.3 De-Emphasis Filter ................................................................................................................ 35
4.4.4 Internal Digital Loopback ....................................................................................................... 35
4.4.5 DAC Description .................................................................................................................... 35
4.4.6 Analog Output Multiplexer ..................................................................................................... 36
4.4.7 Output Transient Control ....................................................................................................... 36
4.4.8 Mute Control .......................................................................................................................... 37
4.5 Initialization ..................................................................................................................................... 37
4.5.1 Determining Hardware or Software Mode ............................................................................. 37
4.5.2 Hardware Mode Start-Up ...................................................................................................... 37
4.5.3 Software Mode Start-Up ........................................................................................................ 38
4.5.4 Initialization Flow Chart ......................................................................................................... 39
4.6 Device Control ................................................................................................................................ 40
DS721A6
3
CS42324
4.6.1 Hardware Mode ..................................................................................................................... 40
4.6.2 Software Mode - I²C Control Port .......................................................................................... 41
4.6.3 Software Mode - SPI Control Port ......................................................................................... 42
4.6.4 Memory Address Pointer (MAP) ............................................................................................ 43
4.7 Interrupts and Overflow .................................................................................................................. 43
5. REGISTER QUICK REFERENCE ........................................................................................................ 44
6. REGISTER DESCRIPTION .................................................................................................................. 46
6.1 Device I.D. and Revision Register (Address 00h) (Read Only) ...................................................... 46
6.1.1 Device I.D. (Read Only) ........................................................................................................ 46
6.1.2 Chip Revision (Read Only) .................................................................................................... 46
6.2 Mute Control (Address 01h) ........................................................................................................... 46
6.2.1 System MCLK Source ........................................................................................................... 46
6.2.2 Mute DAC2 Left-Channel ...................................................................................................... 46
6.2.3 Mute DAC2 Right-Channel .................................................................................................... 47
6.2.4 Mute DAC1 Left-Channel ...................................................................................................... 47
6.2.5 Mute DAC1 Right-Channel .................................................................................................... 47
6.2.6 Mute ADC Left-Channel ........................................................................................................ 47
6.2.7 Mute ADC Right-Channel ...................................................................................................... 47
6.3 Operational Control (Address 02h) ................................................................................................. 47
6.3.1 Global Power-Down .............................................................................................................. 47
6.3.2 INT Pin High/Low Active (INT_H/L) ....................................................................................... 48
6.3.3 Freeze ................................................................................................................................... 48
6.3.4 Tri-State SDOUT ................................................................................................................... 48
6.3.5 Tri-State Serial Port 1 ............................................................................................................ 48
6.3.6 Tri-State Serial Port 2 ............................................................................................................ 49
6.4 Serial Port 1 Control (Address 03h) ................................................................................................ 49
6.4.1 Serial Port 1 Master/Slave Select .......................................................................................... 49
6.4.2 Serial Port 1 Speed Mode ..................................................................................................... 49
6.4.3 MCLK1 Divider ...................................................................................................................... 49
6.4.4 Serial Port 1 MCLK source .................................................................................................... 49
6.5 Serial Port 2 Control (Address 04h) ................................................................................................ 50
6.5.1 Serial Port 2 Master/Slave Select .......................................................................................... 50
6.5.2 Serial Port 2 Speed Mode ..................................................................................................... 50
6.5.3 MCLK2 Divider ...................................................................................................................... 50
6.5.4 Serial Port 2 MCLK Source ................................................................................................... 50
6.6 ADC Clocking (Address 06h) .......................................................................................................... 50
6.6.1 ADC MCLK Source ............................................................................................................... 50
6.6.2 ADC Serial Port Source ......................................................................................................... 51
6.6.3 ADC Digital Interface Format (ADC_DIF) .............................................................................. 51
6.7 DAC1 Clocking (Address 07h) ........................................................................................................ 51
6.7.1 DAC1 MCLK Source ............................................................................................................. 51
6.7.2 DAC1 Serial Port Source ....................................................................................................... 51
6.7.3 DAC1 Digital Interface Format (DAC1_DIF) .......................................................................... 51
6.8 DAC2 Clocking (Address 08h) ........................................................................................................ 52
6.8.1 DAC2 MCLK Source ............................................................................................................. 52
6.8.2 DAC2 Serial Port Source ....................................................................................................... 52
6.8.3 DAC2 Digital Interface Format (DAC2_DIF) .......................................................................... 52
6.9 ADC Control (Address 0Ah) ........................................................................................................... 52
6.9.1 ADC High-Pass Filter Freeze ................................................................................................ 52
6.9.2 ADC Soft Ramp Control ........................................................................................................ 52
6.9.3 Analog Input Selection .......................................................................................................... 53
6.10 DAC1 Control (Address 0Bh) ....................................................................................................... 53
6.10.1 DAC1 De-Emphasis Control ................................................................................................ 53
6.10.2 DAC1 Single Volume Control .............................................................................................. 53
4
DS721A6
CS42324
6.10.3 DAC1 Soft Ramp Control .................................................................................................... 53
6.10.4 DAC1 Zero Cross Control ................................................................................................... 54
6.10.5 DAC1 Loop-Back ................................................................................................................. 54
6.10.6 DAC1 Invert Signal Polarity ................................................................................................. 54
6.10.7 DAC1 Channel Mixer ........................................................................................................... 54
6.11 DAC2 Control (Address 0Ch) ....................................................................................................... 55
6.11.1 DAC2 De-Emphasis Control ................................................................................................ 55
6.11.2 DAC2 Single Volume Control .............................................................................................. 55
6.11.3 DAC2 Soft Ramp Control .................................................................................................... 55
6.11.4 DAC2 Zero Cross Control ................................................................................................... 55
6.11.5 DAC2 Loop-Back ................................................................................................................. 56
6.11.6 DAC2 Invert Signal Polarity ................................................................................................. 56
6.11.7 DAC2 Channel Mixer ........................................................................................................... 56
6.12 AOUT1 Control (Address 0Dh) ..................................................................................................... 56
6.12.1 External Mute Control Pin ................................................................................................... 56
6.12.2 AOUT1 Select ..................................................................................................................... 56
6.13 AOUT2 Control (Address 0Eh) ..................................................................................................... 57
6.13.1 External Mute Control Pin ................................................................................................... 57
6.13.2 AOUT2 Select ..................................................................................................................... 57
6.14 AOUT3 Control (Address 0Fh) ..................................................................................................... 57
6.14.1 External Mute Control Pin ................................................................................................... 57
6.14.2 AOUT3 Select ..................................................................................................................... 58
6.15 ADCx Volume Control: ADCA (Address 10h) & ADCB (Address 11h) ......................................... 58
6.16 DAC1x Volume Control: DAC1A (Address 12h) & DAC1B (Address 13h) ................................... 58
6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h) ................................... 59
6.18 Interrupt Mode (Address 16h) ....................................................................................................... 59
6.19 Interrupt Mask (Address 17h) ....................................................................................................... 59
6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM) ................................................................ 60
6.19.2 DAC2 Auto Mute Right Mask (DAC2_AMUTERM) ............................................................. 60
6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM) ................................................................ 60
6.19.4 DAC1 Auto Mute Right Mask (DAC1_AMUTELM) .............................................................. 60
6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM) .............................................................. 60
6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM) .............................................................. 60
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM) ................................................................... 61
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM) ................................................................. 61
6.20 Interrupt Status (Address 18h) (Read Only) ................................................................................. 61
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL) ................................................... 61
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER) ................................................ 61
6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL) ................................................... 62
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL) ................................................. 62
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR) ................................................. 62
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR) ................................................. 62
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP) ............................................................ 62
6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN) .......................................................... 63
7. GROUNDING AND POWER SUPPLY DECOUPLING ........................................................................ 64
8. ADC FILTER PLOTS ........................................................................................................................... 65
9. DAC DIGITAL FILTER RESPONSE PLOTS
................................................................................ 67
10. PARAMETER DEFINITIONS .............................................................................................................. 69
11. PACKAGE DIMENSIONS ................................................................................................................. 70
THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 70
12. ORDERING INFORMATION .............................................................................................................. 71
13. REVISION HISTORY .......................................................................................................................... 71
DS721A6
5
CS42324
LIST OF FIGURES
Figure 1.Equivalent Analog Output Load .................................................................................................. 16
Figure 2.Maximum Analog Output Loading ............................................................................................... 16
Figure 3.Serial Input Timing ...................................................................................................................... 22
Figure 4.Serial Output Timing ................................................................................................................... 23
Figure 5.Software Mode Timing - I²C Format ............................................................................................ 24
Figure 6.Software Mode Timing - SPI Mode ............................................................................................. 25
Figure 7.Typical Connection Diagram - Software Mode ........................................................................... 26
Figure 8.Typical Connection Diagram - Hardware Mode .......................................................................... 27
Figure 9.Serial Port Topology ................................................................................................................... 29
Figure 10.Master Mode Clock Generation ................................................................................................ 30
Figure 11.Converter Clocking ................................................................................................................... 31
Figure 12.Tri-State Serial Port .................................................................................................................. 31
Figure 13.Left-Justified up to 24-Bit Data .................................................................................................. 32
Figure 14.I²S up to 24-Bit Data ................................................................................................................. 32
Figure 15.Right-Justified 16-Bit Data, Right-Justified 24-Bit Data ............................................................ 32
Figure 16.Analog Input Architecture .......................................................................................................... 33
Figure 17.De-Emphasis Curve .................................................................................................................. 35
Figure 18.Analog Output Architecture ....................................................................................................... 36
Figure 19.Initialization Flow Chart ............................................................................................................. 39
Figure 20.Software Mode Timing, I²C Write .............................................................................................. 41
Figure 21.Software Mode Timing, I²C Read .............................................................................................. 41
Figure 22.Software Mode Timing, SPI Mode ............................................................................................ 43
Figure 23.Single-Speed Mode Stopband Rejection .................................................................................. 65
Figure 24.Single-Speed Mode Transition Band ........................................................................................ 65
Figure 25.Single-Speed Mode Transition Band (Detail) ............................................................................ 65
Figure 26.Single-Speed Mode Passband Ripple ...................................................................................... 65
Figure 27.Double-Speed Mode Stopband Rejection ................................................................................. 65
Figure 28.Double-Speed Mode Transition Band ....................................................................................... 65
Figure 29.Double-Speed Mode Transition Band (Detail) .......................................................................... 66
Figure 30.Double-Speed Mode Passband Ripple ..................................................................................... 66
Figure 31.Single-Speed Stopband Rejection ............................................................................................ 67
Figure 32.Single-Speed Transition Band .................................................................................................. 67
Figure 33.Single-Speed Transition Band (detail) ...................................................................................... 67
Figure 34.Single-Speed Passband Ripple ................................................................................................ 67
Figure 35.Double-Speed Stopband Rejection ........................................................................................... 67
Figure 36.Double-Speed Transition Band ................................................................................................. 67
Figure 37.Double-Speed Transition Band (detail) ..................................................................................... 68
Figure 38.Double-Speed Passband Ripple ............................................................................................... 68
Figure 39.Quad-Speed Stopband Rejection ............................................................................................. 68
Figure 40.Quad-Speed Transition Band ................................................................................................... 68
Figure 41.Quad-Speed Transition Band (detail) ....................................................................................... 68
Figure 42.Quad-Speed Passband Ripple ................................................................................................. 68
LIST OF TABLES
Table 1. I/O Power Rails ........................................................................................................................... 12
Table 2. Speed Modes .............................................................................................................................. 28
Table 3. Single-Speed Mode Common Clock Frequencies ...................................................................... 28
Table 4. Double-Speed Mode Common Clock Frequencies ..................................................................... 28
Table 5. M1 and M0 Mode Pins in Hardware Mode .................................................................................. 29
Table 6. Slave Mode SCLK/LRCK Ratios ................................................................................................. 30
Table 7. MCLKx to LRCKx Ratios ............................................................................................................. 30
Table 8. Hardware Mode Interface Format Control ................................................................................... 32
6
DS721A6
CS42324
Table 9. Hardware Mode Feature Summary ............................................................................................. 40
Table 10. Freeze-able Bits ........................................................................................................................ 48
DS721A6
7
CS42324
1. PIN DESCRIPTIONS
VD
SCLK2
44
43
42
41
40
39
38
SDIN2
GND
45
MCLK2
VL
46
SDIN1
SDOUT
47
LRCK2
LRCK1
SCLK1
48
37
SDA/CDOUT
1
36
OVFL
SCL/CCLK
2
35
RST
AIN1A
3
34
AD1/CDIN
4
33
AIN1B
INT
5
32
AIN2A
FILT+
6
31
AIN2B
7
30
AIN3A
GND
8
29
AIN3B
VA
9
28
AIN4A
10
27
AIN4B
MUTEC1
11
26
AIN5A
MUTEC2
12
25
AIN5B
#
18
19
GNDH
VA_H
AOUT1A
20
21
22
23
24
AOUT3B
17
AOUT3A
16
AOUT2B
15
AOUT2A
14
AOUT1B
13
VA_H
VBIAS
VCMDAC
VCMADC
CS42324
VCMBUF
AD0/CS
Pin Name
MCLK1
Software Mode
MUTEC3
1.1
Pin Description
SDA/CDOUT
1
I²C Format SDA (Input/Output) - Acts as an input/output data pin. An external pull-up resistor is
required for I²C control port operation.
SPI Format CDOUT (Output) - Acts as an output only data pin.
SCL/CCLK
2
I²C Format, SCL (Input) – Serial clock for the serial control port. An external pull-up resistor is
required for I²C control port operation.
SPI Format, CCLK (Input) – Serial clock for the serial control port.
AD0/CS
3
I²C Format, AD0 (Input) - Forms the device address input AD[0].
SPI Format, CS (Input) - Acts as the active low chip select input.
AD1/CDIN
4
I²C Format, AD1 (Input) - Forms the device address input AD[1].
SPI Format, CDIN (Input) - Becomes the input data pin.
INT
5
Interrupt (Output) - Indicates an interrupt condition has occurred.
FILT+
6
FILT+ (Output) - Full-scale reference voltage for ADC.
VCMADC
7
ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent reference voltage.
GND
8
Analog Ground (Input) - Analog ground reference.
VA
9
Analog Power (Input) - Positive power for the internal analog section.
VBIAS
10
Bias Voltage (Output) - Positive reference voltage for the internal DAC.
MUTEC1
11
Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
8
DS721A6
CS42324
MUTEC2
12
Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
MUTEC3
13
Mute Control 3 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
VCMBUF
14
VCMBUF (Output) - Internally buffered VCMDAC
VCMDAC
15
DAC Common-Mode Voltage (Output) - Filter connections for the DAC internal quiescent reference voltage.
VA_H
16
18
Analog High Voltage Power (Input) - Positive power for the internal output buffer section.
GNDH
17
Analog Ground (Input) - Ground reference for high-voltage section.
AOUT1A, AOUT1B 19, 20
DAC Analog Audio Outputs (Output) - The full-scale output level is specified in the DAC Analog
AOUT2A, AOUT2B 21, 22
Characteristics specification table.
AOUT3A, AOUT3B 23, 24
AIN5B, AIN5A
AIN4B, AIN4A
AIN3B, AIN3A
AIN2B, AIN2A
AIN1B, AIN1A
RST
25, 26
27, 28
Stereo Analog Inputs 1-5 (Input) - The full-scale input level is specified in the ADC Analog Char29, 30
acteristics specification table.
31, 32
33, 34
35
Reset (Input) - The device enters a low-power mode when this pin is driven low.
OVFL
36
ADC Overflow (Output) - Indicates an ADC overflow condition is present.
SDIN2
SDIN1
37
38
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
MCLK2
39
Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators.
LRCK2
40
Serial Port 2 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio input data line.
SCLK2
41
Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.
VD
42
Digital Power (Input) - Positive power for the internal digital section.
GND
43
Digital Ground (Input) - Ground reference for the internal digital section.
VL
44
Digital Interface Power (Input) - Determines the required signal level for the control and serial
port interfaces as shown in “I/O Power Rails” on page 12. Refer to the“Recommended Operating
Conditions” on page 13 for appropriate voltages.
SDOUT
45
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK1
46
Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.
LRCK1
47
Serial Port 1 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio output data line.
MCLK1
48
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal also clocks the DAC’s delta-sigma modulators.
DS721A6
9
CS42324
LRCK1
SCLK1
SDOUT
VL
GND
VD
SCLK2
LRCK2
MCLK2
SDIN1
SDIN2
47
46
45
44
43
42
41
40
39
38
37
1
36
OVFL
M1
2
35
RST
MDIV
3
34
AIN1A
MUTE
4
33
AIN1B
DIF
5
32
AIN2A
31
AIN2B
30
AIN3A
CS42324
6
10
AIN4B
MUTEC1
11
26
AIN5A
MUTEC2
12
25
AIN5B
#
1, 2
14
15
16
17
18
19
20
AOUT1B
13
21
22
23
24
AOUT3B
AIN4A
27
AOUT3A
28
AOUT2B
9
AOUT2A
VA
AOUT1A
AIN3B
VA_H
29
GNDH
8
VA_H
GND
VCMDAC
7
VCMBUF
VCMADC
VBIAS
M0, M1
48
M0
FILT+
Pin Name
MCLK1
Hardware Mode
MUTEC3
1.2
Pin Description
Mode Selection (Input) - Determines the operational mode of the device.
MDIV
3
MCLK Divider (Input) - Setting this pin high places a divide-by-2 circuit in the MCLK path to the
core device circuitry.
MUTE
4
MUTE (Input) - Engages the internal digital mute and activates the MUTECx pins
DIF
5
DIF (Input) - Sets the serial audio interface format. Setting DIF high selects I²S audio format and
low selects LJ audio format.
FILT+
6
FILT+ (Output) - Full-scale reference voltage for ADC.
VCMADC
7
ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent reference voltage.
GND
8
Analog Ground (Input) - Analog ground reference.
VA
9
Analog Power (Input) - Positive power for the internal analog section.
VBIAS
10
Bias Voltage (Output) - Positive reference voltage for the internal DAC.
MUTEC1
11
Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
MUTEC2
12
Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
10
DS721A6
CS42324
MUTEC3
13
VCMBUF
14
VCMDAC
15
VA_H
GNDH
Mute Control 3 (Output) - Active-low mute output can drive external circuitry to eliminate the
clicks and pops associated with any single-rail output. This pin will become a high-impedance output during power-down mode or when an invalid MCLK to LRCK ratio is detected.
VCMBUF (Output) - Internally buffered VCMDAC
DAC Common-Mode Voltage (Output) - Filter connections for the DAC internal quiescent reference voltage.
16, 18 Analog High Voltage Power (Input) - Positive power for the internal output buffer section.
17
Analog Ground (Input) - Ground reference for high-voltage section.
AOUT1A, AOUT1B 19, 20 DAC Analog Audio Outputs (Output) - The full-scale output level is specified in the DAC Analog
AOUT2A, AOUT2B 21, 22 Characteristics specification table.
AOUT3A, AOUT3B 23, 24
AIN5B, AIN5A
AIN4B, AIN4A
AIN3B, AIN3A
AIN2B, AIN2A
AIN1B, AIN1A
25, 26 Stereo Analog Inputs 1-5 (Input) - The full-scale input level is specified in the ADC Analog Char27, 28 acteristics specification table.
29, 30
31, 32
33, 34
RST
35
Reset (Input) - The device enters a low-power mode when this pin is driven low.
OVFL
36
ADC Overflow (Output) - Indicates an ADC overflow condition is present.
SDIN2
SDIN1
37
38
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
MCLK2
39
Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modulators.
LRCK2
40
Serial Port 2 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio input data line.
SCLK2
41
Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.
VD
42
Digital Power (Input) - Positive power for the internal digital section.
GND
43
Digital Ground (Input) - Ground reference for the internal digital section.
VL
44
Digital Interface Power (Input) - Determines the required signal level for the control and serial
port interfaces as shown in “I/O Power Rails” on page 12. Refer to the“Recommended Operating
Conditions” on page 13 for appropriate voltages
SDOUT
45
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK1
46
Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.
LRCK1
47
Serial Port 1 Left Right/Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio output data line.
MCLK1
48
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this signal also clocks the DAC’s delta-sigma modulators.
DS721A6
11
CS42324
1.3
Digital I/O Pin Characteristics
The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.
Power
Supply
Pin
Number
Pin Name
I/O
Driver
Receiver
SDA
CDOUT
Input/Output
Hi-Z/Output
1.8 V - 3.3 V, Open Drain
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V, with Hysteresis
2
SCL
CCLK
Input
-
1.8 V - 3.3 V, with Hysteresis
3
AD0
CS
Input
-
1.8 V - 3.3 V, with Hysteresis
4
AD1
CDIN
Input
-
1.8 V - 3.3 V, with Hysteresis
5
INT
Output
1.8 V - 3.3 V, Open Drain
1.8 V - 3.3 V, with Hysteresis
M0
Input
-
1.8 V - 3.3 V, with Hysteresis
2
M1
Input
-
1.8 V - 3.3 V, with Hysteresis
3
MDIV
Input
-
1.8 V - 3.3 V, with Hysteresis
4
MUTE
Input
-
1.8 V - 3.3 V, with Hysteresis
5
DIF
Input
-
1.8 V - 3.3 V, with Hysteresis
35
RST
Input
-
1.8 V - 3.3 V
47
40
LRCK1
LRCK2
Input/Output
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V
46
41
SCLK1
SCLK2
Input/Output
1.8 V - 3.3 V, CMOS
1.8 V - 3.3 V
48
39
MCLK1
MCLK2
Input
-
1.8 V - 3.3 V
38
37
SDIN1
SDIN2
Input
-
1.8 V - 3.3 V
45
SDOUT
Output
1.8 V - 3.3 V, CMOS
-
36
OVFL
Output
1.8 V - 3.3 V, Open Drain
-
11
12
13
MUTEC1
MUTEC2
MUTEC3
Output
9.0 V - 12.0 V
-
Software Mode
1
VL
Hardware Mode
1
VL
All Modes
VL
VA_H
Table 1. I/O Power Rails
12
DS721A6
CS42324
2. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
GND = GNDH = 0 V; All voltages with respect to ground.
Parameters
DC Power Supplies:
Analog
Digital
Logic
High Voltage Analog
Ambient Operating Temperature (Power Applied)
Commercial(-CQZ)
Automotive(-DQZ)
Symbol
VA
VD
VL
VA_H
Min
3.13
3.13
1.71
8.55
Nom
3.3
3.3
3.3
9.0
Max
3.47
3.47
3.47
12.60
Units
V
V
V
V
TA
-40
-40
-
+85
+105
°C
°C
ABSOLUTE MAXIMUM RATINGS
GND = GNDH = 0 V; All voltages with respect to ground. (Note 1)
Parameter
DC Power Supplies:
Input Current
Analog
Digital
Logic
High Voltage Analog
(Note 2)
Analog Input Voltage
Symbol
Min
Max
Units
VA
VD
VL
VA_H
-0.3
-0.3
-0.3
-0.3
+4.50
+4.50
+4.50
+17.0
V
V
V
V
Iin
-10
+10
mA
VINA
GND - 0.3
VA_H + 0.3
V
VIND
-0.3
VL + 0.4
V
Ambient Operating Temperature (Power Applied)
TA
-55
+125
°C
Storage Temperature
Tstg
-65
+150
°C
Digital Input Voltage
Logic
Notes: 1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
DS721A6
13
CS42324
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)
Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V, VA_H = 9 V, GND = GNDH = 0 V; TA = 25° C;
997 Hz Full-Scale Output Sine Wave. Decoupling capacitors, Filter capacitors, and Recommended output filter as
shown in Figure 7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement
Bandwidth 10 Hz to 20 kHz,
Parameter
Min
Typ
Max
Unit
94
91
88
85
100
97
93
90
-
dB
dB
dB
dB
-
-90
-77
-37
-87
-77
-37
-84
-73
-33
-82
-62
-22
dB
dB
dB
dB
dB
dB
-
-100
-
dB
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
Symbol
(Note 3)
A-weighted
unweighted
A-weighted
unweighted
(Note 3)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
(1 kHz)
DC Accuracy
Analog Output
Full-Scale Output Voltage
Max current draw from an AOUT pin
1.9
2.0
2.1
Vrms
IOUT
-
575
-
μA
AC-Load Resistance
(Note 4)
RL
5
-
-
kΩ
Load Capacitance
(Note 4)
CL
-
-
100
pF
ZOUT
-
50
-
Ω
Output Impedance
Notes: 3. One-half LSB of triangular PDF dither added to data.
4. See Figures 1 and 2 on page 16. RL and CL reflect the minimum resistance and maximum capacitance
allowed in order to maintain stability in the internal op-amp. CL affects the dominant pole of the internal
output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable.
14
DS721A6
CS42324
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)
Test Conditions (unless otherwise specified): VA = 3.13 V to 3.47 V, VD = 3.13 V to 3.47 V, VL = 1.71 V to 3.47 V,
VA_H = 8.55 V to 12.60 V, GND = GNDH = 0 V; TA = -40° C to +85° C; 997 Hz Full-Scale Output Sine Wave.
Decoupling capacitors, filter capacitors, and recommended output filter as shown in Figure 7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth 10 Hz to 20 kHz,
Parameter
Min
Typ
Max
Unit
90
87
83
80
100
97
93
90
-
dB
dB
dB
dB
-
-90
-77
-37
-87
-77
-37
-80
-67
-27
-77
-67
-27
dB
dB
dB
dB
dB
dB
-
-100
-
dB
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
Symbol
(Note 3)
A-weighted
unweighted
A-weighted
unweighted
(Note 3)
0 dB
-20 dB
-60 dB THD+N
0 dB
-20 dB
-60 dB
(1 kHz)
DC Accuracy
Analog Output
Full-Scale Output Voltage
Max current draw from an AOUT pin
1.9
2.0
2.1
Vrms
IOUT
-
575
-
μA
AC-Load Resistance
(Note 4)
RL
5
-
-
kΩ
Load Capacitance
(Note 4)
CL
-
-
100
pF
ZOUT
-
50
-
Ω
Output Impedance
DS721A6
15
CS42324
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 5)
Symbol
Min
Typ
Max
Unit
0
0
-
.454
.499
Fs
Fs
Frequency Response (10 Hz to 20 kHz)
-0.01
-
+0.01
dB
StopBand
0.547
-
-
Fs
102
-
-
dB
Single-Speed Mode
Passband (Note 6)
to -0.01 dB corner
to -3 dB corner
StopBand Attenuation
(Note 6)
Group Delay
-
9.4/Fs
-
s
Fs = 44.1 kHz
tgd
-
-
+/-0.14
dB
to -0.01 dB corner
to -3 dB corner
0
0
-
.43
.499
Fs
Fs
-0.01
-
+0.01
dB
.583
-
-
Fs
80
-
-
dB
-
4.6/Fs
-
s
De-emphasis Error (Note 7)
Double-Speed Mode
Passband (Note 6)
Frequency Response (10 Hz to 20 kHz)
StopBand
StopBand Attenuation
(Note 6)
Group Delay
tgd
Notes: 5. Response is clock-dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this
data (Figures 31 to 42) have been normalized to Fs and can be de-normalized by multiplying the X-axis
scale by Fs.
6. For Single-Speed Mode, the measurement bandwidth is from StopBand to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is from StopBand to 3 Fs.
7. De-emphasis is available only in Single-Speed Mode.
125
V
out
AOUTx
R
L
C
L
GND
Capacitive Load -- C L (pF)
3.3 µF
100
75
Safe Operating
Region
50
25
10
2.5
5
10
15
20
Resistive Load -- RL (kΩ)
Figure 1. Equivalent Analog Output Load
16
Figure 2. Maximum Analog Output Loading
DS721A6
CS42324
ADC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)
Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V, VA_H = 9 V, GND = GNDH = 0 V; TA = 25° C;
997 Hz Input Sine Wave. Decoupling capacitors, filter capacitors, and recommended input filter as shown in Figure
7 on page 26 and Figure 8 on page 27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth
10 Hz to 20 kHz,
Parameter
Single-Speed Mode
Dynamic Range
Total Harmonic Distortion + Noise
Double-Speed Mode
Dynamic Range
Total Harmonic Distortion + Noise
Symbol
A-weighted
unweighted
(Note 8)
-1 dB
-20 dB
-60 dB
A-weighted
unweighted
(Note 8)
-1 dB
-20 dB
-60 dB
DC Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Input Characteristics
Full-scale Input Voltage
Input Impedance
Maximum Interchannel Input Impedance Mismatch
Interchannel Isolation
(1 kHz)
Note:
Min
Typ
Max
Unit
89
86
95
92
-
dB
dB
-
-88
-72
-32
-80
-
dB
dB
dB
89
86
95
92
-
dB
dB
-
-88
-72
-32
-80
-
dB
dB
dB
-5
-
0.1
±100
+5
-
dB
%
ppm/°C
0.576•VA
-
0.606•VA
200
2
-90
0.636•VA
-
Vrms
kΩ
%
dB
THD+N
THD+N
8. Referred to the typical line-level full-scale input voltage.
DS721A6
17
CS42324
ADC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)
Test Conditions (unless otherwise specified): VA = 3.13 V to 3.47 V, VD = 3.13 V to 3.47 V, VL = 1.71 V to 3.47 V,
VA_H = 8.55 V to 12.60 V, GND = GNDH = 0 V; TA = -40° C to +85° C; 997 Hz Input Sine Wave. Decoupling
capacitors, filter capacitors, and recommended input filter as shown in Figure 7 on page 26 and Figure 8 on page
27; Fs = 48 kHz or 96 kHz; Synchronous Mode; Measurement Bandwidth 10 Hz to 20 kHz,
Parameter
Single-Speed Mode
Dynamic Range
Total Harmonic Distortion + Noise
Double-Speed Mode
Dynamic Range
Total Harmonic Distortion + Noise
Symbol
A-weighted
unweighted
(Note 8)
-1 dB
-20 dB
-60 dB
A-weighted
unweighted
(Note 8)
-1 dB
-20 dB
-60 dB
DC Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Input Characteristics
Full-scale Input Voltage
Input Impedance
Maximum Interchannel Input Impedance Mismatch
Interchannel Isolation
(1 kHz)
Note:
18
Min
Typ
Max
Unit
85
82
95
92
-
dB
dB
-
-88
-72
-32
-78
-
dB
dB
dB
85
82
95
92
-
dB
dB
-
-88
-72
-32
-78
-
dB
dB
dB
-5
-
0.1
±100
+5
-
dB
%
ppm/°C
0.576•VA
-
0.606•VA
200
2
-90
0.636•VA
-
Vrms
kΩ
%
dB
THD+N
THD+N
9. Referred to the typical line-level full-scale input voltage.
DS721A6
CS42324
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 10)
Symbol
Min
Typ
Max
Unit
0
-
0.489
Fs
-
-
0.035
dB
Single-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
tgd
0.569
-
-
Fs
70
-
-
dB
-
12/Fs
-
s
0
-
0.489
Fs
-
-
0.025
dB
Double-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay
tgd
0.5604
-
-
Fs
69
-
-
dB
-
9/Fs
-
s
-
1
20
-
Hz
Hz
-
10
-
Deg
-
-
0
dB
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 11)
@ 20 Hz
(Note 11)
Passband Ripple
Filter Settling Time
105/Fs
s
Notes: 10. Response is clock dependent and will scale with sample rate (Fs). Note that the response plots
(Figures 23 to 30) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
11. Response shown is for Fs = 48 kHz.
DS721A6
19
CS42324
ANALOG PASS-THRU CHARACTERISTICS
Test Conditions (unless otherwise specified): VA = VD = VL = 3.3 V; VA_H = 9 V; GND = GNDH = 0 V; TA = 25° C;
Input test signal is a 1 kHz sine wave; Measurement Bandwidth is 10 Hz to 20 kHz; Synchronous Mode.
Parameter
Symbol
Analog Input to Analog Output Characteristics (Gain=0dB)
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 8)
0 dB
THD+N
-3 dB
Frequency Response 10 Hz to 20 kHz
Analog Characteristics
Max Input Voltage
Max Output Voltage
Max current draw from an AOUT pin
IOUT
AC-Load Resistance
(Note 4)
RL
Load Capacitance
(Note 4)
CL
Output Impedance
ZOUT
Interchannel Isolation
(1 kHz)
Note:
20
Min
Typ
Max
Unit
89
86
95
92
-
dB
dB
-
-87
-93
±0.1
-81
-
dB
dB
dB
5
-
2.0
2.0
575
50
-90
100
-
Vrms
Vrms
μA
kΩ
pF
Ω
dB
12. Referred to the typical line-level full-scale input voltage.
DS721A6
CS42324
DC ELECTRICAL CHARACTERISTICS
GND = GNDH = 0 V; all voltages with respect to ground. MCLK1=12.288 MHz; MCLK2=static; Fs=48 kHz; Master
Mode.
Parameter
Symbol
Min
Typ
Max
Unit
VA_H = 9 V
VA = 3.3 V
VD = 3.3 V
VL = 3.3 V
IA_H
IA
ID
IL
-
24
19
22
10
32
25
29
13
mA
mA
mA
mA
VA _H= 9 V
VL=VD=VA=3.3 V
IPD
-
0
200
-
μA
μA
VA_H = 9 V
VL=VD=VA = 3.3 V
All supplies
-
-
216
169
0.7
289
225
-
mW
mW
mW
PSRR
-
60
-
dB
VCMADC
-
0.5•VA
-
V
VCMDAC
-
4
-
V
ICM
-
-
1
μA
Power Supply Current (Normal Operation)
Power Supply Current
(Power-Down Mode) (Note 13)
Power Consumption (Normal Operation)
(Power-Down Mode)
Power Supply Rejection Ratio (1 kHz)
(Note 14)
Reference Voltages
VCMADC Nominal Voltage
VCMDAC Nominal Voltage
DC Current from VCMADC or VCMDAC
(Note 15)
ZCM
-
23
-
kΩ
FILT+ Nominal Voltage
VCMADC or VCMDAC Output Impedance
FILT+
-
VA
-
V
VBIAS Nominal Voltage
VBIAS
-
VA-0.8
-
V
Notes: 13. Power-Down Mode is defined as RST = Low, with all clock and data lines held static low and no analog
input.
14. Valid with the recommended capacitor values on FILT+, VCMDAC, VCMADC and VCMBUF as shown
in Figure 7 on page 26 and Figure 8 on page 27.
15. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic
de-coupling capacitors.
DIGITAL INTERFACE CHARACTERISTICS
Parameters (Note 16)
Symbol
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Digital Interface
VOH
High-Level Output Voltage at Io=2 mA
VOH
MUTEC1/MUTEC2/MUTEC3
Digital Interface
VOL
Low-Level Output Voltage at Io=2 mA
VOL
MUTEC1/MUTEC2/MUTEC3
Input Leakage Current
Iin
Input Capacitance
Maximum MUTEC1/MUTEC2/MUTEC3 Drive Current
Min
0.7•VL
VL-1.0
VA_H-1.0
-10
6
Minimum OVFL Active Time
Note:
10
--------------------LRCKX
Typ
3
Max
0.2•VL
0.4
0.4
+10
1
-
Units
V
V
V
V
V
V
μA
pF
mA
μs
16. Digital Interface signals include all pins sourced from the VL supply as shown in “I/O Power Rails” on
page 12.
DS721A6
21
CS42324
SWITCHING CHARACTERISTICS - SERIAL AUDIO
Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VL; CL = 20 pF.
Parameter
Symbol
Min
Typ
Max
Unit
1.024
40
50
41.4720
60
MHz
%
-
4
50
-
54
108
kHz
tPERIOD
tHIGH ÷ tPERIOD
64•Fs
72.3
40
50
64•Fs
60
Hz
ns
%
Master Clock (MCLKx = MCLK1, MCLK2)
MCLKx Frequency
MCLKx Duty Cycle
Sample Rates
Single-Speed Mode
Double-Speed Mode
Master Mode
SCLKx Frequency
SCLKx Period
SCLKx Duty Cycle (Note 17)
1/(128*108 kHz)
LRCKx setup
LRCKx hold
before SCLK rising
after SCLK rising
tSETUP1
tHOLD1
20
20
-
-
ns
SDOUT setup
SDOUT hold
before SCLK rising
after SCLK rising
tSETUP2
tHOLD2
10
10
-
-
ns
tPERIOD
tHIGH ÷ tPERIOD
72.3
40
64•Fs
50
60
Hz
ns
%
Slave Mode
SCLKx Frequency (Note 18)
SCLKx Period
SCLKx Duty Cycle
1/(128•108 kHz)
LRCKx setup
LRCKx hold
before SCLK rising
after SCLK rising
tSETUP1
tHOLD1
20
20
-
-
ns
SDOUT setup
SDOUT hold
before SCLK rising
after SCLK rising
tSETUP2
tHOLD2
10
10
-
-
ns
Notes: 17. Duty cycle of generated SCLKx in Master Mode depends on duty cycle of the corresponding MCLKx as
specified under “System Clocking” on page 28.
18. In Slave Mode, the SCLK/LRCK ratio can be set according to preference. However, specified performance is guaranteed only when using the ratios in Section 4.2.1 Master Mode on page 30 and Section
4.2.2 Slave Mode on page 30.
tPERIOD
tHIGH
SCLKx
tHOLD1
LRCKx
channel
tSETUP1
channel
tSETUP2
SDOUT
data
tHOLD2
data
Figure 3. Serial Input Timing
22
DS721A6
CS42324
SWITCHING CHARACTERISTICS - SERIAL AUDIO (CONT.)
Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VL; CL = 20 pF.
Parameter
Symbol
Min
Typ
Max
Unit
before SCLK rising
after SCLK rising
tSETUP3
tHOLD3
10
10
-
-
ns
before SCLK rising
after SCLK rising
tSETUP3
tHOLD3
10
10
-
-
ns
Master Mode
SDINx setup
SDINx hold
Slave Mode
SDINx setup
SDINx hold
tPERIOD
tHIGH
SCLKx
tHOLD1
LRCKx
channel
tSETUP1
channel
tSETUP3
SDINx
data
tHOLD3
data
Figure 4. Serial Output Timing
DS721A6
23
CS42324
SWITCHING CHARACTERISTICS - SOFTWARE MODE - I²C FORMAT
Inputs: Logic ‘0’ = GND = GNDH = 0 V, Logic ‘1’ = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
trc
-
1
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note Note:)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Fall Time SCL and SDA
Note:
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t hdst
t high
t
tf
hdst
t susp
SCL
t
24
t
t sud
t sust
low
hdd
Figure 5. Software Mode Timing - I²C Format
tr
DS721A6
CS42324
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT
Inputs: Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VLC; CL = 20 pF.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling (Note 20)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time (Note 21)
tdh
15
-
ns
Rise Time of CCLK and CDIN (Note 22)
tr2
-
100
ns
Fall Time of CCLK and CDIN (Note 22)
tf2
-
100
ns
Transition Time from CCLK to CDOUT Valid (Note 23)
tr2
-
100
ns
Time from CS rising to CDOUT High-Z
tf2
-
100
ns
Notes: 20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For FSCK < 1 MHz.
23. CDOUT should not be sampled during this time.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Hi-Impedance
CDOUT
t scdov
t scdov
t cscdo
Figure 6. Software Mode Timing - SPI Mode
DS721A6
25
CS42324
3. TYPICAL CONNECTION DIAGRAMS
+9 V to +12 V
+3.3 V
10 µF
0.1 µF
0.1 µF
VD
+3.3 V
VA_H
0.1 µF
10 µF
0.1 µF
1 µF
CS42324
0.1 µF 3.3 µF
470 Ω
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
AOUT1B
2 Vrms Right
Analog Out 1
470 Ω
Optional
Analog
Muting
MUTEC 2
0.1 µF
470 Ω
AOUT2A
VCMBUF
VCMDAC
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
2 Vrms Right
Analog Out 2
470 Ω
For best response to Fs /2 :
C=
Rext + 470
4πFs(Rext × 470)
Optional
Analog
Muting
MUTEC 3
470 Ω
AOUT3A
This circuitry is intended for applications where
the CS 42324 connects directly to a line level
output. For internal routing applications please
see the DAC Analog Output Characteristics
section for loading lim itations . R ext is the load
im pedance .
2 Vrms Left
Analog Out 2
* See Note 2
AOUT2B
Note 2 :
2 Vrms Left
Analog Out 1
* See Note 2
0.1 µF
GND
3.3 µF
Optional
Analog
Muting
AOUT1A
VBIAS
VCMADC
FILT+
1 µF
VA_H
M UTEC 1
VA
3.3 µF
10 µF
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
2 Vrms Left
Analog Out 3
* See Note 2
AOUT3B
MCLK2
470 Ω
2 Vrms Right
Analog Out 3
* Capacitors must be C0G or equivalent
SCLK2
LRCK2
SDIN1
SDIN2
SCLK1
SDOUT
2 Vrms Right
Analog In 1
1 µF
2 Vrms Left
Analog In 2
1 µF
2 Vrms Right
Analog In 2
1 µF
2 Vrms Left
Analog In 3
1 µF
2 Vrms Right
Analog In 3
1 µF
2 Vrms Left
Analog In 4
1 µF
2 Vrms Right
Analog In 4
1 µF
2 Vrms Left
Analog In 5
1 µF
2 Vrms Right
Analog In 5
AIN2B
INT
OVFL
AIN3A
RST
SCL/CCLK
AIN3B
SDA/CDOUT
AD0/CS
AD1/CDIN
+1.8V
to +3.3V
1 µF
AIN2A
LRCK1
2 kΩ
2 Vrms Left
Analog In 1
AIN1B
MCLK1
SOC/DSP
1 µF
AIN1A
AIN4A
AIN4B
2 kΩ
See Note 1
AIN5A
VL
0.1 µF
AIN5B
Note 1: Resistors are required for I ²C control
port operation
GND
GNDH
Figure 7. Typical Connection Diagram - Software Mode
26
DS721A6
CS42324
+9 V to +12 V
+3.3 V
10 µF
0.1 µF
0.1 µF
VD
+3.3 V
VA_H
0.1 µF
10 µF
0.1 µF
1 µF
CS42324
0.1 µF 3.3 µF
470 Ω
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
AOUT1B
2 Vrms Right
Analog Out 1
470 Ω
Optional
Analog
Muting
MUTEC2
0.1 µF
470 Ω
AOUT2A
VCMBUF
VCMDAC
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
2 Vrms Right
Analog Out 2
470 Ω
For best response to Fs/2 :
Rext + 470
C=
4πFs(Rext × 470)
Optional
Analog
Muting
MUTEC3
470 Ω
AOUT3A
This circuitry is intended for applications where
the CS42324 connects directly to a line level
output. For internal routing applications please
see the DAC Analog Output Characteristics
section for loading limitations. R ext is the load
impedance.
2 Vrms Left
Analog Out 2
* See Note 1
AOUT2B
Note 1 :
2 Vrms Left
Analog Out 1
* See Note 1
0.1 µF
GND
3.3 µF
Optional
Analog
Muting
AOUT1A
VBIAS
VCMADC
FILT+
1 µF
VA_H
MUTEC1
VA
3.3 µF
10 µF
3.3 µF
10 kΩ
*
C
3.3 µF
10 kΩ
*
C
2 Vrms Left
Analog Out 3
* See Note 1
AOUT3B
MCLK2
470 Ω
2 Vrms Right
Analog Out 3
* Capacitors must be C0G or equivalent
SCLK2
LRCK2
SDIN1
SDIN2
SCLK1
1 µF
2 Vrms Right
Analog In 1
1 µF
2 Vrms Left
Analog In 2
1 µF
2 Vrms Right
Analog In 2
1 µF
2 Vrms Left
Analog In 3
1 µF
2 Vrms Right
Analog In 3
1 µF
2 Vrms Left
Analog In 4
1 µF
2 Vrms Right
Analog In 4
1 µF
2 Vrms Left
Analog In 5
1 µF
2 Vrms Right
Analog In 5
AIN2A
LRCK1
VL
* See
Note 2
2 Vrms Left
Analog In 1
AIN1B
MCLK1
SOC/DSP
1 µF
AIN1A
AIN2B
5 kΩ
SDOUT
AIN3A
RST
OVFL
AIN3B
M0
M1
AIN4A
MDIV
MUTE
AIN4B
DIF
+1.8V
to +3.3V
AIN5A
VL
0.1 µF
AIN5B
Note 2 :
Pull-up on SDOUT indicates hardware mode
operation
GND
GNDH
Figure 8. Typical Connection Diagram - Hardware Mode
DS721A6
27
CS42324
4. APPLICATIONS
4.1
System Clocking
The CS42324 will operate at sampling frequencies from 4 kHz to 108 kHz. This range is divided into two
speed modes as shown in Table 2.
Master Mode Sampling
Frequency
Slave Mode
Sampling Frequency
Single-Speed
4-54 kHz
4-54 kHz
Double-Speed
50-108 kHz
50-108 kHz
Speed Mode
Table 2. Speed Modes
The CS42324 has two serial ports which can operate synchronously or asynchronously. Serial Port 1
(SP1) consists of the SCLK1 and LRCK1 signals. Serial Port 2 (SP2) consists of the SCLK2 and LRCK2
signals. The serial audio output, SDOUT, and serial audio inputs, SDIN1 and SDIN2, can be independently assigned to either of the two serial ports for ease of clocking. Each serial port may be independently
placed into Single- or Double-Speed Mode. The serial ports may also be independently placed into Master
or Slave Mode.
4.1.1
Master Clock
In both Synchronous and Asynchronous Modes, MCLKx (MCLK1 and/or MCLK2) and the corresponding
LRCKx must maintain an integer ratio. Some common ratios are shown in Tables 3 and 4. The LRCKx
frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out
of the device. The SP1_SPEED and SP2_SPEED bits and the MCLKx FREQ bits configure the device to
generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode when auto detect
mode is disabled. Tables 3 and 4 illustrate several standard audio sample rates and the required MCLKx
and LRCKx frequencies.
Mode
SINGLE SPEED
MODE (SSM)
LRCKx
(kHz)
MCLKx (MHz)
128x
192x
256x
384x
512x
768x
32
-
-
8.1920
12.2880
16.3840
24.5760
44.1
-
-
11.2896
16.9344
22.5792
33.8680
48
-
-
12.2880
18.4320
24.5760
36.8640
MCLKx FREQ [1:0]
-
-
00
01
10
11
MDIV pin
-
-
0
-
1
-
Table 3. Single-Speed Mode Common Clock Frequencies
Mode
DOUBLE SPEED
MODE (DSM)
LRCKx
(kHz)
MCLKx (MHz)
128x
192x
256x
384x
512x
768x
64
8.1920
12.2880
16.3840
24.5760
-
-
88.2
11.2896
16.9344
22.5792
33.8680
-
-
96
12.2880
18.4320
24.5760
36.8640
-
-
MCLKx FREQ [1:0]
00
01
10
11
-
-
MDIV pin
0
-
1
-
-
-
Table 4. Double-Speed Mode Common Clock Frequencies
28
DS721A6
CS42324
4.1.2
Synchronous / Asynchronous Mode
By default, the CS42324 operates in Synchronous Mode with both serial ports synchronous to MCLK1. In
this mode, the serial ports may operate at different synchronous rates as set by the SP1_SPEED and
SP2_SPEED bits, and MCLK2 does not need to be provided (the MCLK2 pin should be left unconnected
if not required).
If the SPx_MCLK (SPx = SP1 and/or SP2) bits in serial ports 1 and 2 are set differently, the CS42324 will
operate in Asynchronous Mode. The serial ports will operate asynchronously with Serial Port 1 clocked
from its SP1_MCLK selection and Serial Port 2 clocked from its SP2_MCLK selection. In this mode, the
serial ports may operate at different asynchronous rates.
In Hardware Mode MCLK1 is the master clock source for all internal circuits. Clock selection and asynchronous operation are not available.
4.2
Serial Port Operation
Each CS42324 serial audio interface port operates as either a clock slave or master. They accept externally
generated clocks in slave mode (LRCKx and SCLKx pins are inputs, generated clocks shown in Figure 9
are disabled) and will generate synchronous clocks derived from an input master clock (MCLK1/MCLK2) in
master mode (LRCKx and SCLKx pins are outputs, generated clocks shown in Figure 9 are enabled).
SP1_M/S
SP2_M/S
Generated-LRCK1
Generated-LRCK2
LRCK1
pin
LRCK2
pin
Internal-LRCK1
To converters
SP1_M/S
Generated-SCLK1
SCLK1
pin
Internal-LRCK2
To converters
Master
Mode
Clock
Generation
SP2_M/S
Figure 10
on page 30
Generated-SCLK2
Master
Mode
Clock
Generation
Figure 10
on page 30
SCLK2
pin
Internal-SCLK1
To converters
Internal-SCLK2
To converters
Serial Port 1 (SP1)
Serial Port 2 (SP2)
Figure 9. Serial Port Topology
The LRCK, Fs, is the frequency at which audio samples for each channel are clocked into or out of the device. In slave mode, LRCK should be synchronously derived from the MCLK selected in SPx_MCLK register.
The SCLK is the bit clock which is used to clock in the serial audio data stream. SCLK should adhere to the
timing requirements outlined in “Switching Characteristics - Serial Audio” on page 22.
The SP1_SPEED, SP2_SPEED, MCLK1 FREQ[1:0] and MCLK2 FREQ[1:0] Software Mode control bits or
the M1, M0, and MDIV hardware control pins, configure the device to generate the proper clocks in Master
Mode and receive the proper clocks in Slave Mode. In hardware mode, control pins M1 and M0 configure
the master/slave mode setting for the serial ports as well as the speed mode as shown in Table 5.
M0 (Pin 1)
0
0
1
1
M1 (Pin 2)
0
1
0
1
Serial Port Configuration
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Reserved
Clock Slave, Auto-detect Speed Mode
Table 5. M1 and M0 Mode Pins in Hardware Mode
DS721A6
29
CS42324
4.2.1
Master Mode
As a clock master, the LRCKx and SCLKx of each serial port will operate as outputs. The two serial ports
may be independently placed into Master or Slave Mode. Each LRCKx and SCLKx are internally derived
from the MCLKx selected by the SP1_MCLK and SP2_MCLK signals as shown in Figure 10.
MCLK1 FREQ[1:0]
÷1
÷1.5
01
÷2
10
÷3
11
0
Internal-MCLK1
MCLK1
÷256
0
÷128
1
Generated-LRCK1
00
SP1_SPEED
1
÷4
0
÷2
1
÷256
0
÷128
1
Generated-SCLK1
SP1_MCLK
MCLK2 FREQ[1:0]
Generated-LRCK2
÷1
00
÷1.5
01
0
SP2_SPEED
Internal-MCLK2
MCLK2
÷2
10
÷3
11
1
÷4
0
÷2
1
Generated-SCLK2
SP2_MCLK
Figure 10. Master Mode Clock Generation
4.2.2
Slave Mode
In Slave Mode, SCLKx and LRCKx operate as inputs. Each serial port may be independently placed into
Slave Mode. The Left/Right clock signal, LRCKx, must be equal to the sample rate, Fs. The serial bit
clock, SCLKx, must be equal to 128x, 64x, 48x, or 32x Fs depending on the desired speed mode. Refer
to Table 6 for required serial bit clock to Left/Right clock ratios.
If operating in Asynchronous Mode, LRCK1 and SCLK1 must be synchronously derived from the SP1’s
selected MCLK, and LRCK2 and SCLK2 must be synchronously derived from SP2’s selected MCLK. If
operating in Synchronous Mode, SCLK1, LRCK1, SCLK2 and LRCK2 must be synchronously derived
from the same MCLK. For more information on Synchronous and Asynchronous Modes, see “Synchronous / Asynchronous Mode” on page 29.
SCLKx to LRCKx Ratio
Serial Data Format
I²S, LJ or RJ Data Format
Single Speed Mode
Double Speed Mode
32, 48, 64, 128
32, 48, 64
Table 6. Slave Mode SCLK/LRCK Ratios
The speed of each serial port is automatically determined based on the input MCLKx to LRCKx ratio when
the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two
of MCLKx using either the MCLKx FREQ bits or the MDIV hardware control pin.
Mode
MCLKx to LRCKx Ratio
Single Speed Mode
Double Speed Mode
SW Auto Mode Detect
256, 384, 512, 768
128, 192, 256, 384
HW Auto Mode Detect
256, 512
128, 256
See Table 3 an Table 4 on page 28 for clock ratio configuration.
Table 7. MCLKx to LRCKx Ratios
30
DS721A6
CS42324
4.2.3
ADC, DAC1, and DAC2 clock selection
The ADC, DAC1, and DAC2 can be independently set to use either of the two serial ports as a clock
source. Each also has control over which MCLK to use. This allows for full flexibility in configuration of the
converter. Master/Slave control is achieved at the serial port level (See Figure 9 on page 29); the internal
converters discussed here are always slave.
Each converter has a bit in the registers (xxx_SP, where xxx = ADC, DAC1, or DAC2) which allows selection of the SCLK/LRCK pair used for the converter. The xxx_MCLK bits select which MCLK source to
use for the converter. If the serial port selected for use is in master mode, this selection must be the same
as the MCLK_SPx for the serial port which is in use. In Slave mode the MCLK selected must be synchronous to the LRCK/SCLK selected by xxx_SP.
ADC_MCLK
Internal-MCLK1
0
Internal-MCLK2
1
DAC1_MCLK
DAC2_MCLK
Internal-MCLK1
0
Internal-MCLK1
0
Internal-MCLK2
1
Internal-MCLK2
1
ADC_SP
DAC1_SP
DAC2_SP
Internal-LRCK1
0
Internal-LRCK1
0
Internal-LRCK1
0
Internal-LRCK2
1
Internal-LRCK2
1
Internal-LRCK2
1
Internal-SCLK1
0
Internal-SCLK1
0
Internal-SCLK1
0
Internal-SCLK2
1
Internal-SCLK2
1
Internal-SCLK2
1
ADC
ADC_DIF[2:0]
DAC1
DAC1_DIF[2:0]
SDOUT
DAC2
DAC2_DIF[2:0]
SDIN1
SDIN2
Figure 11. Converter Clocking
4.2.4
High-Impedance Digital Output
Each serial port may be placed on a clock/data bus that allows multiple masters, without the need for external buffers. The 3ST_SP1, 3ST_SP2 and 3ST_SDOUT bits place the internal buffers for the serial port
signals in a high-impedance state, allowing another device to transmit clocks or data without bus contention.
CS42324
Transm itting Device #2
Transm itting Device #1
3ST_SDOUT
SDOUT
3ST_SPx
SCLKx/LRCKx
Receiving Device
Figure 12. Tri-State Serial Port
DS721A6
31
CS42324
4.2.5
Digital Interface Formats
Each converter (ADC, DAC1, and DAC2) has independent selection for serial formats (I²S, Left-Justified,
etc.). Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 13-17 illustrate
the general structure of each format. Refer to “Switching Characteristics - Serial Audio” on page 22 or
“Switching Characteristics - Serial Audio (Cont.)” on page 23 for exact timing relationship between clocks
and data. For a complete overview of Serial Audio Interface Formats, please reference Application Note
AN282.
DIF (Pin 5) Setting
Selection
LO
Left-Justified Interface
HI
I²S Interface
Table 8. Hardware Mode Interface Format Control
L eft C h a n n el
LRCKx
Rig ht C h a n n el
SCLKx
SDIN1/2
SDOUT
MSB
MSB
LS B
LS B
MSB
AOUTxB
AINxB
AOUTxA
AINxA
Figure 13. Left-Justified up to 24-Bit Data
LRCKx
L eft C h a n n el
Rig ht C h a n n el
SCLKx
SDIN1/2
SDOUT
M SB
MSB
LS B
MSB
LS B
AOUTxB
AINxB
AOUTxA
AINxA
Figure 14. I²S up to 24-Bit Data
LRCKx
L e ft C h a n n e l
R ig ht C h a n n e l
SCLKx
SDIN1/2
SDOUT
M SB
LS B
AOUTxA
AINxA
MSB
LS B
AOUTxB
AINxB
Figure 15. Right-Justified 16-Bit Data, Right-Justified 24-Bit Data
4.2.6
Synchronization of Multiple Devices
In systems where multiple ADCs and DACs are required, care must be taken to achieve simultaneous
sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for
all of the CS42324’s in the system. If only one master clock source is needed, one solution is to place one
CS42324 in Master Mode, and slave all of the other devices to the one master.
32
DS721A6
CS42324
4.3
Analog-to-Digital Data Path
4.3.1
ADC Analog Input Multiplexer
AINxA and AINxB are the analog inputs, internally biased to VCMADC. The CS42324 contains a stereo
5-to-1 analog input multiplexer which can select one of 5 possible stereo analog input sources and route
it to the ADC. Figure 16 shows the architecture of the input multiplexer.
AIN1A
AIN2A
AIN3A
MUX
Out to ADC
Channel A
AIN4A
AIN5A
AIN_SEL[2:0]
AIN1B
AIN2B
AIN3B
MUX
Out to ADC
Channel B
AIN4B
AIN5B
Figure 16. Analog Input Architecture
“Section 6.9 “ADC Control (Address 0Ah)” on page 52” outlines the bit settings necessary to control the input multiplexer. By default, line level input 1 is selected.
4.3.2
ADC Description
The ADC analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for input signals which are
(n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of
capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided
since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
The ADC output data is in two’s complement binary format. For inputs above positive full-scale or below
negative full-scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to “ADC Analog Characteristics - Commercial (-CQZ)” on page 17 for
the specified offset level).
DS721A6
33
CS42324
4.3.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS42324, a small DC offset may be
driven into the A/D converter. The CS42324 includes a high-pass filter after the decimator to remove any
DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit is set during normal operation, the current value of the DC offset for the each
channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature
makes it possible to perform a system DC offset calibration by:
1. Running the CS42324 with the high-pass filter enabled until the filter settles. See “ADC Digital Filter
Characteristics” on page 19 for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset for continuous subtraction.
A system calibration performed in this way eliminates offsets anywhere in the signal path between the
calibration point and the CS42324.
4.3.4
Digital Attenuation Control
Digital attenuation control functions are implemented, offering independent channel control for the ADC
PCM signal path. The volume controls are programmable to ramp in increments of 0.5 dB at a rate controlled by the ADC soft ramp.
Each ADC signal path may also be independently muted via mute control bits. When enabled, each bit
attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the attenuation level set in the respective volume control register. The attenuation is ramped up and down at the
rate specified by the ADC_SOFT.
4.4
4.4.1
Digital-to-Analog Data Path
Digital Volume Control
Two stereo digital volume control functions are implemented, offering independent channel control for
DAC1 and DAC2 PCM signal paths into the digital mixer. The volume controls are programmable to ramp
in increments of 0.5 dB at a rate controlled by the DAC1/2 soft ramp/zero cross settings.
Each DAC1/2 signal path may also be independently muted via mute control bits. When enabled, each
bit attenuates the signal to its maximum value. When the mute bit is disabled, the signal returns to the
attenuation level set in the respective volume control register. The attenuation is ramped up and down at
the rate specified by the DAC1/2_SOFT and DAC1/2_ZC bits.
4.4.2
Mono Channel Mixer
Independent channel mixers for DAC1 and DAC2 may be used to create a mix of the left and right channels PCM signals. This mix allows the user to produce a MONO signal from a stereo source. The mixer
may also be used to implement a left/right channel swap.
34
DS721A6
CS42324
4.4.3
De-Emphasis Filter
The CS42324 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 17. The frequency response of the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 17. De-Emphasis Curve
4.4.4
Internal Digital Loopback
The CS42324 supports an internal digital loopback mode in which the ADC’s output data can be internally
routed to either of the DAC inputs. This mode may be activated by setting the DACx_LOOP_BACK bit in
“DAC1 Control (Address 0Bh)” on page 53 and “DAC2 Control (Address 0Ch)” on page 55. During this
mode, the ADC and DAC will need to operate at the same synchronous sample rate. When the
DACx_LOOP_BACK bit is set, the respective DACx_DIF[2:0] bits must be set to the same value as the
ADC_DIF[2:0] register.
During loop back mode, the ADC data will continue to be present on the SDOUT pin in the format selected
by the ADC_DIF[2:0] bits.
4.4.5
DAC Description
The CS42324 uses a switched current architecture followed by on chip current to voltage conversion and
continuous time low-pass filter. The digital interpolator response is shown in the “DAC Digital Filter Response Plots” on page 67. The recommended external analog circuitry is shown in the “Typical Connection Diagrams” on page 26.
The CS42324 DAC does not include phase or amplitude compensation for an external filter. Therefore,
the DAC system phase and amplitude response will be dependent on the external analog circuitry.
DS721A6
35
CS42324
4.4.6
Analog Output Multiplexer
The CS42324 contains three independent stereo 7-to-1 analog output multiplexers which can select one
of seven possible stereo analog output sources and route it to the AOUTxA and AOUTxB pins. Figure 18
shows the architecture of the analog output multiplexer.
DAC1A
DAC2A
AIN1A
AIN2A
MUX
AOUTxA
AIN3A
AIN4A
AIN5A
AOUTx_SEL[2:0]
DAC1B
DAC2B
AIN1B
AIN2B
MUX
AOUTxB
AIN3B
AIN4B
AIN5B
Figure 18. Analog Output Architecture
“Section 6.12 “AOUT1 Control (Address 0Dh)” on page 56” and Section 6.13 “AOUT2 Control (Address
0Eh)” on page 57 outline the bit settings necessary to control the output multiplexer.
4.4.7
Output Transient Control
The CS42324 uses Popguard technology to minimize the effects of output transients during power-up and
power-down. This technique eliminates the audio transients commonly produced by single-ended singlesupply converters when it is implemented with external DC-blocking capacitors connected in series with
the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.4.7.1
Power-Up
When the device is initially powered up, the audio outputs AOUTxA and AOUTxB are clamped to VCMBUF which is initially low. After the PDN bit is released (set to ‘0’) the outputs begin to ramp with VCMBUF
towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual
voltage ramping allows time for the external DC-blocking capacitors to charge to VCMBUF, effectively
blocking the quiescent DC voltage. Audio output from the DACs will begin after approximately 2000 sample periods.
4.4.7.2
Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this, either the PDN bit should be set or the device should be reset about
250 ms before removing power. During this time, the voltage on VCMBUF and the AOUTx outputs discharge gradually to GND. If power is removed before this 250 ms time period has passed, a transient will
occur when the VA supply drops below that of VCMBUF. There is no minimum time for a power cycle;
power may be re-applied at any time.
36
DS721A6
CS42324
4.4.7.3
Serial Interface Clock Changes
When changing the serial port clock ratio or sample rate, it is recommended that zero data (or near zero
data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking
change, the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at
the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero
data state.
4.4.8
Mute Control
The MUTECx pins become active during power-up initialization, reset, software/hardware muting, and
power-down mode (PDN=1). The MUTECx pins are intended to be used as control for an external mute
circuit in order to add off-chip mute capability.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. The MUTECx pins are active-low CMOS drivers.
4.5
Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 19 on page 39. The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modulators and software registers are reset. The internal voltage reference, multi-bit DACs and ADC, and on-chip
amplifiers are powered down.
4.5.1
Determining Hardware or Software Mode
The device will remain in the Power-Down state until the RST pin is brought high. If there is a pull-up on
SDOUT, or SDOUT is held high by any other means at the time RST pin is brought high, the device will
enter Hardware mode and begin powering up immediately. If no pull-up is present, or SDOUT is held low
by any other means at the time RST pin is brought high, the device will enter software mode.
4.5.2
Hardware Mode Start-Up
When the pull-up on SDOUT is present Hardware Mode is selected. Once hardware mode is selected,
the hardware mode configuration pins are used to set up the device and power-up will occur following the
HW startup path as shown in Figure 19 on page 39. The modes of configuration for this mode can be
found in Section 4.6.1 "Hardware Mode" on page 40. Because of the limited configuration abilities in Hardware mode, many modes of operation are not available.
Only MCLK1 needs to be applied. Once the appropriate MCLK1 is valid and RST is high, the quiescent
voltage, VCMADC and VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will begin
powering up to normal operation. During this voltage reference ramp delay, both SDOUT and the
AOUTxA/AOUTxB outputs will be automatically muted. Once LRCKx is valid, MCLKx occurrences are
counted over one LRCKx period to determine the MCLKx/LRCKx frequency ratio and normal operation
begins.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
DS721A6
37
CS42324
4.5.2.1
Recommended Power-Up Sequence, Hardware Mode
1. Hold RST low until MCLK1 and the power supplies are stable.
2. Bring RST high (SDOUT must be pulled high).
3. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin.
4. Bring RST low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.5.2.2
Recommended Power-Down Sequence, Hardware Mode
To minimize audible pops when turning off or placing the CODEC in standby:
1. Mute the SDIN1 and SDIN2 streams feeding the CODEC.
2. Bring RST low.
4.5.3
Software Mode Start-Up
When no pull-up on SDOUT is present, the Software Mode is accessible once RST is high. The desired
register settings can be loaded per the interface descriptions in “Software Mode - I²C Control Port” on
page 41. When the desired configuration is complete the PDN bit in “Operational Control (Address 02h)”
on page 47 should be set to 0 to initiate the power up sequence. The quiescent voltage, VCMADC and
VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will then begin powering up to normal operation. During this voltage reference ramp delay, both SDOUT and the AOUTxA/AOUTxB outputs
will be automatically muted. Once LRCKx is valid, MCLKx occurrences are counted over one LRCKx period to determine the MCLKx/LRCKx frequency ratio and normal operation begins.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.5.3.1
Recommended Power-Up Sequence, Software Mode
1. Hold RST low until the power supplies are stable.
2. Bring RST high, the device will be in “standby”.
3. Load the desired register settings while keeping the PDN bit set to ‘1’b.
4. Start MCLK1 (and MCLK2 if it is used) to the appropriate frequency, as discussed in Section 4.1.1.
5. Set the PDN bit to ‘0’b.
6. Apply all LRCKx, SCLKx and SDIN signals for normal operation to begin.
7. Bring RST low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.5.3.2
Recommended Power-Down Sequence, Software Mode
To minimize audible pops when turning off or placing the CODEC in standby:
1. Using the appropriate registers, 9Mute the AOUTxA, AOUTxB, DAC’s & ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches
a fully muted sate.
3. Bring RST low.
38
DS721A6
CS42324
4.5.4
Initialization Flow Chart
No Power
1. No audio signal
generated.
PDN bit = '1'b?
Power Applied
Standby Mode
1. No audio signal generated.
Yes 2. Control Port Registers retain
settings.
3. Update Control Port Registers
as Required.
No
Off Mode (Power Applied)
1. No audio signal generated.
2. Control Port Registers reset
to default.
20 ms delay
Charge Caps
1. VCMADC/VCMDAC
Charged to quiescent voltage.
2. Filt+/VBIAS Charged.
Yes
RST = Low?
No
DAC / ADC
Initialization
Yes
2048 internal
MCLKx cycle delay
No
Pull-up on SDOUT?
Digital/Analog
Output Muted
20 μs delay (DAC
only)
Hardware Mode
Minimal feature
set support.
Power Off Transition
1. Audible pops.
Software Mode
Registers setup to
desired settings.
Sub-Clocks Applied
1. LRCKx valid.
2. SCLKx valid.
3. Audio samples
processed.
Stand-By
Transition
1. Pops suppressed.
No
Reset Transition
1. Pops suppressed.
Valid
MCLKx/LRCKx
Ratio?
Yes
RST = Low
ERROR: MCLKx/LRCKx ratio change
ERROR: Power removed
Normal Operation
Audio signal generated per control port or standalone settings.
PDN bit set to '1'b
(software mode only)
ERROR: MCLKx removed
Analog Output Freeze
1. AOUTx bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
Figure 19. Initialization Flow Chart
DS721A6
39
CS42324
4.6
Device Control
In Software Mode, all functions and features may be controlled either by two-wire I²C or SPI Software Mode
interface. In Hardware Mode, a limited feature set may be controlled via hardware control pins.
4.6.1
Hardware Mode
A limited feature-set is available when the CS42324 powers up in Hardware Mode (see “Recommended
Power-Up Sequence, Hardware Mode” on page 38) and may be controlled via hardware control pins.
Table 9 shows a list of functions/features, the default configuration and the associated hardware control
available.
Feature/Function
Power Control
Hardware Mode Feature Summary
Default Configuration
Powered Up
ADC
Powered Up
DAC1
Powered Up
DAC2
SP_ERROR
Enabled; Active low, open drain
Enabled
(256x/128xFs, 512x/256xFs only)
Auto Detect
Serial Port Master/Slave and Speed Mode
Async / Sync Mode
Synchronous only
MCLK Divide
Serial Port Interface Format
(Selectable)
(Selectable)
Serial Port 1
Serial Port 2
Freeze Bit Settings
(Selectable)
DAC1 & DAC2 De-Emphasis
AOUT1x
AOUT2x
AOUT3x
source
source
source
Disabled
Enabled
Disabled
Disabled
Disabled
0 dB
Enabled
Continuous DC Subtraction
AIN1
Enabled
Disabled
Disabled
Disabled
Disabled (‘00’)
0 dB
Disabled
Output of DAC1
Output of DAC2
AIN1x
AOUTxx
MUTE
(Selectable)
ADC Volume & Gain
Soft Ramp
Zero Cross
Mute
Invert
Volume
ADC High-Pass Filter
ADC High-Pass Filter Freeze
AIN Input Select to ADC
(SDOUT source)
DAC1 & DAC2 Volume & Gain
Soft Ramp
Zero Cross
Mute
Invert
Mixer
Volume
Hardware Control
“M0” and “M1”, pins 1 and 2
(see page 29)
“MDIV” pin 3
(see page 30)
“DIF” pin 5
(see page 32)
MUTE pin 4
(see page 37)
Table 9. Hardware Mode Feature Summary
40
DS721A6
CS42324
4.6.2
Software Mode - I²C Control Port
Software Mode is used to access the registers, allowing the CS42324 to be configured for the desired
operational modes and formats. The operation in Software Mode may be completely asynchronous with
respect to the audio sample rates. However, to avoid potential interference problems, the I²C pins should
remain static if no operation is required. Software Mode supports the I²C interface, with the CS42324 acting as a slave device.
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. Pin AD0 forms
the least significant bit of the chip address and should be connected through a resistor to VL or GND as
desired. The state of the pin is sensed while the CS42324 is being reset.
The signal timings for a read and write cycle are shown in Figure 20 and Figure 21. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42324 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42324,
the chip address field, which is the first byte sent to the CS42324, should match 10011 followed by the
settings of AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP
allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge
bit. The ACK bit is output from the CS42324 after each input byte is read, and is input to the CS42324
from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
INCR
6
5
4
3
DATA +1
DATA
2
1
ACK
0
7
6
ACK
1
0
7
6
1
DATA +n
0
7
6
1
0
ACK
ACK
STOP
START
Figure 20. Software Mode Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
1 AD1 AD0 0
INCR
ACK
START
STOP
MAP BYTE
6
5
4
3
2
1
CHIP ADDRESS (READ)
1
0
ACK
0
0
1
DATA
1 AD1 AD0 1
7
ACK
START
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 21. Software Mode Timing, I²C Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As
shown in Figure 21, the write operation is aborted after the acknowledge for the MAP byte by sending a
stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
DS721A6
41
CS42324
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.6.3
Software Mode - SPI Control Port
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial clock, CCLK (see Figure 22
for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select signal and is
used to control SPI writes to the registers. When the device detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the rising edge
of CCLK.
4.6.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the Software Mode switching specifications in “Switching Characteristics - Software Mode - SPI Format” section on page 25.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 10011110 (R/W = 0).
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see Section 4.6.4.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are
desired, bring CS high
4.6.3.2
SPI Read
To read from the device, follow the procedure below while adhering to the values specified in “Switching
Characteristics - Software Mode - SPI Format” section on page 25.
1.
Bring CS low.
2. The address byte on the CDIN pin must then be 10011111 (R/W = 1).
3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the
SPI write operation.
4. If the INCR bit (see Section 4.6.4.1) is set to 1, keep CS low and continue providing clocks on CCLK
to read from multiple consecutive registers. Bring CS high when reading is complete.
42
DS721A6
CS42324
5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further reads from other registers are
desired, bring CS high.
CS
CCLK
C H IP
ADDRESS
CDIN
1001111
MAP
R/W
MSB
b y te 1
CDOUT
C H IP
ADDRESS
DATA
LSB
1001111
R/W
b y te n
High Impedance
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 22. Software Mode Timing, SPI Mode
4.6.4
Memory Address Pointer (MAP)
The MAP byte comes after the address byte and selects the register to be read or written. Refer to the
pseudo code above for implementation details.
4.6.4.1
Map Increment (INCR)
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is
set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP
will auto increment after each byte is written, allowing block reads or writes of successive registers.
4.7
Interrupts and Overflow
The CS42324 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see “Operational Control (Address 02h)” on page 47). When configured as active low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hookups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an
external pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Interrupt
Status (Address 18h) (Read Only)” on page 61. Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option
of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. Reading the Interrupt Status register will clear the
interrupt condtion.
The CS42324 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADC Overflow Positive and Negative conditions available in the Interrupt Status register; however,
these conditions do not need to be unmasked for proper operation of the OVFL pin.
DS721A6
43
CS42324
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. All bits marked as “Reserved” must maintain their default values.
Addr
00h
Function
Device ID
page 46
01h
Mute Control
page 46
02h
Operational
Control
03h
Serial Port 1
Control
page 47
page 49
04h
Serial Port 2
Control
05h
Reserved
page 50
06h
ADC clocking
page 50
07h
DAC1 clocking
page 51
08h
DAC2 clocking
09h
Reserved
page 52
0Ah
ADC Control
0Bh
DAC1 Control
page 52
page 53
0Ch
DAC2 Control
page 55
0Dh
AOUT1 Control
page 56
0Eh
AOUT2 Control
page 57
0Fh
AOUT3 Control
page 57
44
7
6
5
4
3
2
1
0
DEVICE3
DEVICE2
DEVICE1
DEVICE0
REV3
REV2
REV1
REV0
0
1
1
0
x
x
x
x
Reserved
SYS_MCLK
DAC2_
MuteL
DAC2_
MuteR
DAC1_
MuteL
DAC1_
MuteR
ADC_
MuteL
ADC_
MuteR
0
1
0
0
0
0
0
0
Reserved
PDN
INT_HL
FREEZE
Reserved
TRI-SDOUT
TRI-SP1
TRI-SP2
0
1
0
0
0
0
0
0
SP1_M/S
Reserved
Reserved
SP1_
SPEED
MCLK1
FREQ1
MCLK1
FREQ0
Reserved
SP1_MCLK
0
0
0
0
0
0
0
0
SP2_M/S
Reserved
Reserved
SP2_
SPEED
MCLK2
FREQ1
MCLK2
FREQ0
Reserved
SP2_MCLK
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
ADC_
MCLK
Reserved
ADC_
SP
Reserved
Reserved
ADC_DIF1
ADC_DIF0
0
0
0
0
1
0
0
0
Reserved
DAC1_
MCLK
Reserved
DAC1_SP
Reserved
Reserved
DAC1_DIF1
DAC1_DIF0
0
0
0
1
1
0
0
0
Reserved
DAC2_
MCLK
Reserved
DAC2_SP
Reserved
Reserved
DAC2_DIF1
DAC2_DIF0
0
0
0
1
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
ADC_
HPFRZ
ADC_
SOFT
Reserved
Reserved
AIN_SEL2
AIN_SEL1
AIN_SEL0
0
1
1
0
1
0
0
0
DAC1_
DEPH
DAC1_
SNGVOL
DAC1_SOFT
DAC1_ZC
DAC1_
LOOPBACK
DAC1_INV
0
0
1
0
0
0
DAC2_
DEPH
DAC2_
SNGVOL
DAC2_
SOFT
DAC2_
ZC
DAC2_
LOOPBACK
DAC2_INV
DAC1_MIX1 DAC1_MIX0
0
0
DAC2_MIX1 DAC2_MIX0
0
0
1
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
MUTEC1
AOUT1_
SEL2
AOUT1_
SEL1
AOUT1_
SEL0
0
0
0
0
0
1
1
0
Reserved
Reserved
Reserved
Reserved
MUTEC2
AOUT2_
SEL2
AOUT2_
SEL1
AOUT2_
SEL0
0
0
0
0
0
1
1
1
Reserved
Reserved
Reserved
Reserved
MUTEC3
AOUT3_
SEL2
AOUT3_
SEL1
AOUT3_
SEL0
0
0
0
0
0
0
0
1
DS721A6
CS42324
Addr
10h
Function
ADC Ch A
Volume Control
page 58
11h
ADC Ch B
Volume Control
page 58
12h
DAC1 Ch A
Volume Control
page 58
13h
DAC1 Ch B
Volume Control
page 58
14h
DAC2 Ch A
Volume Control
page 59
15h
DAC2 Ch B
Volume Control
page 59
16h
Interrupt Mode
page 59
17h
Interrupt Mask
18h
Interrupt Status
page 59
page 61
DS721A6
7
6
5
4
3
2
1
0
ADCA_
VOL7
ADCA_
VOL6
ADCA_
VOL5
ADCA_
VOL4
ADCA_
VOL3
ADCA_
VOL2
ADCA_
VOL1
ADCA_
VOL0
0
0
0
0
0
0
0
0
ADCB_
VOL7
ADCB_
VOL6
ADCB_
VOL5
ADCB_
VOL4
ADCB_
VOL3
ADCB_
VOL2
ADCB_
VOL1
ADCB_
VOL0
0
0
0
0
0
0
0
0
DAC1A_
VOL7
DAC1A_
VOL6
DAC1A_
VOL5
DAC1A_
VOL4
DAC1A_
VOL3
DAC1A_
VOL2
DAC1A_
VOL1
DAC1A_
VOL0
0
0
0
0
0
0
0
0
DAC1B_
VOL7
DAC1B_
VOL6
DAC1B_
VOL5
DAC1B_
VOL4
DAC1B_
VOL3
DAC1B_
VOL2
DAC1B_
VOL1
DAC1B_
VOL0
0
0
0
0
0
0
0
0
DAC2A_
VOL7
DAC2A_
VOL6
DAC2A_
VOL5
DAC2A_
VOL4
DAC2A_
VOL3
DAC2A_
VOL2
DAC2A_
VOL1
DAC2A_
VOL0
0
0
0
0
0
0
0
0
DAC2B_
VOL7
DAC2B_
VOL6
DAC2B_
VOL5
DAC2B_
VOL4
DAC2B_
VOL3
DAC2B_
VOL2
DAC2B_
VOL1
DAC2B_
VOL0
0
0
0
0
0
0
0
0
SP2_
CLKERR1
SP2_
CLKERR0
SP1_
CLKERR1
SP1_
CLKERR0
DAC_
AMUTE1
DAC_
AMUTE0
ADC_
OVFLx1
ADC_
OVFLx0
0
0
0
0
0
0
0
0
DAC2_
AMUTELM
DAC2_
AMUTERM
DAC1_
AMUTELM
DAC1_
AMUTERM
SP2_
CLKERRM
SP1_
CLKERRM
ADC_
OVFLPM
ADC_
OVFLNM
0
0
0
0
0
0
0
0
DAC2_
AMUTEL
DAC2_
AMUTER
DAC1_
AMUTEL
DAC1_
AMUTER
SP2_
CLKERR
SP1_
CLKERR
ADC_
OVFLP
ADC_
OVFLN
0
0
0
0
0
0
0
0
45
CS42324
6. REGISTER DESCRIPTION
All registers are read/write except where otherwise noted. See the following bit definition tables for bit assignment
information. The default state of each bit after release of reset is listed in the shaded row of each bit description
table. When writing to registers containing “Reserved” bits, all bits marked as “Reserved” must maintain their default
values.
6.1
Device I.D. and Revision Register (Address 00h) (Read Only)
7
6
5
4
3
2
1
0
DEVICE3
DEVICE2
DEVICE1
DEVICE0
REV3
REV2
REV1
REV0
1
ADC_
MuteL
0
ADC_
MuteR
6.1.1
Device I.D. (Read Only)
I.D. code for the CS42324.
DEVICE[3:0]
0110
6.1.2
Device
CS42324
Chip Revision (Read Only)
CS42324 revision level.
REV[3:0]
6.2
Revision Level
000
A1
001
B0
Mute Control (Address 01h)
7
6
Reserved
SYS_MCLK
6.2.1
5
DAC2_
MuteL
4
DAC2_
MuteR
3
DAC1_
MuteL
2
DAC1_
MuteR
System MCLK Source
This bit selects which MCLK pin provides the clock for internal state machines. It must always be set to
whichever clock is currently active.
SYS_MCLK
6.2.2
System MCLK source
0
MCLK1
1
MCLK2
Mute DAC2 Left-Channel
When set, this bit engages internal mute circuit on DAC2 output.
DAC2_MuteL
46
Mute status of DAC2 Left-channel
0
Un-muted
1
Muted
DS721A6
CS42324
6.2.3
Mute DAC2 Right-Channel
When set, this bit engages internal mute circuit on DAC2 output.
DAC2_MuteR
6.2.4
Mute status of DAC2 Right-channel
0
Un-muted
1
Muted
Mute DAC1 Left-Channel
When set, this bit engages internal mute circuit on DAC1 output.
DAC1_MuteL
6.2.5
Mute status of DAC1 Left-channel
0
Unmuted
1
Muted
Mute DAC1 Right-Channel
When set, this bit engages internal mute circuit on DAC1 output.
DAC1_MuteR
6.2.6
Mute Status of DAC1 Right-Channel
0
Un-muted
1
Muted
Mute ADC Left-Channel
When set, this bit engages internal mute circuit on ADC output.
ADC_MuteL
6.2.7
Mute Status of ADC Left-Channel
0
Un-muted
1
Muted
Mute ADC Right-Channel
When set, this bit engages internal mute circuit on ADC output.
ADC_MuteR
6.3
Mute Status of ADC Right-Channel
0
Un-muted
1
Muted
Operational Control (Address 02h)
7
Reserved
6.3.1
6
PDN
5
INT_H/L
4
FREEZE
3
Reserved
2
TRI-SDOUT
1
TRI-SP1
0
TRI-SP2
Global Power-Down
When set, this bit places the device in power-down mode.
PDN
DS721A6
Device Power-Down State
0
Device is running
1
Device is in power-down mode
47
CS42324
6.3.2
INT Pin High/Low Active (INT_H/L)
When this bit is set, the INT pin will function as an active high CMOS driver. When this bit is cleared, the
INT pin will function as an active low open drain driver and will require an external pull-up resistor for proper operation.
INT_H/L
6.3.3
INT Pin Polarity
0
Active low, open drain driver
1
Active high, CMOS driver
Freeze
This function allows modifications to be made to certain bits without the changes taking effect until the
Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze
bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in
Table 10.
FREEZE
FREEZE Status
0
Changes to registers take effect immediately
1
Changes to registers are held until FREEZE is released
Name
Register
Bit(s)
Mute Control
01h
7:0
ADC Ch A Vol. Control
0Fh
7:0
ADC Ch B Vol. Control
10h
7:0
DAC1 Ch A Vol. Control
11h
7:0
DAC1 Ch B Vol. Control
12h
7:0
DAC2 Ch A Vol. Control
13h
7:0
DAC2 Ch B Vol. Control
14h
7:0
Table 10. Freeze-able Bits
6.3.4
Tri-State SDOUT
When this bit is set, SDOUT will be placed in a high-impedance state.
TRI-SDOUT
6.3.5
SDOUT state
0
Output
1
High-impedance
Tri-State Serial Port 1
When enabled, and the device is configured as a master, then SCLK1 and LRCK1 of Serial Port 1 (SP1)
will be placed in a high-impedance output state. If Serial Port 1 is configured as a slave, SCLK1 and
LRCK1 will remain as inputs.
TRI-SP1
48
SCLK1 and LRCK1 State
0
SCLK1 and LRCK1 operate as inputs if Serial Port 1 is configured as a slave; SCLK1 and LRCK1
operate as outputs if Serial Port 1 is configured as a master
1
SCLK1 and LRCK1 operate as inputs if Serial Port 1 is configured as a slave; SCLK1 and LRCK1
become high-impedance outputs if Serial Port 1 is configured as a master
DS721A6
CS42324
6.3.6
Tri-State Serial Port 2
When enabled, and the device is configured as a master, then SCLK2 and LRCK2 of Serial Port 2 (SP2)
will be placed in a high-impedance output state. If Serial Port 2 is configured as a slave, SCLK2 and
LRCK2 will remain as inputs. SDIN1 and SDIN2 are always configured as inputs.
TRI-SP2
6.4
SCLK2 and LRCK2 State
0
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
operate as outputs if Serial Port 2 is configured as a master
1
SCLK2 and LRCK2 operate as inputs if Serial Port 2 is configured as a slave; SCLK2 and LRCK2
become high-impedance outputs if Serial Port 2 is configured as a master
Serial Port 1 Control (Address 03h)
7
6
5
4
SP1_M/S
Reserved
Reserved
SP1_SPEED
6.4.1
3
MCLK1
FREQ1
2
MCLK1
FREQ0
1
0
Reserved
SP1_MCLK
Serial Port 1 Master/Slave Select
This bit configures Serial Port 1 to operate as either a clock master or clock slave.
SP1_M/S
6.4.2
Serial Port 1 Master/Slave Select
0
Slave Mode
1
Master Mode
Serial Port 1 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 1.
SP1_SPEED
6.4.3
Serial Port 1 Speed Mode
0
Single-Speed Mode (SSM)
1
Double-Speed Mode (DSM)
MCLK1 Divider
These bits configure the internal MCLK1 dividers.
MCLK1
FREQ[1:0]
6.4.4
MCLK Divider
00
÷1
01
÷1.5
10
÷2
11
÷3
Serial Port 1 MCLK source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 1.
SP1_MCLK
DS721A6
Serial Port 1 MCLK source
0
MCLK1
1
MCLK2
49
CS42324
6.5
Serial Port 2 Control (Address 04h)
7
6
5
4
SP2_M/S
Reserved
Reserved0
SP2_SPEED
6.5.1
3
MCLK2
FREQ1
2
MCLK2
FREQ0
1
0
Reserved
SP2_MCLK
Serial Port 2 Master/Slave Select
This bit configures Serial Port 2 to operate as either a clock master or clock slave.
Serial Port 2 Master/Slave Select
SP2_M/S
6.5.2
0
Slave Mode
1
Master Mode
Serial Port 2 Speed Mode
In Master Mode this bit configures the speed mode of Serial Port 2.
SP2_SPEED
6.5.3
Serial Port 2 Speed Mode
0
Single-Speed Mode (SSM)
1
Double-Speed Mode (DSM)
MCLK2 Divider
These bits configure the internal MCLK2 dividers.
MCLK2
FREQ[1:0]
00
6.5.4
MCLK Divider
÷1
01
÷1.5
10
÷2
11
÷3
Serial Port 2 MCLK Source
This bit selects which MCLK pin provides the clock for deriving Master Mode sub-clocks for Serial Port 2.
SP2_MCLK
6.6
Serial Port 2 MCLK source
0
MCLK1
1
MCLK2
ADC Clocking (Address 06h)
7
6
5
4
3
2
1
0
Reserved
ADC_MCLK
Reserved
ADC_SP
Reserved
Reserved
ADC_DIF1
ADC_DIF0
6.6.1
ADC MCLK Source
This bit selects which MCLK pin provides the clock for the ADC.
ADC_MCLK
50
ADC MCLK source
0
MCLK1
1
MCLK2
DS721A6
CS42324
6.6.2
ADC Serial Port Source
This bit selects which serial port provides the sub clocks for the ADC.
ADC_SP
6.6.3
ADC sub clock source
0
Serial Port 1 (SCLK1/LRCK1)
1
Serial Port 2 (SCLK2/LRCK2)
ADC Digital Interface Format (ADC_DIF)
These bits configure the serial audio interface format for transmitting digital audio data on SDOUT
ADC_DIF[1:0]
00
6.7
ADC Serial Audio Interface Format
Left-Justified, 24-bit data
01
I²S, 24-bit data
10
Reserved
11
Reserved
DAC1 Clocking (Address 07h)
7
6
5
4
3
2
1
0
Reserved
DAC1_MCLK
Reserved
DAC1_SP
Reserved
Reserved
DAC1_DIF1
DAC1_DIF0
6.7.1
DAC1 MCLK Source
This bit selects which MCLK pin provides the clock for DAC1.
DAC1_MCLK
6.7.2
DAC1 MCLK source
0
MCLK1
1
MCLK2
DAC1 Serial Port Source
This bit selects which serial port provides the sub clocks for the DAC1.
DAC1_SP
6.7.3
DAC1 sub clock source
0
Serial Port 1 (SCLK1/LRCK1)
1
Serial Port 2 (SCLK2/LRCK2)
DAC1 Digital Interface Format (DAC1_DIF)
These bits configure the serial audio interface format for incoming digital audio data on SDIN1.
DAC1_DIF[1:0]
DS721A6
DAC1 Serial Audio Interface Format
00
Left-Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified, 16-bit data
11
Right Justified, 24-bit data
51
CS42324
6.8
DAC2 Clocking (Address 08h)
7
6
5
4
3
2
1
0
Reserved
DAC2_MCLK
Reserved
DAC2_SP
Reserved
Reserved
DAC2_DIF1
DAC2_DIF0
6.8.1
DAC2 MCLK Source
This bit selects which MCLK pin provides the clock for DAC2.
DAC2_MCLK
6.8.2
DAC2 MCLK source
0
MCLK1
1
MCLK2
DAC2 Serial Port Source
This bit selects which serial port provides the sub clocks for the DAC2.
DAC2_SP
6.8.3
DAC2 sub clock source
0
Serial Port 1 (SCLK1/LRCK1)
1
Serial Port 2 (SCLK2/LRCK2)
DAC2 Digital Interface Format (DAC2_DIF)
These bits configure the serial audio interface format for incoming digital audio data on SDIN2.
DAC2_DIF[1:0]
6.9
DAC2 Serial Audio Interface Format
00
Left-Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified, 16-bit data
11
Right Justified, 24-bit data
ADC Control (Address 0Ah)
7
6
5
4
3
2
1
0
Reserved
ADC_HPFRZ
ADC_SOFT
Reserved
Reserved
AIN_SEL2
AIN_SEL1
AIN_SEL0
6.9.1
ADC High-Pass Filter Freeze
The high-pass filter works by continuously subtracting a measure of the DC offset from the output of the
decimation filter. If the ADC_HPFRZ bit is taken high during normal operation, the current value of the DC
offset is frozen and this DC offset will continue to be subtracted from the conversion result. For DC measurements, this bit must be set to ‘1’.
ADC_HPFRZ
6.9.2
ADC High-Pass Filter Freeze
0
Continuous DC Subtraction
1
Fixed DC Subtraction
ADC Soft Ramp Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
52
DS721A6
CS42324
ADC_SOFT
6.9.3
ADC Soft Ramp Control
0
Off
1
On
Analog Input Selection
These bits are used to select the input source for the ADC.
AIN_SEL[2:0]
6.10
ADC Soft Ramp Control
000
Reserved
001
Line-Level Input Pair 1
010
Line-Level Input Pair 2
011
Line-Level Input Pair 3
100
Line-Level Input Pair 4
101
Line-Level Input Pair 5
110
Reserved
111
Reserved
DAC1 Control (Address 0Bh)
7
6
DAC1_SNGV
DAC1_DEPH
OL
5
4
DAC1_SOFT
DAC1_ZC
3
DAC1_
LOOPBACK
2
1
0
DAC1_INV
DAC1_MIX1
DAC1_MIX0
6.10.1 DAC1 De-Emphasis Control
This bit enables the digital filter to apply the standard 15μs/50μs digital de-emphasis filter response for a
sample rate (Fs) of 44.1 kHz. De-emphasis is available only in Single-Speed Mode.
DAC1_DEPH
DAC1 De-Emphasis Control
0
Off
1
On (valid for Fs = 44.1 kHz)
6.10.2 DAC1 Single Volume Control
The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on DAC1 channels is determined by the
DAC1A Volume Control register and the DAC1B Volume Control register is ignored.
DAC1_SNGVOL
DAC1 Single Volume Control
0
Off
1
On
6.10.3 DAC1 Soft Ramp Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
DAC1_SOFT
DS721A6
DAC1 Soft Ramp Control
0
Off
1
On
53
CS42324
6.10.4 DAC1 Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
DAC1_SOFT
0
0
1
1
DAC1_ZC
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled
6.10.5 DAC1 Loop-Back
Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.
DAC1_LOOP_
BACK
DAC1 Loop-Back
0
Off
1
On
6.10.6 DAC1 Invert Signal Polarity
When enabled, this bit will effect a 180 degree phase shift in the DAC1 channels.
DAC1_INV
DAC1 Invert Signal Polarity
0
Off
1
On
6.10.7 DAC1 Channel Mixer
These bits implement mono mixes of the left and right channels as well as a left/right channel swap.
DAC1_MIX[1:0]
54
DAC1 OUTA
DAC1 OUTB
00
L
R
01
10
L+R
----------2
L+R
----------2
11
R
L
DS721A6
CS42324
6.11
DAC2 Control (Address 0Ch)
7
DAC2_DEPH
6.11.1
6
DAC2_
SNGVOL
5
4
DAC2_SOFT
DAC2_ZC
3
DAC2_
LOOP_BACK
2
1
0
DAC2_INV
DAC2_MIX1
DAC2_MIX0
DAC2 De-Emphasis Control
This bit enables the digital filter to apply the standard 15μs/50μs digital de-emphasis filter response for a
sample rate (Fs) of 44.1 kHz. De-emphasis is available only in Single-Speed Mode.
DAC2_DEPH
6.11.2
DAC2 De-Emphasis Control
0
Off
1
On (valid for Fs = 44.1 kHz)
DAC2 Single Volume Control
The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on DAC2 channels is determined by the
DAC2A Volume Control register and the DAC2B Volume Control register is ignored.
DAC2_SNGVOL
6.11.3
DAC2 Single Volume Control
0
Off
1
On
DAC2 Soft Ramp Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
DAC2_SOFT
6.11.4
DAC2 Soft Ramp Control
0
Off
1
On
DAC2 Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
DAC2_SOFT
0
0
1
1
DS721A6
DAC2_ZC
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled
55
CS42324
6.11.5
DAC2 Loop-Back
Loops ADC SDOUT, SCLK, and LRCK to DAC1 serial port pins.
DAC2_LOOP_
BACK
6.11.6
DAC2 Loop-Back
0
Off
1
On
DAC2 Invert Signal Polarity
When enabled, this bit will effect a 180 degree phase shift in the DAC2 channels.
DAC2_INV
6.11.7
DAC2 Invert Signal Polarity
0
Off
1
On
DAC2 Channel Mixer
These bits implements mono mixes of the left and right channels as well as a left/right channel swap.
DAC2_MIX[1:0]
6.12
DAC2 OUTA
DAC2 OUTB
00
L
R
01
10
L+R
----------2
L+R
----------2
11
R
L
AOUT1 Control (Address 0Dh)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
MUTEC1
2
1
0
AOUT1_SEL2 AOUT1_SEL1 AOUT1_SEL0
6.12.1 External Mute Control Pin
This bit controls the logic state of the corresponding MUTEC1 pin. Though this bit is active high, it should
be noted that the MUTEC1 pin is active low.
MUTEC1
Output on MUTEC1 pin
0
High (Mute Disengaged)
1
Low (Mute Engaged)
6.12.2 AOUT1 Select
These bits are used to select the analog output source.
AOUT1_SEL[2:0]
000
56
AOUT1 Source
Reserved
001
AIN Pair 1
010
AIN Pair 2
011
AIN Pair 3
100
AIN Pair 4
101
AIN Pair 5
110
DAC1 Output Pair
111
DAC2 Output Pair
DS721A6
CS42324
6.13
AOUT2 Control (Address 0Eh)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
MUTEC2
2
1
0
AOUT2_SEL2 AOUT2_SEL1 AOUT2_SEL0
6.13.1 External Mute Control Pin
This bit controls the logic state of the corresponding MUTEC2 pin. Though this bit is active high, it should
be noted that the MUTEC2 pin is active low.
MUTEC2
Output on MUTEC2 pin
0
High (Mute Disengaged)
1
Low (Mute Engaged)
6.13.2 AOUT2 Select
These bits are used to select the analog output source.
AOUT2_SEL[2:0]
6.14
AOUT2 Source
000
Reserved
001
AIN Pair 1
010
AIN Pair 2
011
AIN Pair 3
100
AIN Pair 4
101
AIN Pair 5
110
DAC1 Output Pair
111
DAC2 Output Pair
AOUT3 Control (Address 0Fh)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
MUTEC3
2
1
0
AOUT3_SEL2 AOUT3_SEL1 AOUT3_SEL0
6.14.1 External Mute Control Pin
This bit controls the logic state of the corresponding MUTEC3 pin. Though this bit is active high, it should
be noted that the MUTEC3 pin is active low.
MUTEC3
DS721A6
Output on MUTEC3 pin
0
High (Mute Disengaged)
1
Low (Mute Engaged)
57
CS42324
6.14.2 AOUT3 Select
These bits are used to select the analog output source.
AOUT3_SEL[2:0]
6.15
AOUT3 Source
000
Reserved
001
AIN Pair 1
010
AIN Pair 2
011
AIN Pair 3
100
AIN Pair 4
101
AIN Pair 5
110
DAC1 Output Pair
111
DAC2 Output Pair
ADCx Volume Control: ADCA (Address 10h) & ADCB (Address 11h)
7
ADCx_VOL7
6
ADCx_VOL6
5
ADCx_VOL5
4
ADCx_VOL4
3
ADCx_VOL3
2
ADCx_VOL2
1
ADCx_VOL1
0
ADCx_VOL0
The level for each channel of the ADC can be adjusted in 0.5 dB increments as dictated by the ADC Soft
and Zero Cross bits (ADC_SOFT) from +12 to -84 dB. Levels are decoded in two’s complement, as shown
in the table below.
Binary Code
0001 1000
···
0000 0000
1111 1111
1111 1110
···
0101 1000
All other values
6.16
Volume Setting
+12.0 dB
···
0.0 dB
-0.5 dB
-1.0 dB
···
-84.0 dB
Reserved
DAC1x Volume Control: DAC1A (Address 12h) & DAC1B (Address 13h)
7
6
5
4
3
2
1
0
DAC1x_VOL7 DAC1x_VOL6 DAC1x_VOL5 DAC1x_VOL4 DAC1x_VOL3 DAC1x_VOL2 DAC1x_VOL1 DAC1x_VOL0
The level for each channel of DAC1 output can be adjusted in 0.5 dB increments as dictated by the DAC1
Soft and Zero Cross bits (DAC1_SOFT & DAC1_ZC) from 0 to -127.5 dB. Levels are decoded as unsigned,
as shown in the table below.
Binary Code
0000 0000
0000 0001
0000 0010
···
1111 1111
58
Volume Setting
0 dB
-0.5 dB
-1.0 dB
···
-127.5 dB
DS721A6
CS42324
6.17
DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h)
7
6
5
4
3
2
1
0
DAC2x_VOL7 DAC2x_VOL6 DAC2x_VOL5 DAC2x_VOL4 DAC2x_VOL3 DAC2x_VOL2 DAC2x_VOL1 DAC2x_VOL0
The level for each channel of DAC2 output can be adjusted in 0.5 dB increments as dictated by the DAC2
Soft and Zero Cross bits (DAC2_SOFT & DAC2_ZC) from 0 to -127.5 dB. Levels are decoded in unsigned,
as shown in the table below.
Binary Code
0000 0000
0000 0001
0000 0010
···
1111 1111
6.18
Volume Setting
0 dB
-0.5 dB
-1.0 dB
···
-127.5 dB
Interrupt Mode (Address 16h)
7
SP2_
CLKERR1
6
SP2_
CLKERR0
5
SP1_
CLKERR1
4
SP1_
CLKERR0
3
2
DAC_AMUTE1 DAC_AMUTE0
1
ADC_
OVFLx1
0
ADC_
OVFLx0
The Interrupt Mode register contains four two-bit codes which correspond to either an Interrupt Status bit or
group of bits as shown below. There are three ways to set the INT pin active in accordance with the interrupt
condition. In the Rising-edge Active Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-edge Active Mode, the INT pin becomes active on the removal of the interrupt condition.
In Level Active Mode, the INT pin remains active during the interrupt condition .
Interrupt Mode
SP2_CLKERR[1:0]
SP1_CLKERR[1:0]
DAC_AMUTE[1:0]
ADC_AVFLx[1:0]
Associated Interrupt Status Bit(s)
SP2_CLKERR
SP1_CLKERR
DAC2_AMUTEL, DAC2_AMUTER, DAC1_AMUTEL, DAC1_AMUTER
ADC_OVFLP, ADC_OVFLN
Bit Settings
00
01
10
11
6.19
Interrupt Mode Setting
Rising-edge Active
Falling-edge Active
Level Active
Reserved
Interrupt Mask (Address 17h)
7
DAC2_
AMUTELM
6
DAC2_
AMUTERM
5
DAC1_
AMUTELM
4
DAC1_
AMUTERM
3
SP2_
CLKERRM
2
SP1_
CLKERRM
1
ADC_
OVFLPM
0
ADC_
OVFLNM
These bits are mask bits for the corresponding bits in the “Interrupt Status (Address 18h) (Read Only)” register on page 61.
Bit Settings
0
1
DS721A6
Bit in Interrupt Register
Not Masked
Masked
59
CS42324
6.19.1 DAC2 Auto Mute Left Mask (DAC2_AMUTELM)
This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the
DAC2_AMUTEL interrupt is unmasked, meaning that if the DAC2_AMUTEL condition occurs, the INT pin
will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on
page 59. If the DAC2_AMUTELM bit is set, the DAC2_AMUTEL condition is masked, meaning that its occurrence will not affect the INT pin.
6.19.2 DAC2 Auto Mute Right Mask (DAC2_AMUTERM)
This bit serves as a mask for the DAC2 Auto Mute Left interrupt source. If this bit is cleared, the
DAC2_AMUTER interrupt is unmasked, meaning that if the DAC2_AMUTER condition occurs, the INT pin
will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on
page 59. If the DAC2_AMUTERM bit is set, the DAC2_AMUTER condition is masked, meaning that its
occurrence will not affect the INT pin.
6.19.3 DAC1 Auto Mute Left Mask (DAC1_AMUTELM)
This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the
DAC1_AMUTEL interrupt is unmasked, meaning that if the DAC1_AMUTEL condition occurs, the INT pin
will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on
page 59. If the DAC1_AMUTELM bit is set, the DAC1_AMUTEL condition is masked, meaning that its occurrence will not affect the INT pin.
6.19.4 DAC1 Auto Mute Right Mask (DAC1_AMUTELM)
This bit serves as a mask for the DAC1 Auto Mute Left interrupt source. If this bit is cleared, the
DAC1_AMUTER interrupt is unmasked, meaning that if the DAC1_AMUTER condition occurs, the INT pin
will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)” register on
page 59. If the DAC1_AMUTERM bit is set, the DAC1_AMUTER condition is masked, meaning that its
occurrence will not affect the INT pin.
6.19.5 Serial Port 2 Clock Error Mask (SP2_CLKERRM)
This bit serves as a mask for the serial port 2 clock error interrupt source. If this bit is cleared, the
SP2_CLKERR interrupt is unmasked, meaning that if the SP2_CLKERR bit is set, the INT pin will go active according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If
the SP2_CLKERRM bit is set, the SP2_CLKERR condition is masked, meaning that its occurrence will
not affect the INT pin.
6.19.6 Serial Port 1 Clock Error Mask (SP1_CLKERRM)
This bit serves as a mask for the serial port 1 clock error interrupt source. If this bit is cleared, the
SP1_CLKERR interrupt is unmasked, meaning that if the SP1_CLKERR bit is set, the INT pin will go active according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If
the SP1_CLKERRM bit is set, the SP1_CLKERR condition is masked, meaning that its occurrence will
not affect the INT pin.
60
DS721A6
CS42324
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM)
This bit serves as a mask for the ADC positive overflow interrupt source. If this bit is cleared, the
ADC_OVFLP interrupt is unmasked, meaning that if the ADC_OVFLP conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the ADC_OVFLPM bit is set, the ADC_OVFLP condition is masked,
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM)
This bit serves as a mask for the ADC negative overflow interrupt source. If this bit is cleared, the
ADC_OVFLN interrupt is unmasked, meaning that if the ADC_OVFLN conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” register on page 59. If the ADC_OVFLNM bit is set, the ADC_OVFLN condition is masked,
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
6.20
Interrupt Status (Address 18h) (Read Only)
7
DAC2_
AMUTEL
6
DAC2_
AMUTER
5
DAC1_
AMUTEL
4
DAC1_
AMUTER
3
SP2_
CLKERR
2
SP1_
CLKERR
1
ADC_
OVFLP
0
ADC_
OVFLN
This register defaults to 00h and is read only. If the INT pin is active, reading this register clears the interrupt
condition.
Bit Settings
0
1
Bit in Interrupt Register
Interrupt has not occurred since the last read of this register.
Interrupt has occurred since the last read of this register.
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL)
This bit is read only. When set, indicates that DAC2 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the left channel of SDIN2, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC2_AMUTELM bit is cleared.
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER)
This bit is read only. When set, indicates that DAC2 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN2, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC2_AMUTERM bit is cleared.
DS721A6
61
CS42324
6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL)
This bit is read only. When set, indicates that DAC1 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive samples of zeroes or ones on the left channel of SDIN1, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC1_AMUTELM bit is cleared.
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL)
This bit is read only. When set, indicates that DAC1 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN1, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC1_AMUTERM bit is cleared.
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR)
This bit is read only. When set, indicates that Serial Port 2 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK2, SCLK2, an
MCLKx/LRCK2 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if SP2_CLKERRM bit is cleared.
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR)
This bit is read only. When set, indicates that Serial Port 1 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK1, SCLK1, an
MCLKx/LRCK1 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if SP1_CLKERRM bit is cleared.
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP)
This bit is read only. When set, indicates that a positive over-range condition occurred anywhere in the
CS42324 ADC signal path and has ADC data has been clipped to positive full scale since the last read of
this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” on
page 59 and the status of this bit if ADC_OVFLPM bit is cleared. To determine the current overflow state
of the ADC use the OVFL pin.
62
DS721A6
CS42324
6.20.8 ADC Negative Overflow Interrupt Bit (ADC_OVFLN)
This bit is read only. When set, indicates that a negative over-range condition occurred anywhere in the
CS42324 ADC signal path and has ADC data has been clipped to negative full scale since the last read
of this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this
register.
The INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” on
page 59 and the status of this bit if ADC_OVFLNM bit is cleared. To determine the current overflow state
of the ADC use the OVFL pin.
DS721A6
63
CS42324
7. GROUNDING AND POWER SUPPLY DECOUPLING
As with any high-resolution converter, the CS42324 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 7 on page 26 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system
logic supply (VL) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices
should be powered from VD.
Power supply decoupling capacitors should be as near to the CS42324 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+, VCM_ADC, VBIAS,
VCMBUF, and VCMDAC pins in order to avoid unwanted coupling into the modulators. The FILT+, VCM_ADC,
VBIAS, VCMBUF, and VCMDAC decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from each pin to GND. The CS42324 evaluation board demonstrates the optimum layout and power
supply arrangements. To minimize digital noise, connect the CS42324 digital outputs only to CMOS inputs.
64
DS721A6
CS42324
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Amplitude (dB)
Amplitude (dB)
8. ADC FILTER PLOTS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
Frequency (norm alized to Fs)
0.10
0.08
-2
0.06
Amplitude (dB)
Amplitude (dB)
0
-3
-4
-5
-6
-7
0.51
-0.04
-0.10
0.00 0.05
0.52
Frequency (norm alized to Fs)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (norm alized to Fs)
Figure 27. Double-Speed Mode Stopband Rejection
DS721A6
0.15
0.20 0.25 0.30 0.35 0.40 0.45 0.50
Figure 26. Single-Speed Mode Passband Ripple
Amplitude (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.1
0.10
Frequency (norm alized to Fs)
Figure 25. Single-Speed Mode Transition Band (Detail)
Amplitude (dB)
0.00
-0.08
0.0
0.60
-0.02
-0.06
0.50
0.58
0.02
-9
0.49
0.56
0.04
-8
0.48
0.54
Figure 24. Single-Speed Mode Transition Band
-1
0.47
0.52
Frequency (norm alized to Fs)
Figure 23. Single-Speed Mode Stopband Rejection
-10
0.46
0.46 0.48 0.50
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
0.40 0.42 0.44
0.46 0.48 0.50
0.52
0.54
0.56
0.58
0.60
Frequency (norm alized to Fs)
Figure 28. Double-Speed Mode Transition Band
65
0
0.10
-1
0.08
-2
0.06
Amplitude (dB)
Amplitude (dB)
CS42324
-3
-4
-5
-6
-7
0.02
0.00
-0.02
-0.04
-8
-0.06
-9
-0.08
-10
0.46
0.47
0.48
0.49
0.50
0.51
0.52
Frequency (norm alized to Fs)
Figure 29. Double-Speed Mode Transition Band (Detail)
66
0.04
-0.10
0.00 0.05
0.10
0.15
0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Figure 30. Double-Speed Mode Passband Ripple
DS721A6
CS42324
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
9. DAC DIGITAL FILTER RESPONSE PLOTS
−60
−60
−80
−80
−100
−100
−120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
−120
0.4
1
Figure 31. Single-Speed Stopband Rejection
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 32. Single-Speed Transition Band
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
Figure 33. Single-Speed Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
60
80
80
100
100
120
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
Figure 35. Double-Speed Stopband Rejection
DS721A6
0.1
0
20
0.4
0.05
Figure 34. Single-Speed Passband Ripple
0
120
0
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 36. Double-Speed Transition Band
67
CS42324
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
0
Figure 37. Double-Speed Transition Band (detail)
20
40
40
Amplitude (dB)
Amplitude (dB)
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
60
60
80
80
100
100
120
0.2
0.1
Figure 38. Double-Speed Passband Ripple
0
120
0.05
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
0.2
Figure 39. Quad-Speed Stopband Rejection
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 40. Quad-Speed Transition Band
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 41. Quad-Speed Transition Band (detail)
68
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 42. Quad-Speed Passband Ripple
DS721A6
CS42324
10.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS721A6
69
CS42324
11.PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
MIN
A
--A1
0.002
B
0.007
D
0.343
D1
0.272
E
0.343
E1
0.272
e*
0.016
L
0.018
µ
0.000°
* Nominal pin pitch is 0.50 mm
INCHES
NOM
MAX
MIN
0.055
0.063
--0.004
0.006
0.05
0.009
0.011
0.17
0.354
0.366
8.70
0.28
0.280
6.90
0.354
0.366
8.70
0.28
0.280
6.90
0.020
0.024
0.40
0.24
0.030
0.45
4°
7.000°
0.00°
*Controlling dimension is mm.
MILLIMETERS
NOM
MAX
1.40
1.60
0.10
0.15
0.22
0.27
9.0 BSC
9.30
7.0 BSC
7.10
9.0 BSC
9.30
7.0 BSC
7.10
0.50 BSC
0.60
0.60
0.75
4°
7.00°
*JEDEC Designation: MS022
THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters
Package Thermal Resistance
70
multi-layer
dual-layer
Symbol
θJA
θJA
θJC
Min
-
Typ
48
65
15
Max
-
Units
°C/Watt
°C/Watt
°C/Watt
DS721A6
CS42324
12.ORDERING INFORMATION
Product
Description
Package
2-In, 4-Out Audio
CS42324 CODEC with 2Vrms
LQFP
Analog I/O
2-In, 4-Out Audio
CS42324 CODEC with 2Vrms
LQFP
Analog I/O
CDB42324
Evaluation Board
Pb-Free
Grade
Temp Range
Container
Order #
Yes
Commercial -40°C to +85° C
Tray
CS42324-CQZ
Yes
Automotive -40°C to +105° C
Tray
CS42324-DQZ
-
CDB42324
-
-
-
13.REVISION HISTORY
Release
A5
A6
Changes
Changed Title
Corrected SCL/CCLK pin description (Pin 2) in the Pin Description table on page 8.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus")
believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS"
without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that
information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,
including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use
of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of
Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such
as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
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