EN39SL801 EN39SL801 8 Megabit (512K x 16-bit) Flash Memory With 4Kbytes Uniform Sector, CMOS 1.8 Volt-only FEATURES • - • Single power supply operation - Full voltage range: 1.65-1.95 volt for read and write operations. - Ideal for battery-powered applications. • High performance - Access times as fast as 70 ns High performance program/erase speed Word program time: 8µs typical Sector erase time: 90ms typical Block erase time: 180ms typical Chip erase time: 2s typical • JEDEC Standard Embedded Erase and Program Algorithms • Low power consumption (typical values at 5 MHz) - 5 mA typical active read current - 15 mA typical program/erase current - 0.2 μA typical standby current • JEDEC standard DATA# polling and toggle bits feature • Single Sector, Block and Chip Erase • Erase Suspend / Resume modes: Read or program another Sector/Block during Erase Suspend Mode • Uniform Sector Architecture: - 256 sectors of 2-Kword - 16 blocks of 32-Kword - Any sector or block can be erased individually • Low Vcc write inhibit < 1.2V • Minimum 100K endurance cycle • Block protection: - Hardware locking of blocks to prevent program or erase operations within individual blocks • Package Options - 48-ball 6mm x 8mm TFBGA - 48-ball 4mm x 6mm WFBGA • Chip Unprotect Mode • Industrial temperature and Automotive temperature Range GENERAL DESCRIPTION The EN39SL801 is an 8-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 524,288 words. Any word can be programmed typically in 8µs.The EN39SL801 features 1.8V voltage read and write operation, with access time as fast as 70ns to eliminate the need for WAIT statements in high-performance microprocessor systems. The EN39SL801 has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#) controls, which eliminate bus contention issues. This device is designed to allow either single Sector/Block or full chip erase operation, where each block can be individually protected against program/erase operations or chip unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 CONNECTION DIAGRAMS TFBGA Top View, Balls Facing Down This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 WFBGA Top View, Balls Facing Down A6 A2 A5 A1 A4 A0 A3 CE# A2 VSS B6 A4 B5 A3 B4 A5 B3 DQ8 B2 OE# B1 C6 A6 C5 A7 D6 A17 E6 NC F6 G6 NC NC Reset# H5 D5 NC NC C4 A18 C1 H2 D2 NC NC D1 E1 F1 G1 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 3 DQ2 DQ12 H1 DQ13 K4 K3 DQ5 J1 DQ14 A15 L3 DQ11 J2 A14 L4 A12 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 L5 A13 A10 DQ4 VCC DQ1 K5 J5 J3 DQ10 DQ9 A11 A9 A8 C3 C2 K6 J6 J4 DQ3 DQ0 WE# H6 K2 A16 L2 DQ6 K1 DQ7 L1 DQ15 VSS www.eonssi.com EN39SL801 Table 1. PIN DESCRIPTION Pin Name A0-A18 Figure 1. LOGIC DIAGRAM EN39SL801 Function Addresses DQ0 – DQ15 A0 - A18 DQ0-DQ15 16 Data Inputs/Outputs CE# CE# Chip Enable OE# Output Enable WE# Write Enable RESET# Hardware Reset Pin Vcc Supply Voltage (1.65-1.95V) Vss Ground NC Not Connected to anything OE# WE# RESET# This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 4 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 2. Uniform Sector / Block Architecture (Block 8 ~ 15) Address Range Block Sector Size (Kwords) Sector (X16) 0 0 0 1 1 1 1 0 223 06F800h-06FFFFh 2 1 1 0 1 1 1 1 1 0 1 1 0 0 191 05F800h-05FFFFh 2 1 0 1 1 1 1 1 1 0 0 1 1 1 0 0 0 159 04F800h-04FFFFh 2 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 …. 0 0 0 0 …. 0 1 1 1 …. 1 2 2 2 …. 2 …. 048000h-0487FFh 047800h-047FFFh 047000h-0477FFh 046800h-046FFFh …. 144 143 142 141 …. …. 0 …. 0 …. 1 …. 0 …. 1 …. 2 …. 050000h-0507FFh …. 160 …. …. 0 1 …. 0 0 …. 1 1 …. 1 0 …. 0 1 …. 1 2 …. 2 057800h-057FFFh …. 058000h-0587FFh 175 …. 176 …. …. 0 …. 0 …. 0 …. 0 …. 1 …. 1 …. 2 …. 060000h-0607FFh …. 192 …. …. 0 1 …. 0 1 …. 0 0 …. 1 0 …. 0 1 …. 1 1 …. 1 2 …. 2 067800h-067FFFh …. 068000h-0687FFh 207 …. 208 …. …. 0 …. 0 …. 0 …. 0 …. 1 …. 1 …. 1 …. 2 …. 070000h-0707FFh …. 224 …. …. 0 0 …. 1 1 …. 1 1 …. 1 1 …. 1 2 …. 2 077800h-077FFFh …. 078000h-0787FFh 239 …. 240 …. 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 …. 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 …. 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 …. 8 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 …. 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 …. 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 …. 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 …. 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 …. 13 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 …. 14 07F800h-07FFFFh 07F000h-07F7FFh 07E800h-07EFFFh 07E000h-07E7FFh 07D800h-07DFFFh 07D000h-07D7FFh 07C800h-07CFFFh 07C000h-07C7FFh 07B800h-07BFFFh 07B000h-07B7FFh 07A800h-07AFFFh 07A000h-07A7FFh 079800h-079FFFh 079000h-0797FFh 078800h-078FFFh …. 15 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 A18 A17 A16 A15 A14 A13 A12 A11 130 041000h-0417FFh 2 1 0 0 0 0 0 1 0 129 040800h-040FFFh 2 1 0 0 0 0 0 0 1 128 040000h-0407FFh 2 1 0 0 0 0 0 0 0 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 2. Uniform Sector / Block Architecture (Block 0 ~ 7) Address Range Blaok Sector Size (Kwords) Sector 0 1 1 1 1 1 0 1 0 1 …. …. …. …. …. …. …. …. …. 114 113 039000h-0397FFh 038800h-038FFFh 2 2 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 …. …. …. …. …. 030000h-0307FFh 2 0 1 1 0 0 0 0 0 95 02F800h-02FFFFh 2 0 1 0 1 1 1 1 1 …. …. …. …. …. 96 …. 1 …. 0 1 …. 0 1 …. 0 1 …. 0 0 …. 1 1 …. 1 1 …. 1 0 …. 0 2 …. 2 037800h-037FFFh …. 038000h-0387FFh 111 …. 112 …. …. …. …. …. 64 020000h-0207FFh 2 0 1 0 0 0 0 0 0 63 01F800h-01FFFFh 2 0 0 1 1 1 1 1 1 …. …. …. …. …. 0 1 …. 0 1 …. 0 1 …. 0 1 …. 1 0 …. 0 0 …. 1 1 …. 0 0 …. 2 2 …. 028000h-0287FFh 027800h-027FFFh …. 80 79 …. …. …. …. 32 010000h-0107FFh 2 0 0 1 0 0 0 0 0 31 00F800h-00FFFFh 2 0 0 0 1 1 1 1 1 …. …. …. 0 1 …. 0 1 …. 0 1 …. 0 1 …. 1 0 …. 1 1 …. 0 0 …. 0 0 …. 2 2 …. 018000h-0187FFh 017800h-017FFFh …. 48 47 …. 1 1 1 1 …. 2 1 1 1 …. 3 1 1 1 …. 4 1 1 1 …. 5 0 0 0 …. 6 2 2 2 …. 7 03F800h-03FFFFh 03F000h-03F7FFh 03E800h-03EFFFh …. 127 126 125 A18 A17 A16 A15 A14 A13 A12 A11 …. (X16) 16 008000h-0087FFh 2 0 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 007800h-007FFFh 007000h-0077FFh 006800h-006FFFh 006000h-0067FFh 005800h-005FFFh 005000h-0057FFh 004800h-004FFFh 004000h-0047FFh 003800h-003FFFh 003000h-0037FFh 002800h-002FFFh 002000h-0027FFh 001800h-001FFFh 001000h-0017FFh 000800h-000FFFh 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 000000h-0007FFh 2 0 0 0 0 0 0 0 0 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 PRODUCT SELECTOR GUIDE Product Number Speed Option EN39SL801 Full Voltage Range: Vcc=1.65 – 1.95 V -70 90 Max Access Time, ns (tacc) 70 90 Max CE# Access, ns (tce) 70 90 Max OE# Access, ns (toe) 30 40 BLOCK DIAGRAM Vcc Vss DQ0-DQ15 Blo ck Protect Switches Erase Voltage Generator Input/Output Buffers State Co ntrol WE# RESET# Command Register Program Voltage Generator Chip Enable Output Enable Logic CE# OE# Vcc Detecto r Timer Ad dress Latch STB STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0-A18 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 3. OPERATING MODES 8M FLASH USER MODE TABLE Operation Read Write CMOS Standby Output Disable Hardware Reset Temporary Block Unprotect CE# L L Vcc ± 0.2V L X OE# L H X H X WE# H L X H X RESET# H H Vcc± 0.2V H L A0-A18 AIN AIN X X X DQ0-DQ15 DOUT DIN High-Z High-Z High-Z X X X VID AIN DIN Block Protect L H L VID Chip Unprotect L H L VID Block Address, A6 = L, A1 = H, A0 = L Block Address, A6 = L, A1 = H, A0 = L DIN DIN L=logic low= VIL, H=Logic High= VIH, VID =10.0 ± 1.0V, X=Don’t Care (either L or H, but not floating!), DIN=Data In, DOUT=Data Out, AIN=Address In Notes: 1. Please refer to “Block Group Protection and Chip Unprotection “, Flowchart 7a and Flowchart 7b. Table 4. DEVICE IDENTIFICTION (Autoselect Codes) 8M FLASH MANUFACTURER/DEVICE ID TABLE Description CE# OE# WE# A18 to A15 A14 to A10 A9 2 A7 A6 A5 to A2 A1 A0 DQ8 to DQ15 X L X L L X X L X L H 27h 1 Manufacturer ID: Eon L L H X X VID Device ID L L H X X VID Block Protection Verification A8 L L H BA X VID H L X X X L X H L X X DQ7 to DQ0 1Ch 7Fh 3Fh 01h (Protected) 00h (Unprotected) Note: 1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. 2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 USER MODE DEFINITIONS Standby Mode The EN39SL801 has a CMOS-compatible standby mode, which reduces the current to < 0.2µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.2. RESET# pin must also be at CMOS input levels. If CE# and RESET# are held at VIH, but not within VCC ± 0.2V, the device will be in the standby modes, but the standby current will be greater. The outputs are in a high-impedance state independent of the OE# input. Read Mode The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details. Output Disable Mode When the OE# pin is at a logic high level (VIH), the output from the EN39SL801 is disabled. The output pins are placed in a high impedance state. Auto Select Identification Mode The autoselect mode provides manufacturer and device identification, and block protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID ( 9.0 V to 11.0 V) on address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying block protection, the block address must appear on the appropriate highest order address bits. Refer to the corresponding block Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. Write Mode Write operations, including programming data and erasing sectors/blocks of memory, require the host system to write a command or command sequence to the device. Write cycles are initiated by placing the word address on the device’s address inputs while the data to be written is input on DQ [15:0] in Word Mode. The host system must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place. All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to provide further controls or timings. The device automatically provides internally generated program / erase pulses and verifies the programmed /erased cells’ margin. The host system can detect This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 completion of a program or erase operation by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. The ‘Command Definitions’ section of this document provides details on the specific device commands implemented in the EN39SL801. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at Vss±0.3 V, the device draws CMOS standby current (Icc2). If RESET# is held at VIL but not within Vss±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Block Protection and Chip Unprotection The hardware block protection feature disables both program and erase operations in any block. The hardware block unprotection feature re-enables both program and erase operations in previously protected blocks. There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings. When doing Chip Unprotect, all the other blocks should be protected first. The second method is meant for programming equipment. This method requires VID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN39SL801 Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc. Temporary Block Unprotect Start This feature allows temporary unprotection of previously protected block groups to change data while in-system. The Block Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected blocks can be programmed or erased by simply selecting the Block addresses. Once is removed from the RESET# pin, all the previously protected blocks are protected again. See accompanying figure and timing diagrams for more details. Notes: 1. All protected blocks unprotected. 2. Previously protected blocks protected again. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 Reset#=VID (note 1) Perform Erase or Program Operations Reset#=VIH Temporary Block Unprotect Completed (note 2) ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is independent of the CE#, WE# and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output is latched and always available to the system. Icc4 in the DC Characteristics table represents the automatic sleep mode current specification. COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-7. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–7. The system must write the reset command to return the device to the autoselect mode. Table 5. CFI Query Identification String (1) Adresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string “QRY” Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 1. Refer to CFI publication 100 for more details. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 6. System Interface String Addresses (Word Mode) Data 1Bh 0016h 1Ch 0020h 1Dh 1Eh 1Fh 0000h 0000h 0004h 20h 0000h 21h 22h 23h 24h 25h 000Ah 0000h 0005h 0000h 0004h 26h 0000h Description Vcc Min (write /erase) DQ7-DQ4: volts, DQ3 –DQ0: 100 millivolts Vcc Max (write /erase) DQ7-DQ4: volts, DQ3 –DQ0: 100 millivolts Vpp Min. voltage (00h = no Vpp pin present) Vpp Max. voltage (00h = no Vpp pin present) N Typical timeout per single word program 2 μs N Typical timeout for Min, size buffer write 2 μs (00h = not supported) N Typical timeout per individual sector/block erase 2 ms N Typical timeout for full chip erase 2 ms (00h = not supported) N Max. timeout for word write 2 times typical N Max. timeout for buffer write 2 times typical N Max. timeout per individual sector/block erase 2 times typical N Max timeout for full chip erase 2 times typical (00h = not supported) Table 7. Device Geometry Definition Addresses (Word mode) 27h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h Data 0014h 0000h 0000h 0002h 00FFh 0000h 0010h 0000h 000Fh 0000h 0000h 0001h Description 20 Device Size = 2 byte (14h = 20; 2 = 1MByte) N Max. number of byte in multi-byte write = 2 (00h = not supported) Number of Erase Sector/Block Regions within device Erase Sector Region 1 Information (y+1 = Number of sectors; z x 256B = sector size) y = 255 + 1 = 256 sectors (00FFh = 255) z = 16 x 256 Bytes = 4 KByte/sector (0010h = 16) Erase Block Region 2 Information (y+1 = Number of blocks; z x 256B = block size) y = 15 + 1 = 16 blocks (000Fh = 15) z = 256 x 256 Bytes = 64 KByte/block (0100h = 256) N This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise. Low VCC Write Inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO. Write Pulse “Glitch” protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read. Power-up Write Inhibit During power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 13 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 COMMAND DEFINITIONS The operations of EN39SL801 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Block Protection, Program, Sector/Block Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode. Table 8. EN39SL801 Command Definitions Command Sequence Cycles Bus Cycles st nd rd 2 6 Cycle Addr Data Cycle Addr Data RD Reset 1 xxx F0 Manufacturer ID 4 555 AA 2AA 55 555 Device ID 4 555 AA 2AA 55 555 Block Protect Verify 4 555 AA 2AA 55 Program 4 555 AA 2AA Sector Erase 6 555 AA Block Erase 6 555 AA Chip Erase 6 555 AA Autoselect RA 1 xxx B0 1 xxx 30 CFI Query 1 55 98 th 5 Cycle Addr Data 1 Erase Resume th 4 Cycle Addr Data Read Erase Suspend th 3 Cycle Addr Data 1 Cycle Addr Data 000 7F 100 1C 90 X01 273F 555 90 (BA) X02 XX00 55 555 A0 PA PD 2AA 55 555 80 555 AA 2AA 55 SA 30 2AA 55 555 80 555 AA 2AA 55 BA 50 2AA 55 555 80 555 AA 2AA 55 555 10 90 XX01 Address and Data values indicated in hex RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PA BA = Block Address: address of the Block to be erased or verified. Address bits A18-A15 uniquely select any Block SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A11 uniquely select any Sector Reading Array Data The device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors/blocks, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 14 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’tcare for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a block is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires VID on address bit A9 and is intended for PROM programmers. Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence. The system must write the reset command to exit the autoselect mode and return to reading array data. Programming Command Programming the EN39SL801 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#, whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode. Chip Erase Command Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Chip Erase algorithm are ignored. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 15 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip, Sector/Block Erase Operation Timings for timing waveforms. Sector/Block Erase Command Sequence Sector/Block erase is a six bus cycle operation. The sector/block erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector/block to be erased, and the sector/block erase command. The Command Definitions table shows the address and data requirements for the sector/block erase command sequence. Once the sector/block erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector/Block Erase Operations Timing diagram for timing waveforms. Erase Suspend / Resume Command The Erase Suspend command allows the system to interrupt a sector/block erase operation and then read data from, or program data to, any sector/block not selected for erasure. This command is valid only during the sector/block erase operation. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command. When the Erase Suspend command is written during a sector/block erase operation, the device requires a maximum of 20 µs to suspend the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector/block not selected for erasure. (The device “erase suspends” all sector/blocks selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors/blocks produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector/block is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors/blocks. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The Autoselect command is not supported during Erase Suspend Mode. The system must write the Erase Resume command (address bits are don’t-care) to exit the erase suspend mode and continue the sector/block erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 16 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 WRITE OPERATION STATUS DQ7: DATA# Polling The EN39SL801 provides DATA# polling on DQ7 to indicate the status of the embedded operations. The DATA# Polling feature is active during the embedded Programming, Sector/Block Erase, Chip Erase, and Erase Suspend. (See Table 6) When the embedded Programming is in progress, an attempt to read the device will produce the complement of the data last written to DQ7. Upon the completion of the embedded Programming, an attempt to read the device will produce the true data written to DQ7. For the embedded Programming, DATA# polling is valid after the rising edge of the fourth WE# or CE# pulse in the four-cycle sequence. When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output during the read cycles. For Chip Erase, the DATA# polling is valid after the rising edge of the sixth WE# or CE# pulse in the six-cycle sequence. DATA# polling is valid after the last rising edge of the WE# or CE# pulse for chip erase or sector/block erase. DATA# Polling must be performed at any address within a sector/block that is being programmed or erased and not a protected sector/block. Otherwise, DATA# polling may give an inaccurate result if the address used is in a protected block. Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the output enable (OE#) is low. This means that the device is driving status information on DQ7 at one instant of time and valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status of valid data. Even if the device has completed the embedded operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on DQ0-DQ7 will be read on the subsequent read attempts. The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing diagram is shown in Figure 8. DQ6: Toggle Bit I The EN39SL801 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the embedded programming and erase operations. (See Table 6) During an embedded Program or Erase operation, successive attempts to read data from the device at any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During embedded Programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after the rising edge of the sixth WE# pulse for sector/block erase or chip erase. In embedded Programming, if the block being written to is protected, DQ6 will toggles for about 2 μs, then stop toggling without the data in the block having changed. In Sector/Block Erase or Chip Erase, if all selected blocks are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read mode without changing data in all protected blocks. The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown in Figure 9. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 17 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the DQ6 is toggling after detecting a “1” on DQ5. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector/Block Erase Timer After writing a sector/block erase command sequence, the output on DQ3 can be used to determine whether or not an erase operation has begun. (The sector/block erase timer does not apply to the chip erase command.) When sector/block erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector/block erase command sequences so it is not very meaningful since it immediately shows as a “1” after the first 30h command. Future devices may support this feature. DQ2: Erase Toggle Bit II The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector/block is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector/block is erasesuspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors/blocks that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector/block is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors/blocks are selected for erasure. Thus, both status bits are required for sector/block and mode information. Refer to the following table to compare outputs for DQ2 and DQ6. Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 18 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Flowchart 6). Write Operation Status Standar d Mode Erase Suspend Mode Operation DQ7 (note2) DQ6 DQ5 (note1) DQ3 DQ2 (note2) Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle Embedded Erase Algorithm 0 Toggle 0 1 Toggle 1 No Toggle 0 N/A Toggle Data Data Data Data Data DQ7# Toggle 0 N/A N/A Reading within Erase Suspended Sector/Block Reading within Non-Erase Suspended Sector/Block Erase-Suspend Program 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5:Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 19 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 9. Status Register Bits DQ Name Logic Level DQ7# Definition Erase Complete or erase Sector/Block in Erase suspend Erase On-Going Program Complete or data of non-erase Sector/Block during Erase Suspend Program On-Going ‘-1-0-1-0-1-0-1-’ Erase or Program On-going DQ6 Read during Erase Suspend ‘-1-1-1-1-1-1-1-‘ Erase Complete ‘1’ ‘0’ ‘1’ ‘0’ Program or Erase Error Program or Erase On-going Erase operation start Erase timeout period on-going Chip Erase, Sector/Block Erase or Erase suspend on currently addressed Sector/Block. (When DQ5=1, Erase Error due to currently addressed Sector/Block. Program during Erase Suspend on-going at current address ‘1’ 7 6 DATA# POLLING TOGGLE BIT 5 TIME OUT BIT 3 ERASE TIME OUT BIT 2 TOGGLE BIT ‘0’ DQ7 ‘-1-0-1-0-1-0-1-’ Erase Suspend read on non Erase Suspend Sector/Block DQ2 Notes: DQ7 DATA# Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive reads output complementary data on DQ6 while programming or Erase operation are on-going. DQ5 Time Out Bit: set to “1” if failure in programming or erase DQ3 Sector/Block Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES). DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector/Block This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 20 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 EMBEDDED ALGORITHMS Flowchart 1. Embedded Program START Write Program Comma nd Sequence (shown below) Data# P oll Device Verify Data? No Yes Increment Address Last No Address? Yes Programming Done Flowchart 2. Embedded Program Command Sequence See the Command Definitions section for more information on WORD mode. 555H / AAH 2AAH / 55H 555H / A0H PROGRAM ADDRESS / PROGRAM DATA This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 21 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Flowchart 3. Embedded Erase START Write Erase Command Sequence Data Poll from System or Toggle Bit successfully completed Data =FFh? No Yes Erase Done Flowchart 4. Embedded Erase Command Sequence See the Command Definitions section for more information on WORD mode. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 22 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Flowchart 5. DATA# Polling Algorithm Start Read Data DQ7 = Data? Yes No No DQ5 = 1? Yes Read Data (1) Notes: (1) This second read is necessary in case the first read was done at the exact instant when the status data was in transition. DQ7 = Data? Yes No Fail Pass Start Flowchart 6. Toggle Bit Algorithm Read Data twice DQ6 = Toggle? No Yes No DQ5 = 1? Yes Read Data twice (2) DQ6 = Toggle? Notes: (2) This second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. No Yes Fail 23 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 Pass www.eonssi.com EN39SL801 Flowchart 7a. In-System Block Protect Flowchart START PLSCNT = 1 RESET# = VID Wait 1 μs No First Write Cycle = 60h? Temporary Block Unprotect Mode Yes Set up block group address To Protect: Write 60h to block addr with A6 = 0, A1 = 1, A0 = 0 Wait 150 μs To Verify: Write 40h to block address with A6 = 0, A1 = 1, A0 = 0 Increment PLSCNT Reset PLSCNT = 1 Wait 0.4 μs Read from block address with A6 = 0, A1 = 1, A0 = 0 No PLSCNT = 25? No Data = 01h? Yes Yes Device failed Protect another block? Yes No Remove VID from RESET# Write reset command Block Protect Algorithm Block Protect complete This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Flowchart 7b. In-System Chip Unprotect Flowchart START PLSCNT = 1 Protect all blocks: The indicated portion of the block protect algorithm must be performed for all unprotected blocks prior to issuing the first block unprotect address (see Diagram 7a.) RESET# = VID Wait 1 μs No Temporary Block Unprotect Mode First Write Cycle = 60h? tVT Yes No All blocks protected? Yes Set up first block address Chip Unprotect: Write 60H to block address with A6 = 1, A1 = 1, A0 = 0 Wait 15 ms Increment PLSCNT Verify Chip Unprotect: Write 40h to block address with A6 = 1, A1 = 1, A0 =0 Wait 0.4 μs No PLSCNT = 1000? Read from block address with A6 = 1, A1 = 1, A0 = 0 No Yes Yes Device failed Set up next block address Data = 00h? No Last block verified? Yes Chip Unprotect Algorithm Remove VID from RESET# This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 25 Write reset command Chip Unprotect complete ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 10. DC Characteristics (Ta = - 40°C to 85°C or - 40°C to 125°C; VCC = 1.65-1.95V) Symbol Parameter Test Conditions ILI Input Leakage Current ILO ICC1 Max Unit 0V≤ VIN ≤ Vcc ±3 µA Output Leakage Current 0V≤ VOUT ≤ Vcc ±3 µA Active Read Current CE# = VIL, OE# = VIH, F=5MHz CE# = RESET# = Vcc, (Note 1) CE# = RESET# = Vcc (Note 1) CE# = RESET# = Vcc (Note 1) CE# = RESET# = Vss ± 0.2 V (Note 1) Program or Erase in progress 5 10 mA 0.2 5.0 µA 0.2 20 µA 0.2 5.0 µA 0.2 20 µA 15 25 mA 0.2 5.0 µA 0.2 20 µA Supply Current (Standby) ICC2 Supply Current (Standby) For Automotive (-40°C to +125°C) VCC , Reset Current ICC3 ICC4 VCC , Reset Current For Automotive (-40°C to +125°C) Supply Current (Program or Erase) VIH = Vcc ± 0.2 V Automatic Sleep Mode ICC5 Min VIL = Vss ± 0.2 V Automatic Sleep Mode For Automotive (-40°C to +125°C) VIH = Vcc ± 0.2 V VIL = Vss ± 0.2 V VIL Input Low Voltage -0.5 VIH Input High Voltage 0.7 x Vcc VOL Output Low Voltage IOL = 100 μA VOH Output High Voltage IOH = -100 μA, VID A9 Voltage (Electronic Signature) IID A9 Current (Electronic Signature) VLKO Supply voltage (Erase and Program lock-out) Typ 0.3 x VCC Vcc + 0.3 0.1 Vcc 0.1 9.0 V V V V 10.0 A9 = VID 1.2 11.0 V 50 µA 1.5 V Notes 1. RESET# pin input buffers are always enabled so that they draw power if not at full CMOS supply voltages. 2. Maximum ICC specifications are tested with Vcc = Vcc max. B B This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Test Conditions Test Specifications Test Conditions -70 Output Load Capacitance, CL -90 Unit 30 pF Input Rise and Fall times 5 ns Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 0.0-2.0 V 1/2 Vcc V 1/2 Vcc V This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 AC CHARACTERISTICS Hardware Reset (Reset#) (Ta = - 40°C to 85°C or - 40°C to 125°C; VCC = 1.65-1.95V) Parameter Std tRP1 tRP2 tRH tREADY1 tREADY2 Description RESET# Pulse Width (During Embedded Algorithms) RESET# Pulse Width (NOT During Embedded Algorithms) Reset# High Time Before Read Reset# Pin Low (During Embedded Algorithms) to Read or Write Reset# Pin Low (NOT During Embedded Algorithms) to Read or Write Test Setup Min Min Min Speed -70 -90 10 500 50 Max 20 us Max 500 ns Unit us ns ns Figure 2. AC Waveforms for RESET# Reset# Timings This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 28 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 11. AC CHARACTERISTICS (Ta = - 40°C to 85°C or - 40°C to 125°C; VCC = 1.65-1.95 V) Read-only Operations Characteristics Parameter Symbols Test Setup Description JEDEC Standard tAVAV tRC Read Cycle Time Speed Options -70 -90 Unit Min 70 90 ns Max 70 90 ns Max 70 90 ns 30 40 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL tELQV tCE Chip Enable To Output Delay OE# = VIL tGLQV tOE Output Enable to Output Delay Max tEHQZ tDF Chip Enable to Output High Z Max 20 ns tGHQZ tDF Output Enable to Output High Z Max 20 ns tAXQX tOH Output Hold Time from Addresses, CE# or OE#, whichever occurs first Min 0 ns tOEH Output Enable Hold Time Read Min 0 ns Toggle and Data# Polling Min 10 ns Notes: 1. High Z is Not 100% tested. 2. For – 70, 90 Vcc =1.65 – 1.95V Output Load : 30pF Input Rise and Fall Times: 5ns Input Rise Levels: 0.0 V to Vcc Timing Measurement Reference Level, Input and Output: 1/2 Vcc Figure 3. AC Waveforms for READ Operations tBRCB Addresses Addresses Stable tBACC CE# OE# WE# tBDF tBOEB tBOEHB tBCEB Outputs tBOH HIGH Z This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Output Valid 29 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 HIGH Z www.eonssi.com EN39SL801 Table 12. AC CHARACTERISTICS (Ta = - 40°C to 85°C or - 40°C to 125°C; VCC = 1.65-1.95V) Write (Erase/Program) Operations Parameter Symbols Speed Options Description JEDEC Standard -70 -90 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 ns tDVWH tDS Data Setup Time Min tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns Read Recovery Time before Write (OE# High to WE# Low) Min 0 ns 30 40 ns tGHWL tGHWL tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 45 ns tWHDL tWPH Write Pulse Width High Min 20 25 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 8 µs Sector Typ 0.09 s Block Typ 0.18 s Chip Typ 2 s Vcc Setup Time (Note 1) Min 50 µs Voltage Transition Time Min 500 ns Block Pulse Width Min 100 μs Chip Unprotection Pulse Width Min 10 ms Min Voltage setup time Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information. 4 μs tWHWH2 tWHWH2 tVCS tVT tWPP1 tWPP2 tST Erase Operation (Note 2) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 30 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 13. AC CHARACTERISTICS (Ta = - 40°C to 85°C or - 40°C to 125°C; VCC = 1.65-1.95V) Write (Erase/Program) Operations Alternate CE# Controlled Writes Parameter Symbols JEDEC Speed Options Description Standard -70 -90 Unit 70 90 ns tAVAV tWC Write Cycle Time (Note 1) Min tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time before Write (OE# High to CE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 8 µs Sector Typ 0.09 s Block Typ 0.18 s Chip Typ. 2 s tWHWH2 tWHWH2 Erase Operation (Note 2) 30 40 35 45 ns ns Notes: 1. Not 100% tested. 2. See Erase and Programming Performance for more information. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 31 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Table 14. ERASE AND PROGRAMMING PERFORMANCE Typ Limits Max Unit Sector Erase Time 0.09 0.4 sec Block Erase Time 0.18 2 sec Chip Erase Time 2 20 sec Word Programming Time 8 200 µs Chip Programming Time 4 5.5 sec Erase/Program Endurance 100K Parameter cycles Comments Excludes 00H programming prior to erasure Excludes system level overhead Minimum 100K cycles Table 15. DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Data Retention Time This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 32 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 AC CHARACTERISTICS Figure 4. AC Waveforms for Chip Erase Operations Timings Erase Command Sequence (last 2 cycles) tAS tWC Addresses 0x2AA Read Status Data (last two cycles) tAH 0x555 VA VA CE# tGHWL tCH OE# tWP WE# tWPH tCS 0x55 Data tDS VCC tWHWH2 0x10 Status DOUT tDH tVCS Notes: 1. VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 33 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 AC CHARACTERISTICS Figure 5. AC Waveforms for Block Erase Operations Timings Erase Command Sequence (last 2 cycles) tAS tWC Addresses 0x2AA Read Status Data (last two cycles) tAH BA VA VA CE# tGHWL tCH OE# tWP WE# tWPH tCS 0x55 Data tDS VCC tWHWH2 0x50 Status DOUT tDH tVCS Notes: 1. BA=Block Address (for block erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 34 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 6. AC Waveforms for Sector Erase Operations Timings Erase Command Sequence (last 2 cycles) tAS tWC Addresses 0x2AA Read Status Data (last two cycles) tAH SA VA VA CE# tGHWL tCH OE# tWP WE# tWPH tCS 0x55 Data tDS tWHWH2 0x30 Status DOUT tDH VCC tVCS Notes: 1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address. 2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 35 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 7. Program Operation Timings Program Command Sequence (last 2 cycles) tAS tWC Addresses 0x555 Program Command Sequence (last 2 cycles) tAH PA PA PA CE# tGHWL OE# tCH tWP WE# tWPH tCS Data OxA0 tDS VCC tWHWH1 Status PD DOUT tDH tVCS Notes: 1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address. 2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 36 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm Operations tRC Addresses VA tCH VA VA tACC tCE CE# tOE OE# tOEH tDF WE# tOH DQ[7] Complement DQ[6:0] Status Data Comple -ment Status Data Valid Data True True Valid Data Notes: 1. VA=Valid Address for reading Data# Polling status data 2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle. Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm Operations tRC Addresses VA VA tCH VA VA tACC tCE CE# tOE OE# WE# DQ6, DQ2 tOEH tDF tOH Valid Status (first read) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Valid Status (second read) 37 Valid Status (stops toggling) ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 Valid Data www.eonssi.com EN39SL801 Figure 10. Alternate CE# Controlled Write Operation Timings 0x555 for Program 0x2AA for Erase PA for Program SA for Sector Erase BA for Block Erase 0x555 for Chip Erase Addresses VA tWC tAS tAH WE# tWH tGHEL OE# tCP tWS CE# tDS tCPH tWHWH1 / tWHWH2 tBUSY tDH Status Data 0xA0 for Program 0x55 for Erase DOUT PD for Program 0x30 for Sector Erase 0x50 for Block Erase 0x10 for Chip Erase tRH Reset# Notes: PA = address of the memory location to be programmed. PD = data to be programmed at byte address. VA = Valid Address for reading program or erase status Dout = array data read at VA Shown above are the last two cycles of the program or erase command sequence and the last status read cycle Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence. Figure 11. DQ2 vs. DQ6 Enter Embedded Erase WE# Enter Erase Suspend Program Erase Suspend Erase Erase Resume Enter Suspend Program Enter Suspend Read Erase Suspend Read Erase Erase Complete DQ6 DQ2 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 38 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 12. Block Group Protect and Chip Unprotect Timing Diagram VID RESET# Vcc 0V 0V tVIDR tVIDR SA, A6,A1,A0 Data 60h Valid Valid Valid 60h 40h Status Block Protect/Unprotect Verify CE# >0.4μS WE# >1μS Block Protect: 150 uS Chip Unprotect: 15 mS OE# Notes: Use standard microprocessor timings for this device for read and write cycles. For Block Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0. Temporary Block Unprotect Parameter Std Speed Option -70 -90 Unit Min 500 ns Min 4 µs Description tVIDR VID Rise and Fall Time RESET# Setup Time for Temporary tRSP Block Unprotect(Note) Notes: tRSP is Not 100% tested. Figure 13. Temporary Block Unprotect Timing Diagram VID RESET# 0 or 2 V 0 or 2 V tVIDR tVIDR CE# WE# tRSP This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 39 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 14. 48L TFBGA 6mm x 8mm package outline SYMBOL This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 40 DIMENSION IN MM MIN. NOR MAX A --- --- 1.30 A1 0.23 0.29 --- A2 0.84 0.91 --- D 7.90 8.00 8.10 E 5.90 6.00 6.10 D1 --- 5.60 --- E1 --- 4.00 --- e --- 0.80 --- b 0.35 0.40 Note : 1. Coplanarity: 0.1 mm 0.45 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Figure 15. 48L WFBGA 4mm x 6mm package outline Note : Controlling dimensions are in millimeters (mm). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 41 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit Storage Temperature -65 to +150 ℃ Plastic Packages -65 to +125 ℃ Ambient Temperature With Power Applied -55 to +125 ℃ Output Short Circuit Current1 200 mA A9, OE# 2 -0.5 to +11.0 V All other pins 3 -0.5 to Vcc+0.5 V Vcc -0.5 to Vcc+0.5 V Voltage with Respect to Ground Notes: 1. No more than one output shorted may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 2. Minimum DC input voltage on A9 and OE# pins is –0.5V. During voltage transitions, A9 and OE# pins may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC input voltage on A9 and OE# is 9.0V which may overshoot to 11.0V for periods up to 20ns. 3. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below. 4. Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. RECOMMENDED OPERATING RANGES1 Parameter Value Unit -40 to 85 -40 to 125 ℃ Full Voltage Range: 1.65 to 1.95 V Ambient Operating Temperature Industrial Devices Automotive Devices Operating Supply Voltage Vcc 1. Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed. Vcc +2.0V 0 0 Maximum Negative Overshoot Waveform This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Maximum Positive Overshoot Waveform 42 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Purpose Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the same as that of Eon delivered before. Please be advised with the change and appreciate your kindly cooperation and fully support Eon’s product family. Eon products’ New Top Marking cFeon Top Marking Example: cFeon Part Number: XXXX-XXX Lot Number: XXXXX Date Code: XXXXX For More Information Please contact your local sales office for additional information about Eon memory solutions. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 43 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 ORDERING INFORMATION EN39SL801 - 70 B I P PACKAGING CONTENT P = RoHS compliant TEMPERATURE RANGE I = Industrial (-40°C to +85°C) A = Automotive (-40°C to +125°C) PACKAGE B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA) 0.8mm pitch, 6mm x 8mm package N = 48-Ball Very-Very-Thin-Profile Fine Pitch Ball Grid Array (WFBGA) 0.5mm pitch, 4mm x 6mm package SPEED 70 = 70ns 90 = 90ns BASE PART NUMBER EN = Eon Silicon Solution Inc. 39SL = 1.8V Serial 4KByte Uniform-Sector FLASH 801 = 8 Megabit (512K x 16) The valid combinations of EN39SL801 Speed Package Temperature Packaging Content EN39SL801 70 B, N I P EN39SL801 90 B, N A P Base Part Number This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 44 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 www.eonssi.com EN39SL801 Revisions List Revision No Description Date A B 2010/12/07 2011/02/14 C D Initial Release Update Table 4.DEVICE IDENTIFICTION (Autoselect Codes) on page 8. 1. Add Speed option of 90ns. 2. Add Temperature option of Automotive (-40°C to +125°C). 3. Update ORDERING INFORMATION on page 44. Correct the typo for the connection diagrams of WFBGA on page 3. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 45 ©2004 Eon Silicon Solution, Inc., Rev. D, Issue Date: 2011/09/15 2011/03/08 2011/09/15 www.eonssi.com