AD ADG714 Cmos, low voltage serially-controlled, octal spst switch Datasheet

a
CMOS, Low Voltage
Serially-Controlled, Octal SPST Switches
ADG714/ADG715
FEATURES
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I2C™-Compatible Interface
2.7 V to 5.5 V Single Supply
3 V Dual Supply
2.5 On Resistance
0.6 On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
GENERAL DESCRIPTION
The ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a two- or 3-wire
serial interface. On resistance is closely matched between switches
and very flat over the full signal range. Each switch conducts
equally well in both directions and the input signal range extends
to the supplies. Data is written to these devices in the form of
8 bits, each bit corresponding to one channel.
FUNCTIONAL BLOCK DIAGRAMS
ADG715
ADG714
S1
D1
S1
D1
S2
D2
S2
D2
S3
D3
S3
D3
S4
D4
S4
D4
S5
D5
S5
D5
S6
D6
S6
D6
S7
D7
S7
D7
S8
D8
S8
D8
INPUT SHIFT
REGISTER
INTERFACE
LOGIC
DOUT
RESET
SCLK DIN SYNC RESET
SDA
SCL
A0
A1
On power-up of these devices, all switches are in the OFF condition, and the internal registers contain all zeros.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual ± 3 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS
The ADG714 utilizes a 3-wire serial interface that is compatible
with SPI , QSPI and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.
1. 2-3-Wire Serial Interface.
The ADG715 utilizes a 2-wire serial interface that is compatible
with the I2C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by the
user. A maximum of four of these devices may be connected to
the bus.
3. Low On Resistance, typically 2.5 Ω.
2. Single/Dual Supply Operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and ± 3 V
supply rails.
4. Low Leakage.
5. Power-On Reset.
6. Small 24-lead TSSOP package.
I2C is a trademark of Philips Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADG714/ADG715–SPECIFICATIONS1 (V
B Version
–40C
+25C
to +85C
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
2.5
4.5
On-Resistance Match Between Channels (∆RON)
On-Resistance Flatness (R FLAT(ON))
0.6
LEAKAGE CURRENTS
Source OFF Leakage I S (OFF)
± 0.01
± 0.1
± 0.01
± 0.1
± 0.01
± 0.1
Drain OFF Leakage I D (OFF)
Channel ON Leakage I D, IS (ON)
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
Input High Voltage, V INH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT
Output Low Voltage
COUT Digital Output Capacitance
= 5 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted)
Unit
0 V to VDD V
Ω typ
5
Ω max
0.4
Ω typ
0.8
Ω max
Ω typ
1.2
Ω max
± 0.3
± 0.3
± 0.3
2.4
0.8
0.005
DD
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD , IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = VS = 1 V, or 4.5 V
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
0.4
max
pF typ
ISINK = 6 mA
0.7 VDD
VDD + 0.3
–0.3
0.3 VDD
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
± 0.1
3
2
4
DIGITAL INPUTS (SCL, SDA) 2
Input High Voltage, V INH
Input Low Voltage, VINL
IIN, Input Leakage Current
0.005
VHYST, Input Hysteresis
CIN, Input Capacitance
0.05 VDD
6
LOGIC OUTPUT (SDA) 2
VOL, Output Low Voltage
DYNAMIC CHARACTERISTICS 2
tON ADG714
±1
0.4
0.6
20
32
tON ADG715
95
140
tOFF ADG714
8
15
tOFF ADG715
85
130
Break-Before-Make Time Delay, t D
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
8
±3
–60
–80
–70
–90
155
11
11
22
1
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 3 V, RL = 300 Ω, CL = 35 pF
µA typ
µA max
10
20
VIN = 0 V to VDD
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
1
SPECIFICATIONS
ADG714/ADG715
(VDD = 3 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40C
+25C
to +85C
6
11
On-Resistance Match Between Channels (∆RON)
On-Resistance Flatness (R FLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage I S (OFF)
Drain OFF Leakage I D (OFF)
Channel ON Leakage I D, IS (ON)
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
Input High Voltage, V INH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT 2
Output Low Voltage
COUT Digital Output Capacitance
± 0.01
± 0.1
± 0.01
± 0.1
± 0.01
± 0.1
± 0.3
± 0.3
± 0.3
IIN, Input Leakage Current
0.005
VHYST, Input Hysteresis
CIN, Input Capacitance
0.05 VDD
6
LOGIC OUTPUT (SDA) 2
VOL, Output Low Voltage
Charge Injection
Off Isolation
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
±1
0.4
0.6
35
130
11
115
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
8
±2
–60
–80
–70
–90
155
11
11
22
1
20
–3–
VIN = 0 V to VDD
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 2 V, RL = 300 Ω, CL = 35 pF
µA typ
µA max
10
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
VS = VD = 1 V, or 3 V
0.7 VDD
VDD + 0.3
–0.3
0.3 VDD
180
Break-Before-Make Time Delay, t D
VS = 1 V/3 V, VD = 3 V/1 V
ISINK = 6 mA
20
tOFF ADG715
VS = 0 V to VDD, IS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V
max
pF typ
200
tOFF ADG714
VS = 0 V to VDD , IS = 10 mA
0.4
65
tON ADG715
VS = 0 V to VDD, IS = 10 mA
VIN = VINL or VINH
± 0.1
4
Input Low Voltage, VINL
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
V min
V max
µA typ
µA max
pF typ
3
DIGITAL INPUTS (SCL, SDA) 2
Input High Voltage, V INH
DYNAMIC CHARACTERISTICS 2
tON ADG714
0 V to VDD V
Ω typ
12
Ω max
0.4
Ω typ
1.2
Ω max
3.5
Ω typ
2.0
0.4
0.005
Unit
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG714/ADG715–SPECIFICATIONS
1
DUAL SUPPLY
(VDD = +3 V 10%, VSS = 3 V GND = 0 V unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
B Version
–40C
+25C
to +85C
2.5
4.5
On-Resistance Match Between Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT2
Output Low Voltage
COUT Digital Output Capacitance
DIGITAL INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.6
± 0.01
± 0.1
± 0.01
± 0.1
± 0.01
± 0.1
VHYST, Input Hysteresis
CIN, Input Capacitance
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
DYNAMIC CHARACTERISTICS2
tON ADG714
± 0.3
± 0.3
± 0.3
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
POWER REQUIREMENTS
IDD
±1
0.4
0.6
20
133
8
124
8
1
15
25
VIN = 0 V to VDD
V max
V max
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
µA typ
µA max
µA typ
µA max
15
25
ISS
VS = VD = +2.25 V/–1.25 V
V min
V max
V min
V max
µA typ
µA max
V min
pF typ
0.05 VDD
6
±3
–60
–80
–70
–90
155
11
11
22
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V
0.7 VDD
VDD + 0.3
–0.3
0.3 VDD
190
Break-Before-Make Time Delay, tD
VDD = +3.3 V, VSS = –3.3 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V
ISINK = 6 mA
18
tOFF ADG715
VS = VSS to VDD, IDS = 10 mA
max
pF typ
200
tOFF ADG714
VS = VSS to VDD, IDS = 10 mA
0.4
32
tON ADG715
VS = VSS to VDD, IDS = 10 mA
VIN = VINL or VINH
± 0.1
4
0.005
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
V min
V max
µA typ
µA max
pF typ
3
Input Low Voltage, VINL
IIN, Input Leakage Current
VSS to VDD V
Ω typ
5
Ω max
0.4
Ω typ
0.8
Ω max
Ω typ
1
Ω max
2.0
0.4
0.005
Unit
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 0 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
VDD = +3.3 V, VSS = –3.3 V
Digital Inputs = 0 V or 3.3 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG714/ADG715
ADG714 TIMING CHARACTERISTICS1, 2 (V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9 3
30
33
13
13
0
5
4.5
0
33
20
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SCLK Rising Edge to DOUT Valid
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
t1
SCLK
t8
t2
t3
t7
t4
SYNC
t6
t5
DIN
DB7
DB0
t9
DOUT
DB71
DB61
DB21
DB11
DB01
NOTE
1DATA FROM PREVIOUS WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
REV. 0
–5–
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1 (V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCL
t1
t2
t3
t4
t5
t6 2
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
SCL Clock Frequency
SCL Cycle Time
tHIGH, SCL High Time
tLOW, SCL Low Time
tHD, STA, Start/Repeated Start Condition Hold Time
tSU, DAT, Data Setup Time
tHD, DAT, Data Hold Time
300
20 + 0.1Cb3
250
300
20 + 0.1Cb3
400
50
ns max
ns min
ns max
ns max
ns min
pF max
ns max
t7
t8
t9
t10
t11
t11
Cb
tSP4
tSU, STA, Setup Time for Repeated Start
tSU, STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and
a Start Condition
tR, Rise Time of both SCL and SDA when Receiving
tF, Fall Time of SDA When Receiving
tF, Fall Time of SDA when Transmitting
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
NOTES
1
See Figure 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3
Cb is the total capacitance of one bus line in pF. t R and t F measured between 0.3 V DD and 0.7 VDD.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
SDA
t9
t3
t4
t11
t10
SCL
t4
t6
t2
t5
START
CONDITION
t7
REPEATED
START
CONDITION
t1
t8
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
–6–
REV. 0
ADG714/ADG715
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
or 30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
or 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
Temperature Range
Interface
Package Description
Package Option
ADG714BRU
ADG715BRU
–40°C to +85°C
–40°C to +85°C
SPI/QSPI/MICROWIRE
I2C-Compatible
TSSOP
TSSOP
RU-24
RU-24
PIN CONFIGURATIONS
24-Lead TSSOP
REV. 0
SCLK
1
24 SYNC
SCL
1
24 A0
VDD
2
23 RESET
VDD
2
23 RESET
DIN
3
22 DOUT
SDA
3
22 A1
GND
4
21 VSS
GND
4
21 VSS
S1
5
20 S8
S1
5
D1
6
D1
6
ADG714
ADG715
20 S8
S2
TOP VIEW 19 D8
(Not to Scale)
18 S7
7
S2
TOP VIEW 19 D8
(Not to Scale)
18 S7
7
D2
8
17 D7
D2
8
17 D7
S3
9
16 S6
S3
9
16 S6
D3 10
15 D6
D3 10
15 D6
S4 11
14 S5
S4 11
14 S5
D4 12
13 D5
D4 12
13 D5
–7–
ADG714/ADG715
ADG714 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SCLK
2
3
VDD
DIN
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
22
GND
Sx
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices can accommodate serial input rates of up to 30 MHz.
Positive Analog Supply Voltage.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
Ground Reference.
Source. May be an input or output.
Dx
Drain. May be an input or output.
VSS
DOUT
23
24
RESET
SYNC
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of
the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the
switches.
ADG715 PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
SCL
2
3
VDD
SDA
4
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13,
15, 17, 19
21
GND
Sx
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input
shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface.
Positive Analog Supply Voltage.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input
shift register during the write cycle and used to readback one byte of data during the read cycle. It
is a bidirectional open-drain data line which should be pulled to the supply with an external pullup resistor.
Ground Reference.
Source. May be an input or output.
Dx
Drain. May be an input or output.
VSS
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
22
A1
Address Input. Sets the second least significant bit of the 7-bit slave address.
23
RESET
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
24
A0
Address Input. Sets the least significant bit of the 7-bit slave address.
–8–
REV. 0
ADG714/ADG715
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
RON
∆RON
Most positive power supply potential.
Most negative power supply in a dual supply
application. In single supply applications, this
should be tied to ground.
Positive Supply Current.
Negative Supply Current.
Ground (0 V) Reference
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Ohmic resistance between D and S.
On-resistance match between any two channels,
i.e., RON max–RON min.
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on-resistance
as measured over the specified analog signal range.
IS (OFF)
Source leakage current with the switch “OFF.”
ID (OFF)
Drain leakage current with the switch “OFF.”
ID, IS (ON)
Channel leakage current with the switch “ON.”
VD (VS)
Analog voltage on terminals D and S.
CS (OFF)
“OFF” Switch Source Capacitance. Measured
with reference to ground.
CD (OFF)
“OFF” Switch Drain Capacitance. Measured
with reference to ground.
REV. 0
CD, CS (ON)
“ON” Switch Capacitance. Measured with reference to ground.
CIN
Digital Input Capacitance.
tON
Delay time between loading new data to the
shift register and selected switches switching on.
tOFF
Delay time between loading new data to the
shift register and selected switches switching off.
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Charge
A measure of the glitch impulse transferred
Injection
from the digital input to the analog output
during switching.
Bandwidth
The frequency at which the output is attenuated
by –3 dBs.
On Response The frequency response of the “ON” switch.
Insertion Loss The loss due to the ON resistance of the switch.
Insertion Loss = 20 log10 (VOUT with switch/
VOUT without switch.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL(IINH)
Input current of the digital input.
IDD
Positive Supply Current.
–9–
ADG714/ADG715 –Typical Performance Characteristics
8
8
TA = 25C
VSS = GND
7
VDD = 3V
VSS = GND
7
ON RESISTANCE – ON RESISTANCE – 6
VDD = 2.7V
5
VDD = 3.3V
4
VDD = 4.5V
VDD = 5.5V
3
6
+85C
+25C
5
4
–40C
2
3
1
2
0
0
1
2
3
4
VD, VS, DRAIN OR SOURCE VOLTAGE – V
0
5
0.5
1.0
1.5
2.0
8
8
TA = 25C
7
7
6
6
ON RESISTANCE – ON RESISTANCE – 3.0
Figure 6. On Resistance as a Function of VD (VS) for
Different Temperatures; VDD = 5 V
Figure 3. On Resistance as a Function of VD (VS) Single
Supply
5
4
VDD = +2.7V
VSS = –2.7V
3
VDD = +3.0V
VSS = –3.0V
5
4
+25C
3
+85C
2
2
VDD = +3.0V
VSS = –3.0V
1
VDD = +3.3V
VSS = –3.3V
0
–3.3 –2.7 –2.1 –1.5 –0.9 –0.3 0.3 0.9 1.5 2.1 2.7
VD OR VS DRAIN OR SOURCE VOLTAGE – V
–40C
1
0
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
3.3
0
0.5 1.0
1.5
2.0
2.5 3.0
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
Figure 7. On Resistance as a Function of VD (VS) for
Different Temperatures; Dual Supply
Figure 4. On Resistance as a Function of VD (VS); Dual
Supply
0.04
8
VDD = 5V
VSS = GND
TA = 25C
VDD = 5V
VSS = GND
7
6
0.02
CURRENT – nA
ON RESISTANCE – 2.5
VD OR VS DRAIN OR SOURCE VOLTAGE – V
5
4
+85C
+25C
3
I S , I D (ON)
0
I D (OFF)
I S (OFF)
–0.02
2
–40C
1
0
–0.04
0
1
2
3
4
VD OR VS DRAIN OR SOURCE VOLTAGE – V
0
5
1
2
3
4
5
VD OR VS – Volts
Figure 5. On Resistance as a Function of VD (VS) for
Different Temperatures; VDD = 3 V
Figure 8. Leakage Currents as a Function of VD (VS)
–10–
REV. 0
ADG714/ADG715
0.04
0.1
VDD = 3V
VSS = GND
TA = 25C
0.02
0.05
0
I S (OFF)
I D (OFF)
I D , I S (ON)
CURRENT – nA
I S , I D (ON)
CURRENT – nA
VDD = 3V
VSS = GND
VD = 3V/1V
VS = 1V/3V
–0.02
0
I D (OFF)
I S (OFF)
–0.05
–0.04
0
0.5
1
1.5
VOLTAGE – V
2.5
2
–0.1
10
3
Figure 9. Leakage Currents as a Function of VD (VS)
20
30
50
60
40
TEMPERATURE – C
80
70
Figure 12. Leakage Currents as a Function of Temperature
0
0.04
VDD = 5V
TA = 25C
VDD = +3V
VSS = –3V
TA = 25C
–20
ATTENUATION – dB
0.02
CURRENT – nA
I D (OFF)
I S (OFF)
0
I S , I D (ON)
–40
–60
–80
–0.02
–100
–0.04
–3
–2
–1
0
VOLTAGE – V
1
–120
30k
3
2
10M
100M
0
0.1
VDD = +3V
VSS = –3V
VD = +2.25V/–1.25V
VS = –1.25V/+2.25V
VDD = +5V
VSS = GND
VD = 4.5V/1V
VS = 1V/4.5V
I S , I D (ON)
–2
ATTENUATION – dB
CURRENT – nA
1M
FREQUENCY – Hz
Figure 13. Off Isolation vs. Frequency
Figure 10. Leakage Currents as a Function of VD (VS) Dual
Supply
0.05
100k
I S (OFF)
0
I D (OFF)
–4
–6
–8
–10
–0.05
–12
–0.1
10
20
30
40
50
60
TEMPERATURE – C
70
–14
30k
80
1M
10M
FREQUENCY – Hz
100M
Figure 14. On Response vs. Frequency
Figure 11. Leakage Currents as Function of Temperature
REV. 0
100k
–11–
300M
ADG714/ADG715
GENERAL DESCRIPTION
–40
VDD = 5V
TA = 25C
The ADG714 and ADG715 are serially controlled, octal SPST
switches, controlled by either a 2- or 3-wire interface. Each bit
of the 8-bit serial word corresponds to one switch of the part. A
Logic 1 in the particular bit position turns on the switch, while a
Logic 0 turns the switch off. Because each switch is independently
controlled by an individual bit, this provides the option of having
any, all, or none of the switches ON.
ATTENUATION – dB
–50
–60
–70
–80
–90
–100
30k
100k
1M
FREQUENCY – Hz
100M
10M
Figure 15. Crosstalk vs. Frequency
When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will be
minimal glitches on the output of the switch.
POWER-ON RESET
On power-up of the device, all switches will be in the OFF condition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
10
TA = 25C
VDD = +3.3V
VSS = GND
5
SERIAL INTERFACE
3-Wire Serial Interface
QINJ – pC
0
VDD = +5V
VSS = GND
VDD = +3.0V
VSS = –3.0V
The ADG714 has a 3-wire serial interface (SYNC, SCLK, and
DIN), that is compatible with SPI, QSPI, MICROWIRE
interface standards and most DSPs. Figure 1 shows the timing diagram of a typical write sequence.
–5
–10
–15
–20
–3
–2
–1
0
1
2
VOLTAGE – V
3
4
5
Figure 16. Charge Injection vs. Source/Drain Voltage
45
VSS = GND
40
TO N , V DD = 3V
35
TIME – ns
30
TO N , V DD = 5V
25
Data is written to the 8-bit shift register via DIN under the control of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on the falling edge of
SCLK. Each bit of the 8-bit word corresponds to one of the eight
switches. Figure 18 shows the contents of the input shift register. Data appears on the DOUT pin on the rising edge of SCLK
suitable for daisy chaining, delayed of course by eight bits. When
all eight bits have been written into the shift register, the SYNC
line is brought high again. The switches are updated with the
new configuration and the input shift register is disabled. With
SYNC held high, the input shift register is disabled, so further data
or noise on the DIN line will have no effect on the shift register.
20
DB7 (MSB)
TOFF , V DD = 3V
15
S8
S7
S5
S4
S3
S2
S1
DATA BITS
10
5
0
10
DB0 (LSB)
S6
Figure 18. Input Shift Register Contents
TO F F , V DD = 5V
20
30
40
50
60
TEMPERATURE – C
70
80
Figure 17. TON /TOFF Times vs. Temperature for ADG714
SERIAL INTERFACE
2-Wire Serial Interface
The ADG715 is controlled via an I2C-compatible serial bus.
This device is connected to the bus as a slave device (no clock is
generated by the switch).
The ADG715 has a 7-bit slave address. The five MSBs are 10010
and the two LSBs are determined by the state of the A0 and
A1 pins.
–12–
REV. 0
ADG714/ADG715
The 2-wire serial bus protocol operates as follows:
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the configuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and received one data byte,
the switches will update after the data byte; if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause a switch configuration update.
Repeat read of the matrix switch is also allowed.
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is the
address byte that consists of the 7-bit slave address followed
by a R/W bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage,
all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master will read from the
slave device. However, if the R/W bit is low, the master will
write to the slave device.
Input Shift Register
The input shift register is eight bits wide. Figure 18 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure
2. The 8-bit word consists of eight data bits, each controlling
one switch. MSB (Bit 7) is loaded first.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
Write Operation
When writing to the ADG715, the user must begin with an address
byte and R/W bit, after which the switch will acknowledge that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in the Figure 19 below.
3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a no acknowledge
for the ninth clock pulse (i.e., the SDA line remains high).
The master will then bring the SDA line low before the tenth
clock pulse and then high during the tenth clock pulse to establish a STOP condition.
READ Operation
When reading data back from the ADG715, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to transmit data by pulling SDA
low. The readback operation is a single byte that consists of the
eight data bits in the input register. The read operation for the
part is shown in Figure 20.
See Figure 19 for a graphical explanation of the serial interface.
SCL
SDA
1
0
START
COND
BY
MASTER
0
1
0
A1
A0
R/W
S8
S7
S6
S5
ACK
BY
ADG715
ADDRESS BYTE
S4
S3
S2
S1
DATA BYTE
ACK
BY
ADG715
STOP
COND
BY
MASTER
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
Figure 19. ADG715 Write Sequence
SCL
SDA
START
COND
BY
MASTER
1
0
0
1
ADDRESS BYTE
0
A1
A0
R/W
S8
ACK
BY
ADG715
S7
S6
S5
DATA BYTE
Figure 20. ADG715 Readback Sequence
REV. 0
–13–
S4
S3
S2
S1
ADG714/ADG715
APPLICATIONS
Multiple Devices On One Bus
Power Supply Sequencing
When using CMOS devices, care must be taken to ensure correct
power-supply sequencing. Incorrect power-supply sequencing
can result in the device being subjected to stresses beyond those
maximum ratings listed in the data sheet. Digital and analog inputs
should always be applied after power supplies and ground. In dual
supply applications, if digital or analog inputs may be applied to
the device prior to the VDD and VSS supplies, the addition of a
Schottky diode connected between VSS and GND will ensure
that the device powers on correctly. For single supply operation,
VSS should be tied to GND as close to the device as possible.
Figure 21 shows four ADG715 devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each switch to be written to or
read from independently.
Daisy-Chaining Multiple ADG714s
A number of ADG714 switches may be daisy-chained simply by
using the DOUT pin. Figure 22 shows a typical implementation. The SYNC pin of all three parts in the example are tied
together. When SYNC is brought low, the input shift registers
of all parts are enabled, data is written to the parts via DIN, and
clocked through the shift registers. When the transfer is complete,
SYNC is brought high and all switches are updated simultaneously. Further shift registers may be added in series.
Decoding Multiple ADG714s Using an ADG739
The dual 4-channel ADG739 multiplexer can be used to multiplex
a single chip select line in order to provide chip selects for up to
VDD
RP
RP
SDA
MASTER
SCL
VDD
SDA
SCL
A1
SCL
SDA
A1
A0
VDD
VDD
SDA
SDA
A1
A0
ADG715
SCL
A0
ADG715
SCL
A1
A0
ADG715
ADG715
Figure 21. Multiple ADG715s On One Bus
VDD
VDD
R
SCLK
SCLK
SYNC
DIN
SYNC
R
SCLK
ADG714
DIN
DOUT
VDD
ADG714
DIN
R
SCLK
DOUT
SYNC
ADG714
DIN
SYNC
DOUT
TO
OTHER
SERIAL
DEVICES
Figure 22. Multiple ADG714 Devices in a Daisy-Chained Conﬁguration
–14–
REV. 0
ADG714/ADG715
four devices on the SPI bus. Figure 23 illustrates the ADG739 and
multiple ADG714s in such a typical configuration. All devices
receive the same serial clock and serial data, but only one device
will receive the SYNC signal at any one time. The ADG739 is a
serially controlled device also. One bit programmable pin of the
microcontroller is used to enable the ADG739 via SYNC2,
while another bit programmable pin is used as the chip select for
the other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By bringing
SYNC1 low, the selected serial device hanging from the SPI bus
will be enabled and data will be clocked into its shift register on
the falling edges of SCLK. The convenient design of the matrix
switch allows for different combinations of the four serial
devices to be addressed at any one time. If more devices need
to be addressed via one chip select line, the ADG738 is an 8channel device and would allow further expansion of the chip
select scheme. There may be some digital feedthrough from the
digital input lines because SCLK and DIN are permanently
connected to each device. Using a burst clock will minimize the
effects of digital feedthrough on the analog channels.
ADG714
SYNC
DIN
SCLK
ADG714
VDD
SYNC
DIN
SCLK
1/2 of ADG739
S1A
SYNC1
DA
S2A
S3A
S4A
SCLK DIN SYNC
FROM
CONTROLLER
OR DSP
SYNC2
SCLK
DIN
OTHER
SPI
SYNC DEVICE
DIN
SCLK
OTHER
SPI
SYNC DEVICE
DIN
SCLK
Figure 23. Addressing Multiple ADG714s Using an
ADG739
REV. 0
–15–
ADG714/ADG715
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3768–2.5–4/00 (rev. 0) 00043
24-Lead TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
SEATING
PLANE
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8
0
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
–16–
REV. 0

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