AD AD5312 2.5 v to 5.5 v, 230 ua dual rail-to-rail, voltage output 8-/10-/12-bit dac Datasheet

a
+2.5 V to +5.5 V, 230 ␮A Dual Rail-to-Rail,
Voltage Output 8-/10-/12-Bit DACs
AD5302/AD5312/AD5322*
FEATURES
AD5302: Two 8-Bit Buffered DACs in One Package
AD5312: Two 10-Bit Buffered DACs in One Package
AD5322: Two 12-Bit Buffered DACs in One Package
10-Lead ␮SOIC Package
Micropower Operation: 300 ␮A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
0–V REF Output Voltage
Power-On-Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5302/AD5312/AD5322 are dual 8-, 10- and 12-bit buffered voltage output DACs in a 10-lead µSOIC package that
operate from a single +2.5 V to +5.5 V supply consuming
230 µA at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5302/
AD5312/AD5322 utilize a versatile 3-wire serial interface which
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs may be configured as
buffered or unbuffered inputs. The outputs of both DACs may
be updated simultaneously using the asynchronous LDAC input. The parts incorporate a power-on-reset circuit that ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a powerdown feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides softwareselectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VREFA
VDD
POWER-ON
RESET
AD5302/AD5312/AD5322
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
VOUTA
BUFFER
SYNC
INTERFACE
LOGIC
RESISTOR
NETWORK
POWER-DOWN
LOGIC
SCLK
DIN
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
VOUTB
BUFFER
RESISTOR
NETWORK
LDAC
VREFB
GND
*Patent Pending; protected by U.S. Patent No. 5684481.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD5302/AD5312/AD5322–SPECIFICATIONS (V
DD
= +2.5 V to +5.5 V; VREF = +2 V; RL = 2 k⍀
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
Parameter1
Min
B Version2
Typ
Max
Units
Conditions/Comments
8
± 0.15
± 0.02
±1
± 0.25
Bits
LSB
LSB
Guaranteed Monotonic by Design Over All Codes
10
± 0.5
± 0.05
±3
± 0.5
Bits
LSB
LSB
Guaranteed Monotonic by Design Over All Codes
3, 4
DC PERFORMANCE
AD5302
Resolution
Relative Accuracy
Differential Nonlinearity
AD5312
Resolution
Relative Accuracy
Differential Nonlinearity
AD5322
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
Offset Error Drift5
Gain Error Drift5
Power Supply Rejection Ratio5
DC Crosstalk5
DAC REFERENCE INPUTS5
VREF Input Range
12
±2
± 0.2
± 0.4
± 0.15
10
–12
–5
–60
30
1
0
VREF Input Impedance
Reference Feedthrough
Channel-to-Channel Isolation
OUTPUT CHARACTERISTICS5
Minimum Output Voltage6
Maximum Output Voltage6
DC Output Impedance
Short Circuit Current
Power-Up Time
VDD
VDD
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
IDD (Full Power-Down)
VDD = +4.5 V to +5.5 V
VDD = +2.5 V to +3.6 V
∆VDD = ± 10%
>10
180
–90
–80
Buffered Reference Mode
Unbuffered Reference Mode
Buffered Reference Mode
Unbuffered Reference Mode, Input Impedance = RDAC
Frequency = 10 kHz
Frequency = 10 kHz
0.001
VDD – 0.001
0.5
50
20
2.5
5
V min
V max
Ω
mA
mA
µs
µs
This is a measure of the minimum and maximum
drive capability of the output amplifier.
±1
0.8
0.6
0.5
3.5
µA
V
V
V
V
V
V
pF
5.5
V
300
230
450
350
µA
µA
0.2
0.05
1
1
µA
µA
2.4
2.1
2.0
Pin Capacitance
Guaranteed Monotonic by Design Over All Codes
See Figures 2 and 3
See Figures 2 and 3
See Figures 2 and 3
V
V
MΩ
kΩ
dB
dB
LOGIC INPUTS5
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Bits
LSB
LSB
% of FSR
% of FSR
mV
ppm of FSR/°C
ppm of FSR/°C
dB
µV
± 12
±1
±3
±1
60
2
2.5
VDD = +5 V
VDD = +3 V
Coming Out of Power-Down Mode. VDD = +5 V
Coming Out of Power-Down Mode. VDD = +3 V
VDD = +5 V ±
VDD = +3 V ±
VDD = +2.5 V
VDD = +5 V ±
VDD = +3 V ±
VDD = +2.5 V
10%
10%
10%
10%
IDD Specification Is Valid for All DAC Codes
Both DACs Active and Excluding Load Currents
Both DACs in Unbuffered Mode. VIH = VDD and
VIL = GND. In Buffered Mode, extra current is
typically x µA per DAC where x = 5 µA + VREF/RDAC.
NOTES
1
See Terminology.
2
Temperature range: B Version: –40°C to +105°C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,
VREF = VDD and “Offset plus Gain” Error must be positive.
Specifications subject to change without notice.
–2–
REV. 0
AD5302/AD5312/AD5322
(VDD = +2.5 V to +5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless
AC CHARACTERISTICS1 otherwise noted.)
Parameter2
Min
B Version3
Typ
Max
Output Voltage Settling Time
AD5302
AD5312
AD5322
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
6
7
8
0.7
12
0.10
0.01
0.01
200
–70
Units
µs
µs
µs
V/µs
nV-s
nV-s
nV-s
nV-s
kHz
dB
8
9
10
Conditions/Comments
VREF = VDD = +5 V
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
1 LSB Change Around Major Carry (011 . . . 11 to 100 . . . 00)
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology.
3
Temperature range: B Version: –40°C to +105°C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3 (V
DD
= +2.5 V to +5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Parameter
Limit at TMIN, TMAX
(B Version)
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
33
13
13
0
5
4.5
0
100
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Active Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulsewidth
SCLK Falling Edge to LDAC Rising Edge
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2.
3
See Figure 1.
Specifications subject to change without notice.
t1
SCLK
t8
t3
t2
t7
t4
SYNC
t6
t5
DIN*
DB15
DB0
t9
LDAC
t10
LDAC
*SEE PAGE 11 FOR DESCRIPTION OF INPUT REGISTER
Figure 1. Serial Interface Timing Diagram
REV. 0
–3–
AD5302/AD5312/AD5322
ABSOLUTE MAXIMUM RATINGS 1, 2
PIN CONFIGURATION
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . . +150°C
10-Lead µSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ Max–TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
LDAC 1
VDD 2
VREFB 3
VREFA 4
10
GND
AD5302/
AD5312/
AD5322
9
DIN
8
SCLK
TOP VIEW
(Not to Scale)
7
SYNC
6
VOUTB
VOUTA 5
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
Branding
Information
AD5302BRM
AD5312BRM
AD5322BRM
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
µSOIC
µSOIC
µSOIC
RM-10
RM-10
RM-10
D5B
D6B
D7B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5302/AD5312/AD5322 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD5302/AD5312/AD5322
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
1
LDAC
2
VDD
3
VREFB
4
VREFA
5
6
7
VOUTA
VOUTB
SYNC
8
SCLK
9
DIN
10
GND
Function
Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new
data. This allows simultaneous update of both DAC outputs
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply should be decoupled to GND.
Reference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or
an unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range
from 0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
Reference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or
an unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range from
0 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each
write cycle.
Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the
falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle.
Ground reference point for all circuitry on the part.
TERMINOLOGY
GAIN ERROR DRIFT
RELATIVE ACCURACY
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.
For the DAC, relative accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 4.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 7.
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
ANALOG CROSSTALK
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-secs.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
REV. 0
–5–
AD5302/AD5312/AD5322
DAC-TO-DAC CROSSTALK
CHANNEL-TO-CHANNEL ISOLATION
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC low
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-secs.
This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dBs.
GAIN ERROR
PLUS
OFFSET ERROR
IDEAL
DC CROSSTALK
OUTPUT
VOLTAGE
This is the dc change in the output level of one DAC in response to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while
monitoring the other DAC. It is expressed in µV.
ACTUAL
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dBs. VREF is held at +2 V and VDD is varied ± 10%.
POSITIVE
OFFSET
ERROR
DAC CODE
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dBs.
DEADBAND
TOTAL HARMONIC DISTORTION
AMPLIFIER
FOOTROOM
(1mV)
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics
present on the DAC output. It is measured in dBs.
NEGATIVE
OFFSET
ERROR
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Figure 2. Transfer Function with Negative Offset
ACTUAL
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
IDEAL
POSITIVE
OFFSET
ERROR
DAC CODE
Figure 3. Transfer Function with Positive Offset
–6–
REV. 0
Typical Performance Characteristics– AD5302/AD5312/AD5322
TA = +258C
VDD = +5V
TA = +258C
VDD = +5V
INL ERROR – LSBs
0
TA = +258C
VDD = +5V
8
INL ERROR – LSBs
2
0.5
INL ERROR – LSBs
12
3
1.0
1
0
–1
4
0
–4
–0.5
–8
–2
–3
0
50
100
150
CODE
200
250
Figure 4. AD5302 Typical INL Plot
0.6
800
1000
0
DNL ERROR – LSBs
0
–0.1
2000
CODE
3000
4000
1.0
TA = +258C
VDD = +5V
0.4
0.1
1000
Figure 6. AD5322 Typical INL Plot
TA = +258C
VDD = +5V
TA = +258C
VDD = +5V
0.2
400
600
CODE
200
Figure 5. AD5312 Typical INL Plot
0.3
DNL ERROR – LSBs
–12
0
0.5
DNL ERROR – LSBs
–1.0
0.2
0
–0.2
0
–0.5
–0.4
–0.2
–0.6
0
50
100
150
CODE
200
0
250
Figure 7. AD5302 Typical DNL Plot
400
600
CODE
1000
–1.0
0.75
ERROR – LSBs
.25
MAX INL
MAX DNL
0
MIN DNL
–.25
MAX DNL
0
MIN INL
–0.50
–.75
–0.75
2
3
4
VREF – Volts
Figure 10. AD5302 INL and DNL
Error vs. VREF
REV. 0
5
–1.00
–40
3000
4000
0.5
MAX INL
0.25
–.50
2000
CODE
VDD = +5V
VREF = +2V
–0.25
MIN INL
1000
1.0
VDD = +5V
VREF = +3V
0.50
.50
0
Figure 9. AD5322 Typical DNL Plot
1.00
VDD = +5V
TA = +258C
.75
–1.0
800
Figure 8. AD5312 Typical DNL Plot
1.0
ERROR – LSBs
200
ERROR – %
–0.3
GAIN ERROR
0.0
MIN DNL
OFFSET ERROR
–0.5
0
40
80
TEMPERATURE – 8C
120
Figure 11. AD5302 INL Error and
DNL Error vs. Temperature
–7–
–1.0
–40
0
40
80
TEMPERATURE – 8C
120
Figure 12. Offset Error and Gain
Error vs. Temperature
AD5302/AD5312/AD5322
5
600
VDD = +5V
TA = +258C
5V SOURCE
VDD = +5V
500
4
400
3V SOURCE
3
IDD – mA
VOUT – Volts
FREQUENCY
VDD = +3V
2
300
200
1
3V SINK
100
5V SINK
0
100
150
200
250
300
IDD – mA
350
0
400
Figure 13. IDD Histogram with VDD =
+3 V and VDD = +5 V
0
1
2
3
4
5
SINK/SOURCE CURRENT – mA
Figure 14. Source and Sink Current
Capability
600
0
6
700
BOTH DACS IN
THREE-STATE CONDITION
500
TA = +258C
600
0.8
400
500
300
+1058C
0.6
IDD – mA
+258C
–408C
IDD – mA
IDD – mA
FULL-SCALE
Figure 15. Supply Current vs. Code
1.0
BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED
ZERO-SCALE
–408C
0.4
+258C
200
VDD = +5V
300
0.2
100
400
VDD = +3V
200
+1058C
0
2.5
3.0
3.5
4.5
4.0
VDD – Volts
5.0
5.5
Figure 16. Supply Current vs. Supply
Voltage
0
2.7
3.7
4.2
VDD – Volts
4.7
0
5.2
Figure 17. Power-Down Current vs.
Supply Voltage
VDD = +5V
TA = +258C
CH2
100
3.2
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VLOGIC – Volts
Figure 18. Supply Current vs. Logic
Input Voltage
TA = +258C
TA = +258C
VDD
CLK
VOUT
CH1
CH1
VOUT
CH1
VOUTA
CH2
CH1 1V, CH2 5V, TIME BASE = 5ms/DIV
Figure 19. Half-Scale Settling (1/4 to
3/4 Scale Code Change)
CH1 1V, CH2 1V, TIME BASE = 20ms/DIV
Figure 20. Power-On Reset to 0 V
–8–
CH3
CLK
CH1 1V, CH3 5V, TIME BASE = 1ms/DIV
Figure 21. Exiting Power-Down to
Midscale
REV. 0
AD5302/AD5312/AD5322
2.50
10
2mV/DIV
–10
2.49
–20
dB
VOUT – Volts
0
–30
2.48
–40
–50
2.47
–60
0.01
Figure 22. AD5322 Major-Code
Transition
0.1
1
10
100
FREQUENCY – kHz
TA = +258C
FULL-SCALE ERROR – Volts
VDD = +5V
0.5
0
–0.5
0
1
2
3
VREF – Volts
4
5
Figure 25. Full-Scale Error vs. VREF
(Buffered)
REV. 0
10k
Figure 23. Multiplying Bandwidth
(Small-Signal Frequency Response)
1.0
–1.0
1k
–9–
500ns/DIV
Figure 24. DAC-DAC Crosstalk
AD5302/AD5312/AD5322
GENERAL DESCRIPTION
R
The AD5302/AD5312/AD5322 are dual resistor string DACs
fabricated on a CMOS process with resolutions of 8, 10 and 12
bits, respectively. They contain reference buffers, output buffer
amplifiers and are written to via a 3-wire serial interface. They
operate from single supplies of +2.5 V to +5.5 V and the output
buffer amplifiers provide rail-to-rail output swing with a slew
rate of 0.7 V/µs. Each DAC is provided with a separate reference input, which may be buffered to draw virtually no current
from the reference source, or unbuffered to give a reference
input range from GND to VDD. The devices have three programmable power-down modes, in which one or both DACs may be
turned off completely with a high impedance output, or the
output may be pulled low by an on-chip resistor.
R
R
R
R
Figure 27. Resistor String
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 26 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VOUT =
VREF × D
2N
where
D = decimal equivalent of the binary code that is loaded to the
DAC register;
0–255 for AD5302 (8 Bits)
0–1023 for AD5312 (10 Bits)
0–4095 for AD5322 (12 Bits).
There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it.
However, if the unbuffered mode is used, the user can have a
reference voltage as low as GND and as high as VDD since there
is no restriction due to headroom and foot room of the reference
amplifier.
If there is a buffered reference in the circuit (e.g., REF192)
there is no need to use the on-chip buffers of the AD5302/
AD5312/AD5322. In unbuffered mode the impedance is still
large (180 kΩ per reference input).
Output Amplifier
VREFA
REFERENCE
BUFFER
DAC
REGISTER
DAC Reference Inputs
The buffered/unbuffered option is controlled by the BUF bit in
the control word (see Serial Interface section for a description of
the register contents).
N = DAC resolution.
INPUT
REGISTER
TO OUTPUT
AMPLIFIER
SWITCH
CONTROLLED
BY CONTROL
LOGIC
RESISTOR
STRING
VOUTA
OUTPUT BUFFER
AMPLIFIER
Figure 26. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 27. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail which gives an output
range of 0.001 V to VDD – 0.001 V when the reference is VDD. It
is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 14.
The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at 8 bits) of 6 µs. See Figure 19.
POWER-ON RESET
The AD5302/AD5312/AD5322 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is:
– Normal operation.
– Reference inputs unbuffered.
– Output voltage set to 0 V.
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
–10–
REV. 0
AD5302/AD5312/AD5322
SERIAL INTERFACE
The AD5302/AD5312/AD5322 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE and DSP
interface standards.
Input Shift Register
The input shift register is 16 bits wide (see Figures 28–30 below).
Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this
operation is shown in Figure 1. The 16-bit word consists of four
control bits followed by 8, 10 or 12 bits of DAC data, depending on the device type. The first bit loaded is the MSB (Bit 15),
which determines whether the data is for DAC A or DAC B. Bit
14 determines if the reference input will be buffered or unbuffered. Bits 13 and 12 control the operating mode of the DAC.
Table I. Control Bits
Power-On
Default
Bit
Name
Function
15
A/B
14
BUF
13
12
PD1
PD0
0: Data Written to DAC A
1: Data Written to DAC B
0: Reference Is Unbuffered
1: Reference Is Buffered
Mode Bit
Mode Bit
N/A
D5
D4
D3
D2
D1
D0
X
To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being written to. As soon as the 16-bit control word has been written to
the part, the SCLK and DIN input buffers are powered down.
They only power-up again following a falling edge of SYNC.
X
X
X
Figure 28. AD5302 Input Shift Register Contents
DB15 (MSB)
DB0 (LSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
Figure 29. AD5312 Input Shift Register Contents
DB15 (MSB)
A/B BUF PD1 PD0 D11 D10 D9
DB0 (LSB)
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
Figure 30. AD5322 Input Shift Register Contents
The remaining bits are DAC data bits, starting with the MSB
and ending with the LSB. The AD5322 uses all 12 bits of DAC
data, the AD5312 uses 10 bits and ignores the 2 LSBs. The
AD5302 uses eight bits and ignores the last four bits. The data
format is straight binary, with all zeroes corresponding to
0 V output, and all ones corresponding to full-scale output
(VREF – 1 LSB).
REV. 0
When data has been transferred into both input registers, the
DAC registers of both DACs may be simultaneously updated,
by taking LDAC low.
0
0
DATA BITS
A/B BUF PD1 PD0 D9
After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer will be aborted and the input
registers will not be updated.
Low Power Serial Interface
DB0 (LSB)
D6
SYNC may be taken high after the falling edge of the 16th
SCLK pulse, observing the minimum SCLK falling edge to
SYNC rising edge time, t7.
0
DB15 (MSB)
A/B BUF PD1 PD0 D7
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial
data transfer, SYNC should be taken low observing the minimum SYNC to SCLK active edge setup time, t4. After SYNC
goes low, serial data will be shifted into the device’s input shift
register on the falling edges of SCLK for 16 clock pulses. Any
data and clock pulses after the 16th will be ignored, and no
further serial data transfer will occur until SYNC is taken high
and low again.
Double-Buffered Interface
The AD5302/AD5312/AD5322 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers
and DAC registers. The input register is connected directly to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC register contains the digital code used by the resistor
string.
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input register are transferred to it.
This is useful if the user requires simultaneous updating of both
DAC outputs. The user may write to both input registers individually and then, by pulsing the LDAC input low, both outputs
will update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5302/AD5312/
AD5322, the part will only update the DAC register if the input
register has been changed since the last time the DAC register
was updated thereby removing unnecessary digital crosstalk.
–11–
AD5302/AD5312/AD5322
POWER-DOWN MODES
The AD5302/AD5312/AD5322 have very low power consumption, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bits 13 and 12 (PD1
and PD0) of the control word. Table II shows how the state of
the bits corresponds to the mode of operation of that particular
DAC.
Table II. PD1/PD0 Operating Modes
PD1
PD0
Operating Mode
0
0
1
1
0
1
0
1
Normal Operation
Power-Down (1 kΩ Load to GND)
Power-Down (100 kΩ Load to GND)
Power-Down (High Impedance Output)
RESISTOR
STRING DAC
AMPLIFIER
POWER-DOWN
CIRCUITRY
VOUT
RESISTOR
NETWORK
Figure 32 shows a serial interface between the AD5302/AD5312/
AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103
SPORT is programmed through the SPORT control register
and should be configured as follows: Internal Clock Operation,
Active Low Framing, 16-Bit Word Length. Transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. The data is clocked out on each falling edge
of the DSP’s serial clock and clocked into the AD5302/AD5312/
AD5322 on the rising edge of the DSP’s serial clock. This corresponds to the falling edge of the DAC’s SCLK.
AD5302/
AD5312/
AD5322*
ADSP-2101/
ADSP-2103*
When both bits are set to 0, the DACs work normally with their
normal power consumption of 300 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current drop but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode and provides a defined input
condition for whatever is connected to the output of the DAC
amplifier. There are three different options. The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ
resistor or it is left open-circuited (Three-State). The output
stage is illustrated in Figure 31.
The bias generator, the output amplifier, the resistor string and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when
VDD = 3 V. See Figure 21 for a plot.
MICROPROCESSOR INTERFACING
AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface
TFS
DT
SCLK
SYNC
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. AD5302/AD5312/AD5322 to ADSP-2101/ADSP2103 Interface
AD5302/AD5312/AD5322 to 68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5302/AD5312/
AD5322 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5302/AD5312/
AD5322, while the MOSI output drives the serial data line of
the DAC. The SYNC signal is derived from a port line (PC7).
The setup conditions for correct operation of this interface are
as follows: the 68HC11/68L11 should be configured so that its
CPOL bit is a 0 and its CPHA bit is a 1. When data is being
transmitted to the DAC, the SYNC line is taken low (PC7).
When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK.
Serial data from the 68HC11/68L11 is transmitted in 8-bit
bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data
to the AD5302/AD5312/AD5322, PC7 is left low after the first
eight bits are transferred, and a second serial write operation is
performed to the DAC and PC7 is taken high at the end of this
procedure.
AD5302/
AD5312/
AD5322*
68HC11/68L11*
Figure 31. Output Stage During Power-Down
PC7
SYNC
SCK
SCLK
MOSI
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5302/AD5312/AD5322 to 68HC11/68L11
Interface
–12–
REV. 0
AD5302/AD5312/AD5322
AD5302/AD5312/AD5322 to 80C51/80L51 Interface
Figure 34 shows a serial interface between the AD5302/AD5312/
AD5322 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives
SCLK of the AD5302/AD5312/AD5322, while RXD drives the
serial data line of the part. The SYNC signal is again derived
from a bit programmable pin on the port. In this case port line
P3.3 is used. When data is to be transmitted to the AD5302/
AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format that has the LSB first.
The AD5302/AD5312/AD5322 requires its data with the MSB
as the first bit received. The 80C51/80L51 transmit routine
should take this into account.
APPLICATIONS INFORMATION
Typical Application Circuit
The AD5302/AD5312/AD5322 can be used with a wide range
of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0 V to VDD. More typically, the AD5302/AD5312/AD5322 may
be used with a fixed, precision reference voltage. Figure 36
shows a typical setup for the AD5302/AD5312/AD5322 when
using an external reference. If the reference inputs are unbuffered, the reference input range is from 0 V to VDD, but if the
on-chip reference buffers are used, the reference range is reduced.
Suitable references for 5 V operation are the AD780 and REF192
(2.5 V references). For 2.5 V operation, a suitable external
reference would be the REF191, a 2.048 V reference.
VDD = +2.5V TO +5.5V
EXT V
OUT
REF
AD5302/
AD5312/
AD5322*
80C51/80L51*
P3.3
SYNC
TXD
SCLK
RXD
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5302/
AD5312/
AD5322*
CS
SYNC
SK
SCLK
SO
DIN
REV. 0
AD5302/AD5312/
AD5322
SCLK
DIN
SYNC
VOUTB
GND
Figure 36.␣ AD5302/AD5312/AD5322 Using External
Reference
If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered (for example 0 V to +5 V),
the simplest solution is to connect the reference inputs to VDD.
As this supply may not be very accurate and may be noisy, the
AD5302/AD5312/AD5322 may be powered from the reference
voltage; for example, using a 5 V reference such as the REF195,
as shown in Figure 37. The REF195 will output a steady supply
voltage for the AD5302/AD5312/AD5322 The current required
from the REF195 is 300 µA supply current and approximately
30 µA into each of the reference inputs. This is with no load on
the DAC outputs. When the DAC outputs are loaded, the
REF195 also needs to supply the current to the loads. The total
current required (with a 10 kΩ load on each output) is:
360 µA + 2(5 V/10 kΩ) = 1.36 mA
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5302/AD5312/AD5322 to MICROWIRE
Interface
VOUTA
SERIAL
INTERFACE
AD5302/AD5312/AD5322 to MICROWIRE Interface
MICROWIRE*
1mF
AD780/REF192
WITH VDD = +5V
OR REF191 WITH
VDD = +2.5V
Figure 34. AD5302/AD5312/AD5322 to 80C51/80L51
Interface
Figure 35 shows an interface between the AD5302/AD5312/
AD5322 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock and is
clocked into the AD5302/AD5312/AD5322 on the rising edge
of the SK.
VDD
VREFA
VREFB
The load regulation of the REF195 is typically 2 ppm/mA which
results in an error of 2.7 ppm (13.5 µV) for the 1.36 mA current
drawn from it. This corresponds to a 0.0007 LSB error at 8-bits
and 0.011 LSB error at 12 bits.
–13–
AD5302/AD5312/AD5322
VREF is the reference voltage input.
+6V TO +16V
VIN
0.1mF
with
10mF
VREF = 5 V
REF195
GND
R1 = R2 = 10 kΩ and VDD = 5 V
VDD
VOUT
1mF
VREFA
VREFB
VOUT = (10 × D/2N) – 5 V
VOUTA
AD5302/AD5312/
AD5322
Opto-Isolated Interface for Process Control Applications
The AD5302/AD5312/AD5322 has a versatile 3-wire serial
interface, making it ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements or distance, it may be necessary to isolate the
AD5302/AD5312/AD5322 from the controller. This can easily
be achieved by using opto-isolators, which will provide isolation
in excess of 3 kV. The serial loading structure of the AD5302/
AD5312/AD5322 makes it ideally suited for use in opto-isolated
applications. Figure 39 shows an opto-isolated interface to the
AD5302/AD5312/AD5322 where DIN, SCLK and SYNC are
driven from opto-couplers. The power supply to the part also
needs to be isolated. This is done by using a transformer. On
the DAC side of the transformer, a +5 V regulator provides the
+5 V supply required for the AD5302/AD5312/AD5322.
SCLK
VOUTB
DIN
SYNC
GND
SERIAL
INTERFACE
Figure 37. Using an REF195 as Power and Reference to
the AD5302/AD5312/AD5322
Bipolar Operation Using the AD5302/AD5312/AD5322
The AD5302/AD5312/AD5322 has been designed for single
supply operation, but bipolar operation is also achievable using
the circuit shown in Figure 38. The circuit shown has been configured to achieve an output voltage range of –5␣ V < VOUT < +5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or OP295 as the output amplifier.
+6V TO +16V
VDD = +5V
0.1mF
POWER
R2
10kV
10mF
AD5302/AD5312/
AD5322
VDD
AD5302/AD5312/
AD5322
10kV
VOUTA/B
VOUTA
SYNC
SYNC
SYNC
VOUTB
GND
SERIAL
INTERFACE
VDD
Figure 38. Bipolar Operation Using the AD5302/AD5312/
AD5322
10kV
DIN
where
DIN
GND
The output voltage for any input code can be calculated as
follows:
VOUT = [(VREF × D/2N) × (R1+R2)/R1 – VREF × (R2/R1)]
VREFA
VREFB
–5V
SCLK
DIN
0.1mF
VDD
SCLK
AD820/
OP295
VREFA/B
1mF
10kV
SCLK
65V
VDD
10mF
VDD
+5V
R1
10kV
VIN
REF V
OUT
195
GND
+5V
REGULATOR
Figure 39. AD5302/AD5312/AD5322 in an Opto-Isolated
Interface
D is the decimal equivalent of the code loaded to the DAC
N is the DAC resolution
–14–
REV. 0
AD5302/AD5312/AD5322
Coarse and Fine Adjustment Using the AD5302/AD5312/
AD5322
Decoding Multiple AD5302/AD5312/AD5322s
The SYNC pin on the AD5302/AD5312/AD5322 can be used
in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock
and serial data, but only the SYNC to one of the devices will be
active at any one time allowing access to two channels in this
eight-channel system. The 74HC139 is used as a 2-to-4 line
decoder to address any of the DACs in the system. To prevent
timing errors from occurring, the enable input should be brought
to its inactive state while the coded address inputs are changing
state. Figure 40 shows a diagram of a typical setup for decoding
multiple AD5302/AD5312/AD5322 devices in a system.
SYNC
DIN
VDD
DIN
1G
1A
1B
74HC139
VDD = +5V
SCLK
VCC
CODED
ADDRESS
The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a
rail-to-rail output swing.
AD5302/AD5312/AD5322
SCLK
ENABLE
The DACs in the AD5302/AD5312/AD5322 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 42. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 will change the relative effect of the
coarse and fine adjustments. With the resistor values and external reference shown, the output amplifier has unity gain for the
DAC A output, so the output range is 0 V to 2.5 V – 1 LSB. For
DAC B the amplifier has a gain of 7.6 × 10–3, giving DAC B a
range equal to 19 mV.
1Y0
AD5302/AD5312/AD5322
1Y1
SYNC
1Y2
DIN
1Y3
SCLK
DGND
0.1mF
VIN
EXT V
OUT
REF
GND
AD5302/AD5312/AD5322
10mF
R1
390V
VDD
1mF
R4
390V
+5V
VREFA
AD780/REF192
WITH VDD = +5V
SYNC
R3
51.2kV
VOUTA
AD5302/AD5312/
AD5322
VOUT
AD820/
OP295
R2
51.2kV
VOUTB
VREFB
GND
DIN
SCLK
Figure 42. Coarse/Fine Adjustment
AD5302/AD5312/AD5322
Power Supply Bypassing and Grounding
SYNC
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5302/AD5312/AD5322 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the AD5302/AD5312/AD5322
is in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the AD5302/AD5312/AD5322. The AD5302/AD5312/
AD5322 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as
possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should
have low Effective Series Resistance (ESR) and Effective Series
Inductance (ESI), like the common ceramic types that provide a
low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
DIN
SCLK
Figure 40. Decoding Multiple AD5302/AD5312/AD5322
Devices in a System
AD5302/AD5312/AD5322 as a Digitally Programmable
Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD5302/AD5312/AD5322 is shown in Figure
41. The upper and lower limits for the test are loaded to DACs
A and B which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED will indicate the fail condition.
+5V
0.1mF
VREF
10mF
VIN
AD5302/AD5312/
AD5322
SCLK
SCLK
1kV
PASS
VOUTA
VREFB
SYNC
DIN
FAIL
VDD
VREFA
SYNC
DIN
1kV
VOUTB
GND
1/2
CMP04
PASS/FAIL
1/6 74HC05
Figure 41. Window Detector Using AD5302/AD5312/AD5322
REV. 0
The power supply lines of the AD5302/AD5312/AD5322 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
–15–
AD5302/AD5312/AD5322
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3447–8–3/99
10-Lead ␮SOIC
(RM-10)
0.122 (3.10)
0.114 (2.90)
10
6
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
1
5
PIN 1
0.0197 (0.50) BSC
0.037 (0.94)
0.031 (0.78)
0.120 (3.05)
0.112 (2.85)
0.120 (3.05)
0.112 (2.85)
0.043 (1.10)
MAX
0.028 (0.70)
0.016 (0.40)
PRINTED IN U.S.A.
68
0.006 (0.15) 0.012 (0.30) SEATING
08
PLANE 0.009 (0.23)
0.002 (0.05) 0.006 (0.15)
0.005 (0.13)
–16–
REV. 0