ACTS20MS Radiation Hardened Dual 4-Input NAND Gate April 1995 Features Pinouts 14 LEAD CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-T14, LEAD FINISH C TOP VIEW • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose 300K RAD (Si) • Single Event Upset (SEU) Immunity <1 x 10-10 Errors/Bit-Day (Typ) • SEU LET Threshold >80 MEV-cm2/mg • Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to ALSTTL Logic A1 1 14 VCC B1 2 13 D2 NC 3 12 C2 C1 4 11 NC D1 5 10 B2 Y1 6 9 A2 GND 7 8 Y2 • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2V Min 14 LEAD CERAMIC FLATPACK MIL-STD-1835 DESIGNATOR, CDFP3-F14, LEAD FINISH C TOP VIEW • Input Current ≤1µA at VOL, VOH A1 1 14 VCC D2 B1 2 13 NC 3 12 C2 The Intersil ACTS20MS is a radiation hardened dual 4-input NAND gate. A low on any input forces the output to a high logic state. C1 4 11 NC D1 5 10 B2 Y1 6 9 A2 The ACTS20MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. GND 7 8 Y2 Description Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE ACTS20DMSR -55oC to +125oC Intersil Class S Equivalent 14 Lead SBDIP ACTS20KMSR -55oC to +125oC Intersil Class S Equivalent 14 Lead Ceramic Flatpack ACTS20D/Sample +25oC Sample 14 Lead SBDIP ACTS20K/Sample +25oC Sample 14 Lead Ceramic Flatpack ACTS20HMSR +25oC Die Die Functional Diagram Truth Table INPUTS OUTPUT (1, 9) An Bn (2, 10) An Bn Cn Dn Yn L X X X H X L X X H X X L X H X X X L H H H H H L (6, 8) Yn (4, 12) Cn Dn (5, 13) NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 518824 File Number 3611 Spec Number