Fujitsu MB82DBS02163C-70LPBT 32 m bit (2 m wordã 16 bit) mobile phone application specific memory Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11429-3E
MEMORY Mobile FCRAMTM
CMOS
32 M Bit (2 M word×16 bit)
Mobile Phone Application Specific Memory
MB82DBS02163C-70L
■ DESCRIPTION
The FUJITSU MB82DBS02163C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous
Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format.
MB82DBS02163C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in
comparison to regular SRAM. The MB82DBS02163C adopts asynchronous page mode and synchronous burst
mode for fast memory access as user configurable options.
This MB82DBS02163C is suited for mobile applications such as Cellular Handset and PDA.
*: FCRAM is a trademark of Fujitsu Limited, Japan
■ FEATURES
•
•
•
•
•
•
•
•
Asynchronous SRAM Interface
Fast Access Time : tCE = 70 ns Max
8 words Page Access Capability : tPAA = 20 ns Max
Burst Read/Write Access Capability : tAC = 12 ns Max
Low Voltage Operating Condition : VDD = +1.65 V to +1.95 V
Wide Operating Temperature : TA = -30 °C to +85 °C
Byte Control by LB and UB
Low-Power Consumption : IDDA1 = 30 mA Max
IDDS1 = 80 µA Max
• Various Power Down mode : Sleep
4 M-bit Partial
8 M-bit Partial
• Shipping Form : Wafer/Chip, 71-ball plastic FBGA package
Copyright© 2005-2006 FUJITSU LIMITED All rights reserved
MB82DBS02163C-70L
■ PRODUCT LINEUP
Parameter
MB82DBS02163C-70L
Access Time (Max) (tCE, tAA)
70 ns
CLK Access Time (Max) (tAC)
12 ns
Active Current (Max) (IDDA1)
30 mA
Standby Current (Max) (IDDS1)
80 µA
Power Down Current (Max) (IDDPS)
10 µA
■ PIN ASSIGNMENT
(TOP VIEW)
A
B
8
NC
NC
7
NC
NC
D
E
F
G
H
J
A15
NC
NC
A16
NC
VSS
A11
A12
A13
A14
NC
DQ16
DQ8
DQ15
6
A8
A19
A9
A10
DQ7
DQ14 DQ13
DQ6
5
WE
CE2
A20
DQ5
VDD
NC
4
CLK
ADV WAIT
DQ4
VDD
DQ12
3
LB
UB
A18
A17
DQ2
DQ10 DQ11
DQ3
A7
A6
A5
A4
VSS
OE
DQ1
A3
A2
A1
A0
NC
CE1
2
NC
1
NC
NC
C
(BGA-71P-M03)
2
K
DQ9
L
M
NC
NC
NC
NC
NC
NC
NC
NC
MB82DBS02163C-70L
■ PIN DESCRIPTION
Pin Name
Description
A20 to A0
Address Input
CE1
Chip Enable 1 (Low Active)
CE2
Chip Enable 2(High Active)
WE
Write Enable (Low Active)
OE
Output Enable (Low Active)
LB
Lower Byte Control (Low Active)
UB
Upper Byte Control (Low Active)
CLK
Clock Input
ADV
Address Valid Input (Low Active)
WAIT
Wait Output
DQ8 to DQ1
Lower Byte Data Input/Output
DQ16 to DQ9
Upper Byte Data Input/Output
VDD
Power Supply Voltage
VSS
Ground
NC
No Connection
■ BLOCK DIAGRAM
VDD
VSS
A20 to A3
MODE
CONTROLLER
CLK
WAIT
COMMAND
DECODER
BURST
ADDRESS
COUNTER
MEMORY
CELL
ARRAY
33,554,432 bits
ADDRESS
CONTROLLER
MEMORY
CORE
CONTROLLER
BURST
CONTROLLER
X CONTROLLER
A2 to A0
CE2
CE1
ADV
WE
OE
LB
UB
Y CONTROLLER
ADDRESS
LATCH &
BUFFER
BUS
CONTROLLER
READ
AMP
WRITE
AMP
PARALLEL
SERIAL
TO SERIAL
TO PARALLEL
CONVERSION CONVERSION
CONVERTER
DQ16 to DQ9
I/O
BUFFER
DQ8 to DQ1
3
MB82DBS02163C-70L
■ FUNCTION TRUTH TABLE
1. Asynchronous Operation (Page Mode)
Mode
Standby
(Deselect)
CE2 CE1 CLK ADV WE
UB A20 to A0 DQ8 to DQ1 DQ16 to DQ9
WAIT
X
X
X
X
X
X
High-Z
High-Z
High-Z
Output Disable*1
X
*3
H
H
X
X
*5
High-Z
High-Z
High-Z
Output Disable
(No Read)
X
*3
H
H
Valid
High-Z
High-Z
High-Z
Read (Upper Byte)
X
*3
H
L
Valid
High-Z
Output
Valid
High-Z
Read (Lower Byte)
X
*3
L
H
Valid
Output
Valid
High-Z
High-Z
X
*3
L
L
Valid
Output
Valid
Output
Valid
High-Z
Page Read
X
*3
L/H
L/H
Valid
*6
*6
High-Z
No Write
X
*3
H
H
Valid
Invalid
Invalid
High-Z
Write (Upper Byte)
X
*3
H
L
Valid
Invalid
Write (Lower Byte)
X
*3
L
H
Valid
Input
Valid
Write (Word)
X
*3
L
L
Valid
Input
Valid
X
X
X
X
X
High-Z
Power Down*2
H
L
H
LB
X
Read (Word)
H
OE
L
X
H
L
X
L
H*4
X
Input Valid High-Z
Invalid
High-Z
Input Valid High-Z
High-Z
High-Z
Note : L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
*1: Should not be kept this logic condition longer than 1 µs.
*2: Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in "■FUNCTIONAL DESCRIPTION" for the details.
*3: "L" for address pass through and "H" for address latch on the rising edge of ADV.
*4: OE can be VIL during write operation if the following conditions are satisfied;
(1) Write pulse is initiated by CE1. Refer to "(14) Asynchronous Read/Write Timing #1-1 (CE1 Control)" in
"■TIMING DIAGRAMS".
(2) OE stays VIL during Write cycle.
*5: Can be either VIL or VIH but must be valid before Read or Write.
*6: Output of upper and lower byte data is either Valid or High-Z depending on the level of LB and UB input.
4
MB82DBS02163C-70L
2. Synchronous Operation (Burst Mode)
Mode
CE2 CE1 CLK ADV WE
Standby(Deselect)
H
Start Address Latch*1
X
*3
Advance Burst Read to
Next Address*1
Burst Read
Suspend*1
*3
H
L
LB
X
X
X
X*4
X*4
X
WAIT
High-Z
High-Z
High-Z
Valid*7
High-Z*8
High-Z*8
High-Z*11
L
Output
Valid*9
Output
Valid*9
Output
Valid
H
High-Z
High-Z
High*12
Input
Valid*10
Input
Valid*10
High*13
Input
Invalid
Input
Invalid
High*12
H
*3
*3
UB A20 to A0 DQ8 to DQ1 DQ16 to DQ9
X
X*6
Advance Burst Write to
Next Address*1
Burst Write Suspend*
X
OE
H
L*
X*6
5
X
H
1
H*
*3
5
Terminate Burst Read
X
H
X
High-Z
High-Z
High-Z
Terminate Burst Write
X
X
H
High-Z
High-Z
High-Z
X
X
High-Z
High-Z
High-Z
Power Down*2
L
X
X
X
Note : L = VIL, H = VIH, X can be either VIL or VIH,
High-Z = High impedance
X
X
= valid edge,
X
= rising edge of Low pulse,
*1: Should not be kept this logic condition longer than 8 µs.
*2: Power Down mode can be entered from Standby state and all output are in High-Z state.
Data retention depends on the selection of Partial Size for Power Down Program.
Refer to "Power Down" in “■FUNCTIONAL DESCRIPTION” for the details.
*3: Valid clock edge shall be set on either rising or falling edge through CR set. CLK must be started and stable
prior to memory access.
*4: Can be either VIL or VIH except for the case the both of OE and WE are VIL.
It is prohibited to bring the both of OE and WE to VIL.
*5: When device is operating in "WE Single Clock Pulse Control" mode, WE is Don’t care once write operation is
determined by WE Low Pulse at the beginning of write access together with address latching. Burst write suspend
feature is not supported in "WE Single Clock Pulse Control" mode.
*6: Can be either VIL or VIH but must be valid before Read or Write is determined. And once LB and UB input levels
are determined, they must not be changed until the end of burst.
*7: Once valid address is determined, input address must not be changed during ADV = L.
*8: If OE = L, output is either Invalid or High-Z depending on the level of LB and UB input. If WE = L, input is Invalid.
If OE = WE = H, output is High-Z.
*9: Outputs is either Valid or High-Z depending on the level of LB and UB input.
*10: Input is either Valid or Invalid depending on the level of LB and UB input.
*11: Output is either High-Z or Invalid depending on the level of OE and WE input.
*12: Keep the level from previous cycle except for suspending on last data. Refer to "WAIT Output Function" in
"■FUNCTIONAL DESCRIPTION" for the details.
*13: WAIT output is driven in High level during burst write operation.
5
MB82DBS02163C-70L
■ STATE DIAGRAM
• Initial/Standby State
Asynchronous Operation
(Page Mode)
Power
Up
Synchronous Operation
(Burst Mode)
Power
Down
@M = 1
CE2 = H
CE2 = L
Common State
CR Set
Pause Time
@M = 0
Power
Down
CE2 = H
Standby
Standby
CE2 = L
• Asynchronous Operation
CE2 = CE1 = H
Standby
CE1 = L
CE1 = L &
WE = L
Output
Disable
CE1 = H
Byte
Control
CE1 = L &
OE = L
CE1 = H
CE1 = H
WE = H
Address Change
or Byte Control
OE = L
WE = L
OE = H
Write
Read
Byte Control @OE = L
• Synchronous Operation
CE2 = CE1 = H
Standby
CE1 = H
Write
Suspend
CE1 = H
WE = H
WE = L
ADV Low Pulse
CE1 = H
Write
CE1 = H
CE1 = L,
ADV Low Pulse,
& WE = L
CE1 = L,
ADV Low Pulse,
& OE = L
ADV Low Pulse
(@BL = 8 or 16, and after burst
operation is completed)
Read
Suspend
OE = H
OE = L
Read
ADV Low Pulse
Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■FUNCTIONAL
DESCRIPTION", "2. AC Characteristics" in "■ELECTRICAL CHARACTERISTICS", and "■TIMING DIAGRAMS" for details.
6
MB82DBS02163C-70L
■ FUNCTIONAL DESCRIPTION
This device supports asynchronous read, page read & normal write operation and synchronous burst read and
burst write operation for faster memory access and features 3 kinds of power down modes for power saving as
user configurable option.
• Power-up
It is required to follow the power-up timing to start executing proper device operation. Refer to "Power-up Timing".
After Power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power
down feature.
• Configuration Register
The Configuration Register(CR) is used to configure the type of device function among optional features. Each
selection of features is set through CR set sequence after power-up. If CR set sequence is not performed after
power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration.
• CR Set Sequence
The CR set requires total 6 read/write cycles with unique address. Operation other than read/write operation
requires that device being in standby mode. Following table shows the detail sequence.
Cycle #
Operation
Address
Data
#1
Read
1FFFFFh (MSB)
Read Data (RDa)
#2
Write
1FFFFFh
RDa
#3
Write
1FFFFFh
RDa
#4
Write
1FFFFFh
X
#5
Write
1FFFFFh
X
#6
Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address(MSB).
The second and third cycles are to write to MSB. If the second or third cycle is written into the different address,
the CR set is cancelled and the data written by the second or third cycle is valid as a normal write operation. It
is recommended to write back the data(RDa) read by first cycle to MSB in order to secure the data.
The forth and fifth cycles are to write to MSB. The data of forth and fifth cycle is don't-care. If the forth or fifth
cycle is written into different address, the CR set is also cancelled, but write data may not be written as normal
write operation.
The last cycle is to read from specific address key for mode selection. And read data(RDb) is invalid.
Once this CR set sequence is performed from an initial CR set to the other new CR set, the written data stored
in memory cell array may be lost. So, it should perform the CR set sequence prior to regular read/write operation
if necessary to change from default configuration.
7
MB82DBS02163C-70L
• Address Key
The address key has the following format.
Address Register
Function
Key
Pin
Name
A20, A19
A18 to A16
A15
A14 to A12
PS
BL
M
RL
Partial Size
Burst Length
Mode
Read Latency
Description
Note
00
8 M-bit Partial
01
4 M-bit Partial
10
Reserved for future use
11
Sleep [Default]
000
Reserved for future use
*1
001
Reserved for future use
*1
010
8 words
011
16 words
100
Reserved for future use
*1
101
Reserved for future use
*1
110
Reserved for future use
*1
111
Continuous
*1
0
Synchronous Mode (Burst Read / Write)
*2
1
Asynchronous Mode [Default] (Page Read / Normal Write)
*3
000
Reserved for future use
*1
001
3 clocks
010
4 clocks
011
5 clocks
1xx
Reserved for future use
*1
0
Reserved for future use
*1
1
Sequential
0
Burst Read & Burst Write
1
Burst Read & Single Write
A11
BS
Burst Sequence
A10
SW
Single Write
A9
VE
Valid Clock
Edge
0
Falling Clock Edge
1
Rising Clock Edge
A8
⎯
⎯
1
Unused bits must be 1
*5
0
WE Single Clock Pulse Control without Write Suspend
Function
*4
1
WE Level Control with Write Suspend Function
1
Unused bits must be 1
A7
A6 to A0
WC
⎯
Write Control
⎯
*4
*5
*1: It is prohibited to apply this key.
*2: If M = 0, all the registers must be set with appropriate Key input at the same time.
*3: If M = 1, PS must be set with appropriate Key input at the same time. Except for PS, all the other key inputs
must be "1".
*4: Burst Read & Single Write is not supported at WE Single Clock Pulse Control.
*5: A8 and A6 to A0 must be all "1" in any cases.
8
MB82DBS02163C-70L
• Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has 3 power down modes, Sleep, 4 M-bit Partial, and 8 M-bit Partial.
The selection of power down mode is set through CR set sequence. Each mode has following data retention
features.
Mode
Data Retention Size
Retention Address
Sleep [default]
No
N/A
4 M-bit Partial
4 M bits
000000h to 03FFFFh
8 M-bit Partial
8 M bits
000000h to 07FFFFh
The default state after power-up is Sleep and it is the lowest power consumption but all data will be lost once
CE2 is brought to Low for Power Down. It is not required to perform CR set sequence to set to Sleep mode after
power-up in case of asynchronous operation.
• Burst Read/Write Operation
Synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or
system bus frequency. Configuration Register(CR) Set is required to perform burst read & write operation after
power-up. Once CR set sequence is performed to select synchronous burst mode, the device is configured to
synchronous burst read/write operation mode with corresponding RL and BL that is set through CR set sequence
together with operation mode. In order to perform synchronous burst read & write operation, it is required to
control new signals, CLK, ADV and WAIT that Low Power SRAMs do not have.
• Burst Read Operation
CLK
Address
Valid address
ADV
CE1
OE
WE
DQ
High
RL
High-Z
Q1
Q2
QBL
BL
WAIT
High-Z
(Continued)
9
MB82DBS02163C-70L
(Continued)
• Burst Write Operation
CLK
Address
Valid address
ADV
CE1
OE
High
WE
RL-1
DQ
High-Z
D1
D2
DBL
BL
WAIT
High-Z
• CLK Input Function
The CLK is input signal to synchronize memory to microcontroller or system bus frequency during synchronous
burst read & write operation. The CLK input increments device internal address counter and the valid edge of
CLK is referred for latency counts from address latch, burst write data latch, and burst read data output. During
synchronous operation mode, CLK input must be supplied except for standby state and power down state. CLK
is Don't care during asynchronous operation.
• ADV Input Function
The ADV is input signal to latch valid address. It is applicable to synchronous operation as well as asynchronous
operation. ADV input is active during CE1 = L and CE1 = H disables ADV input. All addresses are determined
on the rising edge of ADV.
During synchronous burst read/write operation, ADV = H disables all address inputs. Once ADV is brought to
High after valid address latch, it is inhibited to bring ADV Low until the end of burst or until burst operation is
terminated. ADV Low pulse is mandatory for synchronous burst read/write operation mode to latch the valid
address input.
During asynchronous operation, ADV = H also disables all address inputs. ADV can be tied to Low during
asynchronous operation and it is not necessary to control ADV to High.
10
MB82DBS02163C-70L
• WAIT Output Function
The WAIT is output signal to indicate data bus status when the device is operating in synchronous burst mode.
During burst read operation, WAIT output is enabled after specified time duration from OE = L or CE1 = L
whichever occurs last. WAIT output Low indicates data output at next clock cycle is invalid, and WAIT output
becomes High one clock cycle prior to valid data output. During continuous burst read operation, an additional
output delay may occur when a burst sequence crosses it's device-row boundary. The WAIT output notifies this
delay to controller. Refer to the section "Burst Length" for the additional delay cycles in details. During OE read
suspend, WAIT output does not indicate data bus status but carries the same level from previous clock cycle
(kept High) except for read suspend on the final data output. If final read data output is suspended, WAIT output
becomes high impedance after specified time duration from OE = H.
During burst write operation, WAIT output is enabled to High level after specified time duration from WE = L or
CE1 = L whichever occurs last and kept High for entire write cycles including WE write suspend. The actual
write data latching starts on the appropriate clock edge with respect to Valid Clock Edge, Read Latency, and
Burst Length. During WE Write suspend, WAIT output does not indicate data bus status but carries the same
level from previous clock cycle (kept High) except for write suspend on the final data input. If final write data
input is suspended, WAIT output becomes high impedance after specified time duration from WE = H.
The burst operation is always started after fixed latency with respect to Read Latency set in CR.
When the device is operating in asynchronous mode, WAIT output is always in High Impedance.
11
MB82DBS02163C-70L
• Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through CR set sequence after power-up. Once
specific RL is set through CR set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL-1. The burst operation is always started
after fixed latency with respect to Read Latency set in CR.
CLK
0
Address
1
2
3
4
5
6
Valid address
ADV
CE1
OE or WE
RL = 3
DQ
[Output]
WAIT
Q2
Q3
Q4
Q5
D2
D3
D4
D5
D6
Q1
Q2
Q3
Q4
D2
D3
D4
D5
Q1
Q2
Q3
D2
D3
D4
High-Z
DQ [Input]
WAIT
Q1
D1
High-Z
RL = 4
DQ [Output]
WAIT
High-Z
D1
DQ [Input]
WAIT
High-Z
RL = 5
DQ [Output]
WAIT
High-Z
D1
DQ [Input]
WAIT
12
High-Z
MB82DBS02163C-70L
• Address Latch by ADV
The ADV latches valid address presence on address inputs. During synchronous burst read/write operation
mode, all the address are determined on the rising edge of ADV when CE1 = L. The specified minimum value
of ADV = L setup time and hold time against valid edge of clock where RL count is begun must be satisfied.
Valid address must be determined with specified setup time against either the falling edge of ADV or falling edge
of CE1 whichever comes late. And the determined valid address must not be changed during ADV = L period.
• Burst Length
Burst Length is the number of word to be read or written during synchronous burst read/write operation as the
result of a single address latch cycle. It can be set on 8,16 words boundary or continuous for entire address
through CR set sequence. The burst type is sequential that is incremental decoding scheme within a boundary
address. Starting from initial address being latched, device internal address counter assigns +1 to the previous
address until reaching the end of boundary address and then wrap round to least significant address (= 0). After
completing read data output or write data latch for the set burst length, operation automatically ended except
for continuous burst length. When continuous burst length is set, read/write is endless unless it is terminated by
the rising edge of CE1. During continuous burst read, an additional output delay may occur when a burst
sequence cross it's device-row boundary. This is the case when A0 to A6 of starting address is either 7Dh, 7Eh,
or 7Fh as shown in the following table. The WAIT signal indicates this delay.
Read Address Sequence
Start Address
(A6 to A0)
BL = 8
BL = 16
Continuous
00h
00-01-02-...-06-07
00-01-02-...-0E-0F
00-01-02-03-04-...
01h
01-02-03-...-07-00
01-02-03-...-0F-00
01-02-03-04-05-...
02h
02-03-...-07-00-01
02-03-...-0F-00-01
02-03-04-05-06-...
03h
03-...-07-00-01-02
03-...-0F-00-01-02
03-04-05-06-07-...
...
...
...
...
7Ch
7C-...-7F-78-...-7B
7C-...-7F-70-...-7B
7C-7D-7E-7F-80-81-...
7Dh
7D-7E-7F-78-...-7C
7D-7E-7F-70-...-7C
7D-7E-7F-WAIT-80-81-...
7Eh
7E-7F-78-79-...-7D
7E-7F-70-71-...-7D
7E-7F-WAIT-WAIT-80-81-...
7Fh
7F-78-79-7A-...-7E
7F-70-71-72-...-7E
7F-WAIT-WAIT-WAIT-80-81
Note : Read address in Hexadecimal
• Single Write
Single write is synchronous write operation with Burst Length = 1. The device can be configured either to "Burst
Read & Single Write" or to "Burst Read & Burst Write" through CR set sequence. Once the device is configured
to "Burst Read & Single Write" mode, the burst length for synchronous write operation is always fixed 1 regardless
of BL values set in CR, while burst length for read is in accordance with BL values set in CR.
13
MB82DBS02163C-70L
• Write control
The device has two types of WE signal control method, "WE Level Control" and "WE Single Clock Pulse Control",
for synchronous burst write operation. It is configured through CR set sequence.
CLK
0
Address
1
2
3
4
5
D1
D2
D3
D4
D1
D2
D3
D4
6
Valid address
ADV
RL = 5
CE1
WE Level Control
tWLD
WE
DQ
[Input]
WAIT
tWLTH
High-Z
WE Single Clock Pulse Control
tWSCK
WE
tCKWH
DQ
[Input]
WAIT
14
tCLTH
tWLTH
High-Z
MB82DBS02163C-70L
• Burst Read Suspend
Burst read operation can be suspended by OE High pulse. During burst read operation, OE brought to High
from Low suspends burst read operation. Once OE is brought to High with the specified setup time against clock
where the data being suspended, the device internal counter is suspended, and the data output becomes high
impedance after specified time duration. It is inhibited to suspend the first data output at the beginning of burst
read.
OE brought to Low from High resumes burst read operation. Once OE is brought to Low, data output becomes
valid after specified time duration, and internal address counter is reactivated. The last data output being suspended as the result of OE = H and first data output as the result of OE = L are from the same address.
In order to guarantee to output last data before suspension and first data after resumption, the specified minimum
value of OE hold time and setup time against clock edge must be satisfied respectively.
CLK
tCKOH tOSCK
tCKOH tOSCK
OE
tOHZ
tAC
Q1
DQ
tCKQX
tCKTV
tAC
Q2
tOLZ
tAC
tAC
Q2
Q4
Q3
tCKQX
tCKQX
WAIT
• Burst Write Suspend
Burst write operation can be suspended by WE High pulse. During burst write operation, WE brought to High
from Low suspends burst write operation. Once WE is brought to High with the specified setup time against
clock where the data being suspended, device internal counter is suspended, data input is ignored. It is inhibited
to suspend the first data input at the beginning of burst write.
WE brought to Low from High resumes burst write operation. Once WE is brought to Low, data input becomes
valid after specified time duration, and internal address counter is reactivated. The write address of the cycle
where data being suspended and the first write address as the result of WE = L are the same address.
In order to guarantee to latch the last data input before suspension and first data input after resumption, the
specified minimum value of WE hold time and setup time against clock edge must be satisfied respectively.
Burst write suspend function is available when the device is operating in WE level controlled burst write only.
CLK
tCKWH tWSCK
tCKWH tWSCK
WE
tDSCK
tDSCK
D1
DQ
tDHCK
WAIT
D2
tDSCK
D2
tDHCK
tDSCK
D3
D4
tDHCK
High
15
MB82DBS02163C-70L
• Burst Read Termination
Burst read operation can be terminated by CE1 brought to High. If BL is set on Continuous, burst read operation
is continued endless unless terminated by CE1 = H. It is inhibited to terminate burst read before first data output
is completed. In order to guarantee last data output, the specified minimum value of CE1 = L hold time from
clock edge must be satisfied. After termination, the specified minimum recovery time is required to start new
access.
CLK
Valid address
Address
ADV
tTRB
tCKCLH
tCHZ
CE1
tOHZ
tCKOH
OE
WAIT
tCHTZ
tAC
High-Z
tCKQX
DQ
Q2
Q1
• Burst Write Termination
Burst write operation can be terminated by CE1 brought to High. If BL is set on Continuous, burst write operation
is continued endless unless terminated by CE1 = H. It is inhibited to terminate burst write before first data input
is completed. In order to guarantee last data input being latched, the specified minimum values of CE1 = L hold
time from clock edge must be satisfied. After termination, the specified minimum recovery time is required to
start new access.
CLK
Address
Valid address
ADV
tTRB
tCKCLH
tCHCK
CE1
tCKWH
WE
WAIT
DQ
16
tDSCK
tCHTZ
tDSCK
D1
D2
tDHCK
tDHCK
High-Z
MB82DBS02163C-70L
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Symbol
Unit
Min
Max
VDD
− 0.5
+ 3.6
V
VIN, VOUT
− 0.5
+ 3.6
V
Short Circuit Output Current *
IOUT
− 50
+ 50
mA
Storage Temperature
TSTG
− 55
+ 125
°C
Voltage of VDD Supply Relative to VSS *
Voltage at Any Pin Relative to VSS *
* : All voltages are referenced to VSS = 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Min
Max
VDD
1.65
1.95
V
VSS
0
0
V
High Level Input Voltage* *
VIH
VDD × 0.8
VDD + 0.2
V
Low Level Input Voltage*1, *3
VIL
− 0.3
VDD × 0.2
V
Ambient Temperature
TA
− 30
+ 85
°C
Power Supply Voltage*1
1, 2
*1 : All voltages are referenced to VSS = 0 V.
*2 : Maximum DC voltage on input and I/O pins is VDD + 0.2 V. During voltage transitions, inputs may overshoot to
VDD + 1.0 V for the periods of up to 5 ns.
*3 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, inputs may undershoot VSS to
-1.0 V for the periods of up to 5 ns.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
■ PACKAGE CAPACITANCE
(f = 1 MHz, TA = +25 °C)
Value
Symbol
Test
conditions
Min
Typ
Max
Address Input Capacitance
CIN1
VIN = 0 V
⎯
⎯
5
pF
Control Input Capacitance
CIN2
VIN = 0 V
⎯
⎯
5
pF
Data Input/Output Capacitance
CI/O
VIO = 0 V
⎯
⎯
8
pF
Parameter
Unit
17
MB82DBS02163C-70L
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
(At recommended operating conditions unless otherwise noted)
Value
Test Conditions
Unit
Min
Max
Input Leakage Current
ILI
VSS ≤ VIN ≤ VDD
−1.0
+1.0
µA
Output Leakage Current
ILO
0 V ≤ VOUT ≤ VDD, Output Disable
−1.0
+1.0
µA
Output High Voltage Level
VOH
VDD = VDD (Min), IOH = −0.5 mA
1.4
⎯
V
Output Low Voltage Level
VOL
IOL = 1 mA
⎯
0.4
V
IDDPS
VDD = VDD (Max),
VIN = VIH or VIL,
CE2 ≤ 0.2 V
SLEEP
⎯
10
µA
4 M-bit Partial
⎯
40
µA
8 M-bit Partial
⎯
50
µA
VDD Power Down Current
IDDP4
IDDP8
VDD Standby Current
IDDS
VDD = VDD (Max),
VIN (including CLK) = VIH or VIL,
CE1 = CE2 = VIH
⎯
1.5
mA
IDDS1
VDD = VDD (Max),
VIN (including CLK) ≤ 0.2 V or
VIN (including CLK) ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V
⎯
80
µA
IDDS2
VDD = VDD (Max), tCK = Min
VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V,
CE1 = CE2 ≥ VDD − 0.2 V
⎯
200
µA
tRC/tWC = Min
⎯
30
mA
tRC/tWC = 1 µs
⎯
3
mA
IDDA1
VDD Active Current
IDDA2
VDD Page Read Current
VDD Burst Access Current
VDD = VDD (Max),
VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA
IDDA3
VDD = VDD (Max), VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
IOUT = 0 mA, tPRC = Min
⎯
10
mA
IDDA4
VDD = VDD (Max), VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH,
tCK = tCK (Min), BL = Continuous,
IOUT = 0 mA
⎯
15
mA
Notes : • All voltages are referenced to VSS = 0 V.
• IDD depends on the output termination, load conditions, and AC characteristics.
• After power on, initialization following POWER-UP timing is required. DC characteristics are guaranteed
after the initialization.
18
MB82DBS02163C-70L
2. AC Characteristics
(1) Asynchronous Read Operation (Page mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Read Cycle Time
tRC
70
1000
ns
*1, *2
CE1 Access Time
tCE
⎯
70
ns
*3
OE Access Time
tOE
⎯
40
ns
*3
Address Access Time
tAA
⎯
70
ns
*3, *5
ADV Access Time
tAV
⎯
70
ns
*3
LB, UB Access Time
tBA
⎯
30
ns
*3
Page Address Access Time
tPAA
⎯
20
ns
*3, *6
Page Read Cycle Time
tPRC
20
1000
ns
*1, *6, *7
Output Data Hold Time
tOH
5
⎯
ns
*3
CE1 Low to Output Low-Z
tCLZ
5
⎯
ns
*4
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*4
LB, UB Low to Output Low-Z
tBLZ
0
⎯
ns
*4
CE1 High to Output High-Z
tCHZ
⎯
14
ns
*3
OE High to Output High-Z
tOHZ
⎯
14
ns
*3
LB, UB High to Output High-Z
tBHZ
⎯
14
ns
*3
Address Setup Time to CE1 Low
tASC
−5
⎯
ns
Address Setup Time to OE Low
tASO
10
⎯
ns
ADV Low Pulse Width
tVPL
10
⎯
ns
*8
ADV High Pulse Width
tVPH
15
⎯
ns
*8
Address Setup Time to ADV High
tASV
5
⎯
ns
Address Hold Time from ADV High
tAHV
10
⎯
ns
Address Invalid Time
tAX
⎯
10
ns
*5, *9
Address Hold Time from CE1 High
tCHAH
−5
⎯
ns
*10
Address Hold Time from OE High
tOHAH
−5
⎯
ns
WE High to OE Low Time for Read
tWHOL
15
1000
ns
tCP
15
⎯
ns
CE1 High Pulse Width
*11
*1 : Maximum value is applicable if CE1 is kept at Low without change of address input of A20 to A3.
*2 : Address should not be changed within minimum tRC.
*3 : The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*4 : The output load 5 pF without any other load.
*5 : Applicable to A20 to A3 when CE1 is kept at Low.
*6 : Applicable only to A2, A1 and A0 when CE1 is kept at Low for the page address access.
(Continued)
19
MB82DBS02163C-70L
(Continued)
*7 : In case Page Read Cycle is continued with keeping CE1 stays Low, CE1 must be brought to High within 4 µs.
In other words, Page Read Cycle must be closed within 4 µs.
*8 : tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of tVPL and tVPH must
be equal or greater than tRC for each access.
*9 : Applicable to address access when at least two of address inputs are switched from previous state.
*10 : tRC (Min) and tPRC (Min) must be satisfied.
*11 : If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read may become
longer by the amount of subtracting actual value from specified minimum value.
20
MB82DBS02163C-70L
(2) Asynchronous Write Operation
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
Write Cycle Time
tWC
70
1000
ns
*1, *2
Address Setup Time
tAS
0
⎯
ns
*3
ADV Low Pulse Width
tVPL
10
⎯
ns
*4
ADV High Pulse Width
tVPH
15
⎯
ns
*4
Address Setup Time to ADV High
tASV
5
⎯
ns
Address Hold Time from ADV High
tAHV
10
⎯
ns
CE1 Write Pulse Width
tCW
45
⎯
ns
*3
WE Write Pulse Width
tWP
45
⎯
ns
*3
LB, UB Write Pulse Width
tBW
45
⎯
ns
*3
LB, UB Byte Mask Setup Time
tBS
−5
⎯
ns
*5
LB, UB Byte Mask Hold Time
tBH
−5
⎯
ns
*6
Write Recovery Time
tWR
0
⎯
ns
*7
CE1 High Pulse Width
tCP
15
⎯
ns
WE High Pulse Width
tWHP
15
1000
ns
LB, UB High Pulse Width
tBHP
15
1000
ns
Data Setup Time
tDS
15
⎯
ns
Data Hold Time
tDH
0
⎯
ns
OE High to CE1 Low Setup Time for Write
tOHCL
−5
⎯
ns
*8
OE High to Address Setup Time for Write
tOES
0
⎯
ns
*9
LB and UB Write Pulse Overlap
tBWO
30
⎯
ns
*1 : Maximum value is applicable if CE1 is kept at Low without any address change.
*2 : Minimum value must be equal or greater than the sum of write pulse width (tCW, tWP or tBW) and write recovery
time (tWR).
*3 : Write pulse width is defined from High to Low transition of CE1, WE, LB, or UB, whichever occurs last.
*4: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late. The sum of tVPL and tVPH must
be equal or greater than tWC for each access.
*5: Applicable for byte mask only. Byte mask setup time is defined from the High to Low transition of CE1 or WE
whichever occurs last.
*6: Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1 or WE
whichever occurs first.
*7: Write recovery time is defined from Low to High transition of CE1, WE, LB, or UB, whichever occurs first.
*8: If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5 ns
after CE1 is brought to Low.
*9: If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address is valid.
21
MB82DBS02163C-70L
(3) Synchronous Operation - Clock Input (Burst mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
RL = 5
Clock Period
RL = 4
tCK
RL = 3
15
⎯
ns
*1
20
⎯
ns
*1
30
⎯
ns
*1
Clock High Pulse Width
tCKH
5
⎯
ns
Clock Low Pulse Width
tCKL
5
⎯
ns
Clock Transition Time
tCKT
⎯
3
ns
*2
*1: Clock period is defined between valid clock edges.
*2: Clock transition time is defined between VIH (Min) and VIL (Max)
(4) Synchronous Operation - Address Latch (Burst mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Address Setup Time to CE1 Low
tASCL
−5
⎯
ns
*1
Address Setup Time to ADV Low
tASVL
−5
⎯
ns
*2
Address Hold Time from ADV High
tAHV
10
⎯
ns
ADV Low Pulse Width
tVPL
10
⎯
ns
*3
ADV Low Setup Time to CLK
tVSCK
7
⎯
ns
*4
CE1 Low Setup Time to CLK
tCLCK
7
⎯
ns
*4
ADV Low Hold Time from CLK
tCKVH
1
⎯
ns
*4
Burst End ADV High Hold Time from CLK
tVHVL
15
⎯
ns
*1: tASCL is applicable if CE1 is brought to Low after ADV is brought to Low.
*2: tASVL is applicable if ADV is brought to Low after CE1 is brought to Low.
*3: tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
*4: Applicable to the 1st valid clock edge.
22
MB82DBS02163C-70L
(5) Synchronous Read Operation (Burst mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Read Cycle Time
tRCB
⎯
8000
ns
CLK Access Time
tAC
⎯
12
ns
*1
Output Hold Time from CLK
tCKQX
3
⎯
ns
*1
CE1 Low to WAIT Low
tCLTL
5
20
ns
*1
OE Low to WAIT Low
tOLTL
0
20
ns
*1, *2
CLK to WAIT Valid Time
tCKTV
⎯
12
ns
*1, *3
WAIT Valid Hold Time from CLK
tCKTX
3
⎯
ns
*1
CE1 Low to Output Low-Z
tCLZ
5
⎯
ns
*4
OE Low to Output Low-Z
tOLZ
10
⎯
ns
*4
LB, UB Low to Output Low-Z
tBLZ
0
⎯
ns
*4
CE1 High to Output High-Z
tCHZ
⎯
14
ns
*1
OE High to Output High-Z
tOHZ
⎯
14
ns
*1
LB, UB High to Output High-Z
tBHZ
⎯
14
ns
*1
CE1 High to WAIT High-Z
tCHTZ
⎯
20
ns
*1
OE High to WAIT High-Z
tOHTZ
⎯
20
ns
*1
OE Low Setup Time to 1st Data-output
tOLQ
30
⎯
ns
LB, UB Setup Time to 1st Data-output
tBLQ
30
⎯
ns
OE Setup Time to CLK
tOSCK
5
⎯
ns
OE Hold Time from CLK
tCKOH
5
⎯
ns
Burst End CE1 Low Hold Time from CLK
tCKCLH
5
⎯
ns
Burst End LB, UB Hold Time from CLK
tCKBH
5
⎯
ns
30
⎯
ns
*6
70
⎯
ns
*6
Burst Terminate
Recovery Time
BL = 8, 16
BL = Continuous
tTRB
*5
*1: The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*2: WAIT drives High at the beginning depending on OE falling edge timing.
*3: tCKTV is guaranteed after tOLTL (Max) from OE falling edge and tOSCK must be satisfied.
*4: The output load 5 pF without any other load.
*5: Once LB and UB are determined, they must not be changed until the end of burst read.
*6: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever
occurs late.
23
MB82DBS02163C-70L
(6) Synchronous Write Operation (Burst mode)
(At recommended operating conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Notes
Min
Max
Burst Write Cycle Time
tWCB
⎯
8000
ns
Data Setup Time to CLK
tDSCK
7
⎯
ns
Data Hold Time from CLK
tDHCK
3
⎯
ns
WE Low Setup Time to 1st Data Input
tWLD
30
⎯
ns
LB, UB Setup Time for Write
tBS
-5
⎯
ns
WE Setup Time to CLK
tWSCK
5
⎯
ns
WE Hold Time from CLK
tCKWH
5
⎯
ns
CE1 Low to WAIT High
tCLTH
5
20
ns
*2
WE Low to WAIT High
tWLTH
0
20
ns
*2
CE1 High to WAIT High-Z
tCHTZ
⎯
20
ns
*2
WE High to WAIT High-Z
tWHTZ
⎯
20
ns
*2
Burst End CE1 Low Hold Time from CLK
tCKCLH
5
⎯
ns
Burst End CE1 High Setup Time to next CLK
tCHCK
5
⎯
ns
Burst End LB, UB Hold Time from CLK
tCKBH
5
⎯
ns
Burst Write Recovery Time
tWRB
30
⎯
ns
*3
30
⎯
ns
*4
70
⎯
ns
*4
Burst Terminate
Recovery Time
BL = 8, 16
BL = Continuous
tTRB
*1
*1: Defined from the valid input edge to the High to Low transition of either ADV, CE1, or WE, whichever occurs
last. And once LB, UB are determined, LB, UB must not be changed until the end of burst write.
*2: The output load 50 pF with 50 Ω termination to VDD × 0.5 V.
*3: Defined from the valid clock edge where last data-input being latched at the end of burst write to the High to
Low transition of either ADV or CE1 whichever occurs late for the next access.
*4: Defined from the Low to High transition of CE1 to the High to Low transition of either ADV or CE1 whichever
occurs late for the next access.
24
MB82DBS02163C-70L
(7) Power Down Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE2 Low Setup Time for Power Down Entry
tCSP
20
⎯
ns
CE2 Low Hold Time after Power Down Entry
tC2LP
70
⎯
ns
CE1 High Hold Time following CE2 High
after Power Down Exit [Sleep mode only]
tCHH
300
⎯
µs
*1
CE1 High Hold Time following CE2 High
after Power Down Exit [not in Sleep mode]
tCHHP
70
⎯
ns
*2
CE1 High Setup Time following CE2 High
after Power Down Exit
tCHS
0
⎯
ns
*1
*1 : Applicable also to power-up.
*2 : Applicable when 4 M-bit and 8 M-bit Partial mode is set.
(8) Other Timing Parameters
Parameter
(At recommended operating conditions unless otherwise noted)
Value
Symbol
Unit
Notes
Min
Max
CE1 High to OE Invalid Time for Standby Entry
tCHOX
10
⎯
ns
CE1 High to WE Invalid Time for Standby Entry
tCHWX
10
⎯
ns
CE2 Low Hold Time after Power-up
tC2LH
50
⎯
µs
CE1 High Hold Time following CE2 High after Power-up
tCHH
300
⎯
µs
tT
1
25
ns
Input Transition Time (except for CLK)
*1
*2, *3
*1 : Some data might be written into any address location if tCHWX (Min) is not satisfied.
*2 : Except for clock input transition time.
*3 : The Input Transition Time (tT) at AC testing is 5 ns for Asynchronous operation and 3 ns for Synchronous
operation respectively. If actual tT is longer than 5 ns or 3 ns specified as AC test condition, it may violate AC
specification of some timing parameters. Refer to " (9) AC Test Conditions".
25
MB82DBS02163C-70L
(9) AC Test Conditions
Description
Symbol
Test Setup
Value
Unit
Input High Level
VIH
⎯
VDD × 0.8
V
Input Low Level
VIL
⎯
VDD × 0.2
V
VREF
⎯
VDD × 0.5
V
tT
Between VIL and VIH
5
ns
3
ns
Input Timing Measurement Level
Async.
Input Transition Time
Sync.
• AC MEASUREMENT OUTPUT LOAD CIRCUIT
VDD
50
VDD
0.1 µF
VSS
26
0.5 V
Device under
Test
Output
50 pF
Notes
MB82DBS02163C-70L
■ TIMING DIAGRAMS
(1) Asynchronous Read Timing #1-1 (Basic Timing)
tRC
Address
ADV
Address Valid
Low
tASC
tCHAH
tCE
CE1
tASC
tCP
tCHZ
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
tOH
DQ
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
27
MB82DBS02163C-70L
(2) Asynchronous Read Timing #1-2 (Basic Timing)
tRC
Address
Address Valid
tASV
tAHV
tAV
ADV
tVPH
tVPL
tASC
tCE
CE1
tCP
tCHZ
tASC
tOE
OE
tOHZ
tBA
LB, UB
tBHZ
tBLZ
tOLZ
DQ
(Output)
tOH
Valid Data Output
Note : This timing diagram assumes CE2 = H and WE = H.
28
MB82DBS02163C-70L
(3) Asynchronous Read Timing #2 (OE Control & Address Access)
tRC
Address
tAX
Address Valid
tRC
Address Valid
tAA
tOHAH
tAA
CE1
Low
tASO
tOE
OE
LB, UB
tOHZ
tOLZ
DQ
(Output)
tOH
Valid Data
Output
tOH
Valid Data
Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
29
MB82DBS02163C-70L
(4) Asynchronous Read Timing #3 (LB, UB Byte Control Access)
tAX
tRC
Address
tAX
Address Valid
tAA
CE1, OE
Low
tBA
tBA
LB
tBA
UB
tBHZ
tBLZ
tBHZ
tOH
tBLZ
tOH
DQ8 to DQ1
(Output)
Valid Data Output
Valid Data Output
tBLZ
tOH
DQ16 to DQ9
(Output)
Valid Data Output
Note : This timing diagram assumes CE2 = H, ADV = L and WE = H.
30
tBHZ
MB82DBS02163C-70L
(5) Asynchronous Read Timing #4 (Page Address Access after CE1 Control Access)
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
Address Valid
tASC
tPRC
tPRC
tPRC
Address Valid
Address Valid
Address Valid
tPAA
tPAA
tPAA
tCHAH
ADV
CE1
tCE
tCHZ
OE
LB, UB
tCLZ
tOH
tOH
tOH
tOH
DQ
(Output)
Valid Data Output
(Normal Access)
Valid Data Output
(Page Access)
Note : This timing diagram assumes CE2 = H and WE = H.
31
MB82DBS02163C-70L
(6) Asynchronous Read Timing #5 (Random and Page Address Access)
tAX
tRC
Address
(A20 to A3)
Address Valid
tRC
Address
(A2 to A0)
tRC
tPRC
Address Valid
Address Valid
tAA
CE1
Address Valid
tPRC
Address Valid
tAX
tRC
tPAA
Address Valid
tAA
tPAA
LOW
tASO
tOE
OE
tBA
LB, UB
tOLZ
DQ
tOH
tOH
tOH
tBLZ
(Output)
Valid Data Output
(Normal Access)
Valid Data Output
(Page Access)
Notes : • This timing diagram assumes CE2 = H, ADV = L and WE = H.
• Either or both LB and UB must be Low when both CE1 and OE are Low.
32
tOH
MB82DBS02163C-70L
(7) Asynchronous Write Timing #1-1 (Basic Timing)
tWC
Address
ADV
Address Valid
Low
tWR
tCW
tAS
CE1
tAS
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
33
MB82DBS02163C-70L
(8) Asynchronous Write Timing #1-2 (Basic Timing)
tWC
Address
Address Valid
tAHV
tASV
tVPL
ADV
tVPH
tWR
tCW
tAS
CE1
tCP
tAS
tWR
tWP
WE
tAS
tWHP
tAS
tWR
tBW
LB, UB
tAS
tBHP
tOHCL
OE
tDS
tDH
DQ
(Input)
Valid Data Input
Note : This timing diagram assumes CE2 = H.
34
tAS
MB82DBS02163C-70L
(9) Asynchronous Write Timing #2 (WE Control)
tWC
Address
tWC
Address Valid
Address Valid
tOHAH
CE1
Low
tAS
tWR
tWP
WE
tAS
tWR
tWP
tWHP
LB, UB
tOES
OE
tOHZ
tDS
tDH
tDS
tDH
DQ
(Input)
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H and ADV = L.
35
MB82DBS02163C-70L
(10) Asynchronous Write Timing #3-1 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tAS
tAS
tWP
tWP
tWHP
WE
tWR
tBH
tBS
LB
tBH
tBS
tWR
UB
tDS
tDH
DQ8 to DQ1
(Input)
tDS
DQ16 to DQ9
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
36
MB82DBS02163C-70L
(11) Asynchronous Write Timing #3-2 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWR
WE
tWR
tWHP
tAS
tBW
tBS
tBH
LB
tBH
tBS
tAS
tBW
UB
tDS
tDH
DQ8 to DQ1
(Input)
tDS
DQ16 to DQ9
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
37
MB82DBS02163C-70L
(12) Asynchronous Write Timing #3-3 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
tWHP
WE
tAS
tBW
tWR
tBH
tBS
LB
tBS
tBH
tAS
tWR
tBW
UB
tDS
tDH
DQ8 to DQ1
(Input)
tDS
DQ16 to DQ9
(Input)
tDH
Valid Data Input
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
38
MB82DBS02163C-70L
(13) Asynchronous Write Timing #3-4 (WE, LB, UB Byte Write Control)
tWC
Address
CE1
tWC
Address Valid
Address Valid
Low
WE
tAS
tBW
tWR
LB
tAS
tBW
tWR
tBHP
tBWO
tDS
DQ8 to DQ1
(Input)
tDS
tDH
Valid Data Input
tDH
Valid Data Input
tBWO
tAS
tBW
UB
tBW
tWR
tBHP
tDS
DQ16 to DQ9
(Input)
tAS
tWR
tDH
Valid Data Input
tDS
tDH
Valid Data Input
Note : This timing diagram assumes CE2 = H, ADV = L and OE = H.
39
MB82DBS02163C-70L
(14) Asynchronous Read/Write Timing #1-1 (CE1 Control)
tWC
Address
tRC
Write Address
tCHAH
tAS
Read Address
tWR
tCHAH
tASC
tCW
tCE
CE1
tCP
tCP
WE
LB, UB
tOHCL
OE
tCHZ
tOH
tDS
tDH
tCLZ
tOH
DQ
Read Data Output
Write Data Input
Notes : • This timing diagram assumes CE2 = H and ADV = L
• Write address is valid from either CE1 or WE of last falling edge.
40
Read Data Output
MB82DBS02163C-70L
(15) Asynchronous Read/Write Timing #1-2 (CE1, WE, OE Control)
Address
tWC
tRC
Write Address
Read Address
tAS
tCHAH
tWR
tASC
tCHAH
tCE
CE1
tCP
tCP
tWP
WE
LB, UB
tOHCL
tOE
OE
tCHZ
tOH
tDS
tDH
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• OE can be fixed Low during write operation if it is CE1 controlled write at Read-Write-Read
sequence.
41
MB82DBS02163C-70L
(16) Asynchronous Read/Write Timing #2 (OE, WE Control)
tWC
Address
tRC
Write Address
Read Address
tAA
tOHAH
CE1
tOHAH
Low
tAS
tWR
tWP
WE
tOES
LB, UB
tASO
tOE
OE
tWHOL
tOHZ
tOH
tDS
tDH
tOHZ
tOLZ
tOH
DQ
Read Data Output
Write Data Input
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
42
Read Data Output
MB82DBS02163C-70L
(17) Asynchronous Read/Write Timing #3 (OE, WE, LB, UB Control)
tWC
Address
tRC
Read Address
Write Address
tAA
tOHAH
CE1
tOHAH
Low
WE
tOES
tAS
tBW
tWR
tBA
LB, UB
tASO
tBHZ
OE
tWHOL
tBHZ
tOH
tDS
tDH
tBLZ
tOH
DQ
Read Data Output
Write Data Input
Read Data Output
Notes : • This timing diagram assumes CE2 = H and ADV = L.
• CE1 can be tied to Low for WE and OE controlled operation.
43
MB82DBS02163C-70L
(18) Clock Input Timing
tCK
CLK
tCK
tCKH
tCKT
tCKL
tCKT
Notes : • Stable clock input must be required during CE1 = L.
• tCK is defined between valid clock edges.
• tCKT is defined between VIH (Min) and VIL (Max)
(19) Address Latch Timing (Synchronous Mode)
Case #1
Case #2
CLK
Address
Valid
tASCL
Valid
tAHV
tVSCK
tASVL
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tVPL
tCLCK
CE1
Low
Notes : • Case #1 is the timing when CE1 is brought to Low after ADV is brought to Low.
Case #2 is the timing when ADV is brought to Low after CE1 is brought to Low.
• tVPL is specified from the falling edge of either CE1 or ADV whichever comes late.
At least one valid clock edge must be input during ADV = L.
• tVSCK and tCLCK are applied to the 1st valid clock edge during ADV=L.
44
MB82DBS02163C-70L
(20) Synchronous Read Timing #1 (OE Control)
RL = 5
CLK
tRCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tASVL
tVSCK tCKVH
tVSCK
tCKVH
ADV
tVPL
tVHVL
tASCL
tVPL
tASCL
CE1
tCLCK
tCKOH
tCP
tCLCK
OE
tOLQ
WE
High
tCKBH
tBLQ
LB, UB
tCKTV
WAIT
tOHTZ
High-Z
tOLTL
DQ
tCKTV
High-Z
tCKTX
tAC
tAC
Q1
tOLZ
tCKQX
tAC
tCKTX
tOHZ
QBL
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
45
MB82DBS02163C-70L
(21) Synchronous Read Timing #2 (CE1 Control)
RL = 5
CLK
tRCB
Address
Valid
Address
Valid
Address
tAHV
tASVL
tVSCK
tASVL
tCKVH
tAHV
tVSCK
tCKVH
ADV
tVPL
tVHVL
tVPL
tASCL
tASCL
CE1
tCP
tCLCK
tCLCK
tCKCLH
OE
WE
High
tCKBH
LB, UB
tCKTV
tCKTV
tCHTZ
tCLTL
WAIT
tCLTL
tCKTX
tAC
tAC
Q1
DQ
tCLZ
tCKQX
tAC
tCKTX
tCLZ
tCHZ
QBL
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
46
MB82DBS02163C-70L
(22) Synchronous Read Timing #3 (ADV Control)
RL = 5
CLK
tRCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tVSCK
tASVL
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
CE1
Low
OE
Low
WE
High
tVHVL
tVPL
LB, UB
tCKTV
tCKTV
WAIT
tCKTX
DQ
tAC
tAC
Q1
tCKQX
tAC
tCKTX
QBL
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
47
MB82DBS02163C-70L
(23) Synchronous Read - WAIT Output Timing (Continuous Read)
RL = 5
CLK
Address
XXX7Fh
tASVL
tAHV
tVSCK
tCKVH
ADV
tVPL
tASCL
CE1
tCLCK
OE
tOLQ
WE
High
tBLQ
LB,UB
tCKTV
WAIT
tCKTV
tCKTV
High-Z
tCKTX
tOLTL
DQ
High-Z
tOLZ
tCKTX
tCKTX
tAC
tAC
tAC
tAC
Q1
Q2
Q3
tCKQX
tCKQX
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = Continuous.
48
MB82DBS02163C-70L
(24) Synchronous Write Timing #1 (WE Level Control)
RL = 5
CLK
tWCB
Address
Valid
Address
Address
Valid
tAHV
tASVL
tVSCK
tAHV
tASVL
tVSCK
tCKVH
tCKVH
ADV
tWRB
tVPL
tASCL
tVPL
tCLCK
tASCL
CE1
tCP
tCLCK
OE
High
tCKWH
tWLD
WE
tBS
tCKBH
tBS
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
D2
tDSCK
tWHTZ
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
49
MB82DBS02163C-70L
(25) Synchronous Write Timing #2 (WE Single Clock Pulse Timing)
RL = 5
CLK
tWCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV
tWRB
tVPL
tASCL
tVPL
tCLCK
tASCL
CE1
tCLCK
tCP
tCKCLH
OE
High
tWSCK
tWSCK
tCKWH
tCKWH
WE
tBS
tCKBH
tBS
LB, UB
WAIT
High-Z
tWLTH
DQ
tDSCK
tDSCK
D1
tDHCK
D2
tDSCK
tCHTZ
tWLTH
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
50
MB82DBS02163C-70L
(26) Synchronous Write Timing #3 (ADV Control)
RL = 5
CLK
tWCB
Address
Valid
Address
Valid
Address
tASVL
tAHV
tASVL
tVSCK
tAHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tVPL
tWRB
CE1
OE
High
WE
tBS
tCKBH
tBS
LB, UB
High
WAIT
tDSCK
DQ
tDSCK
D1
tDHCK
D2
tDSCK
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
51
MB82DBS02163C-70L
(27) Synchronous Write Timing #4 (WE Level Control, Single Write)
RL = 5
CLK
tWCB
Address
Valid
Address
Address
Valid
tAHV
tASVL
tVSCK
tVSCK
tASVL
ttAHV
AHV
tVSCK
tCKVH
tCKVH
ADV
tVPL
tWRB
tVPL
tCLCK
tASCL
tASCL
CE1
tCLCK
OE
tCP
High
tWLD
tCKWH
WE
tCKBH
tBS
tBS
LB, UB
WAIT
High-Z
tWLTH
DQ
tWHTZ
tDSCK
tWLTH
D1
tDHCK
Notes : • This timing diagram assumes CE2 = H, the valid clock edge on rising edge and single write operation.
• Write data is latched on the valid clock edge.
52
MB82DBS02163C-70L
(28) Synchronous Read to Write Timing #1 (CE1 Control)
RL = 5
CLK
tWCB
Address
Valid
Address
tAHV
tASVL
tVSCK
tCKVH
ADV
tVHVL
tVPL
tCLCK
tCKCLH
CE1
tCKCLH
tASCL
tCP
OE
WE
tCKBH
tBS
tCKBH
LB,UB
tCHTZ
tCKTV
WAIT
tAC
DQ
QBL-1
tCKQX
tCKTX
QBL
tCKQX
tCHZ
tCLTH
tDSCK
tDSCK
tDSCK
tDSCK
D1
D2
D3
DBL
tDHCK
tDHCK
tDHCK
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
53
MB82DBS02163C-70L
(29) Synchronous Read to Write Timing #2 (ADV Control)
RL = 5
CLK
Address
Address
Valid
tAHV
tASVL
tVSCK
tCKVH
ADV
tVPL
tVHVL
CE1
tCKOH
OE
tCKWH
tWLD
WE
tCKBH
tBS
tCKBH
LB,UB
tOHTZ
tCKTV
WAIT
tAC
DQ
QBL-1
tCKQX
tCKTX
QBL
tCKQX
tOHZ
tWLTH
tDSCK
tDSCK
tDSCK
D1
D2
tDHCK
tDHCK
D3
tDHCK
tDSCK
DBL
tDHCK
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
54
MB82DBS02163C-70L
(30) Synchronous Write to Read Timing #1(CE1 Control)
RL = 5
CLK
tCKT
Address
Address
Valid
tAHV
tASVL
tVSCK
tCKVH
ADV
tVPL
tCKCLH
CE1
tASCL
tCP
tCLCK
tWRB
OE
WE
tCKBH
LB,UB
tCKTV
High-Z
WAIT
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tCHTZ
tCLTL
DBL
tDHCK
tCLZ
tCKTX
tAC
tAC
Q1
Q2
tCKQX
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
55
MB82DBS02163C-70L
(31) Synchronous Write to Read Timing #2 (ADV Control)
RL = 5
CLK
tCKT
Address
Valid
Address
tASVL
tAHV
tVSCK
tCKVH
ADV
tVPL
tWRB
Low
CE1
OE
tOLQ
tCKWH
WE
tCKBH
tBLQ
LB,UB
tCKTV
High-Z
WAIT
tDSCK
DQ
tDSCK
DBL-1
tDHCK
tWHTZ
tOLTL
DBL
tDHCK
tOLZ
tCKTX
tAC
tAC
Q1
Q2
tCKQX
tCKQX
Note : This timing diagram assumes CE2 = H, the valid clock edge on rising edge and BL = 8 or 16.
56
MB82DBS02163C-70L
(32) Power-up Timing #1
CE1
tCHS
tCHH
tC2LH
CE2
VDD (Min)
VDD
0V
Note : The tC2LH specifies after VDD reaches specified minimum level.
(33) Power-up Timing #2
CE1
tCHH
CE2
VDD (Min)
VDD
0V
Note : The tCHH specifies after VDD reaches specified minimum level and applicable both CE1 and CE2.
If transition time of VDD (from 0 V to VDD (Min)) is longer than 50 ms, Power-up Timing #1 must
be applied.
57
MB82DBS02163C-70L
(34) Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHP)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note : This Power Down mode can be also used as a reset timing if “Power-up timing” above could
not be satisfied and Power Down program was not performed prior to this reset.
(35) Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode.
58
Standby
MB82DBS02163C-70L
(36) Configuration Register Set Timing #1 (Asynchronous Operation)
tRC
Address
tWC
MSB*1
MSB*1
tCP
tWC
tWC
tWC
tRC
MSB*1
MSB*1
MSB*1
Key*2
tCP
tCP
tCP
tCP*3
(tRC)
tCP
CE1
OE
WE
LB, UB*4
DQ*3
RDa
Cycle #1
RDa
Cycle #2
RDa
Cycle #3
X
X
Cycle #4
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
*2 : The address key must confirm the format specified in “■FUNCTIONAL DESCRIPTION”.
If not, the operation and data are not guaranteed.
*3 : After tCP or tRC following Cycle #6, the Configuration Register Set is completed and returned
to the normal operation. tCP and tRC are applicable to returning to asynchronous mode and
to synchronous mode respectively.
*4 : Byte read or write is available in addition to Word read or write. At least one byte control
signal (LB or UB) need to be Low.
59
MB82DBS02163C-70L
(37) Configuration Register Set Timing #2 (Synchronous Operation)
CLK
Address
MSB*1
MSB*1
tRCB
MSB*1
MSB*1
tWCB
tWCB
tWCB
MSB*1
Key*2
tWCB
tRCB
ADV
tTRB
tTRB
tTRB
tTRB
3
*
tTRB
tTRB
CE1
OE
WE
LB,UB* 4
WAIT
RL
DQ
RL-1
RDa
Cycle #1
RDa
Cycle #2
RL-1
RL-1
RL-1
X
RDa
Cycle #3
Cycle #4
RL
X
Cycle #5
RDb
Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5.
*2 : The address key must confirm the format specified in “■FUNCTIONAL DESCRIPTION”.
If not, the operation and data are not guaranteed.
*3 : After tTRB following Cycle #6, the Configuration Register Set is completed and returned
to the normal operation.
*4 : Byte read or write is available in addition to Word read or write. At least one byte control
signal (LB or UB) need to be Low.
60
MB82DBS02163C-70L
■ BONDING PAD INFORMATION
Please contact local FUJITSU representative for pad layout and pad coordinate information.
■ ORDERING INFORMATION
Part Number
Shipping Form / Package
MB82DBS02163C-70LWT
wafer
MB82DBS02163C-70LPBT
71-ball plastic FBGA
(BGA-71P-M03)
Remarks
61
MB82DBS02163C-70L
■ PACKAGE DIMENSION
71-ball plastic FBGA
Ball pitch
0.80 mm
Package width ×
package length
7.00 × 11.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
∅0.45 mm
Mounting height
1.20 mm Max.
Weight
0.14 g
(BGA-71P-M03)
71-ball plastic FBGA
(BGA-71P-M03)
11.00±0.10(.433±.004)
B
0.20(.008) S B
1.09
.043
+0.11
–0.10
+.004
–.004
0.80(.031)
REF
0.40(.016)
REF
(Seated height)
0.80(.031)
REF
8
7
6
5
4
3
2
1
A
7.00±0.10
(.276±.004)
0.40(.016)
REF
0.10(.004) S
0.39±0.10
(Stand off)
(.015±.004)
INDEX-MARK AREA
S
0.20(.008) S A
M L K J H G F E D C B A
71-ø0.45 +0.10
–0.05
71-ø.018 –+.004
.002
ø0.08(.003)
M
S AB
0.10(.004) S
C
62
2003 FUJITSU LIMITED B71003S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB82DBS02163C-70L
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0604