Anpec APA3169 20w stereo digital class-d audio power amplifier with eq, drc and 2.1 mode Datasheet

APA3169
20W Stereo Digital Class-D Audio Power Amplifier with EQ, DRC and 2.1
Mode
Features
General Description
•
Operating Voltage: 8.0V-24V for PVDD
The APA3169 is a digital input, stereo, high efficiency,
•
– 3.0V~3.6V for DVDD and AVDD
High Efficiency Class D Operation Eliminate the
Class-D audio amplifier available in a TQFP7x7-48P
package.
Need of Heatsinks
Digital Serial Audio Input (Stereo Output)
The APA3169 accepts the digital serial audio data and
using the digital audio processor to convert the audio
2.1 Mode (2SE + 1BTL)
2.0 Mode (2BTL)
data becomes the stereo Class-D output speaker
amplifier. This provides the seamless integration between
Single-Filter PBTL Mode Support
I2C Address Selection Pin (Chip Select)
the codec and the speaker amplifier.
The APA3169 is a slave device receiving clocks from ex-
I2C Control Interface
Sampling Rate Support from 32kHz to 192kHz
ternal source, and the Class-D’s PWM switching frequency is 352.8kHz for the sampling rate 44.1kHz or 384
Separated Volume Control from 24dB to Mute
Soft Mute (50% Duty Cycle)
kHz for sampling 48kHz, depend on the input signal’s
sampling rate.
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Separate Dynamic Range Control for Satellite and
Subchannels
18 Programmable Biquads for Speaker EQ and
Other Audio Processing Features
Simplified Application Circuit
Programmable Coefficients for DRC Filters
DC Blocking Filters, De-emphasis Filters
Support for 3D Effects
Shutdown and Mute Function
Thermal and Over-Current Protections with AutoRecovery
Space Saving Package TQFP7x7-48P
Lead Free and Green Devices Available
(RoHS Compliant)
Digital
Audio
Source
MCLK
LRCLK
SCLK
SDIN
I2C
Control
SDA
SCL
A_SEL
•
•
•
LCD TV
LCSE
OUT_B
LCSE
PVDD
PVDD
APA3169
Control
Input
/RESET_N
/PDN_N
Loop Filter
PLL_FLTP
PLL_FLTM
Applications
OUT_A
OUT_C
LCBTL
OUT_D
iPod Dock
Sound Bar
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
1
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APA3169
48
47
46
45
44
43
42
41
40
39
38
37
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
Pin Configuration
OUT_A 1
PVDD_A 2
PVDD_A 3
BS_A 4
VCLAB 5
TM1 6
TM2 7
PBTL 8
AVSS 9
PLL_FLTM 10
PLL_FLTP 11
VR_ANA 12
OUT_D
PVDD_D
PVDD_D
BS_D
32
31
30
29
28
27
26
25
VCLCD
VREG
AGND
DGND
DVSS
DVDD
TP3
RESET_N
AVDD
A_SEL
MCLK
TP1
TP2
VR_DIG
PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
APA3169
36
35
34
33
TQFP7x7-48P
(TOP VIEW)
Ordering and Marking Information
Package Code
QCA : TQFP7x7-48P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APA3169
Assembly Material
Handling Code
Temperature Range
Package Code
APA3169 QCA :
APA3169
XXXXX
XXXXX - Date Code
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
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APA3169
Absolute Maximum Ratings
Symbol
(Note 1)
Parameter
Rating
Unit
VPVDD
Supply Voltage (PVDD_X to PGND_XX)
-0.3 to 26
VDVDD
Supply Voltage (DVDD to DVSS)
-0.3 to 6
VAVDD
Supply Voltage (AVDD to AVSS)
-0.3 to 6
Input Voltage (MCLK to AVSS)
-0.5 to 6
Input Voltage (PDN, RESET, LRCLK, SCLK, SDIN, SDA, SCL to DVSS)
-0.5 to 6
Input
Voltage
V
Input Voltage (AVSS, DVSS, AGDN to PGND_XX)
-0.3 to +0.3
VOUT_X
OUT_X to PGND_XX
-0.3 to +26
VBS_X
BS_X to PGND_XX
-0.3 to +31
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
TSDR
Soldering Temperature Range, 10 seconds
PD
Power Dissipation
150
ο
-65 to +150
ο
260
ο
C
C
C
Internally Limited
W
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
Junction-to-Ambient Resistance in Free Air
θJA
Typical Value
Unit
25
°C/W
(Note 2)
TQFP7x7-48P
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TQFP7X7-48P is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
Range
Parameter
Min.
Max.
VAVDD, VDVDD
Analog/Digital Supply Voltage (AVDD,DVDD)
3
3.6
VPVDD
Full Bridge Stage Supply Voltage (PVDD_X)
8
24
2
5
0
0.8
PDN, MCLK, LRCLK, SCLK,
SDIN, SDA, SCL, RESET
PDN, MCLK, LRCLK, SCLK,
SDIN, SDA, SCL, RESET
VIH
High Level Threshold
Voltage
VIL
Low Level Threshold
Voltage
TA
Ambient Temperature Range
-40
85
TJ
Junction Temperature Range
-40
125
Unit
V
ο
C
RL(BTL)
Speaker Resistance
6
-
Ω
LO(BTL)
Output Low Pass Filter Inductance
10
47
µH
Copyright  ANPEC Electronics Corp.
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APA3169
Electrical Characteristics
ο
TA=25 C, VPVDD=18V, VAVDD = VDVDD = 3.3V, RL=8Ω, BD Mode, fS=48kHz (unless otherwise noted)
Symbol
Parameter
APA3169
Test Conditions
Min.
Typ.
Unit
Max.
PWM Operating Conditions
32 kHz Data Rate ±2%
fS
Output Sample Rate
256
44.1k/88.2k/176.4 kHz Data
Rate ±2%
352.8
48k/96k/192 kHz Data Rate
± 2%
kHz
384
PLL Input Parameters and External Filter Components
fMCLK
tr/tf(MCLK)
MCLK Frequency
2.8224
-
24.576
MHz
MCLK Duty Cycle
40
50
60
%
Rise/Fall Time for MCLK
-
-
5
ns
LRCLK Allowable Drift before
LRCLK Reset
-
-
4
MCLKs
External PLL Filter Capacitor C1
SMD 0603 Y5V
-
47
-
External PLL Filter Capacitor C2
SMD 0603 Y5V
-
4.7
-
-
470
-
Ω
External PLL Filter Resistor R
nF
DC CHARACTERISTICS
VOH
High Level output voltage(A_SEL
and SDA)
IOH=-4mA, DVDD=AVDD=3V
2.4
-
-
V
VOL
Low Level output voltage(A_SEL
and SDA)
IOL=4mA, DVDD=AVDD=3V
-
-
0.5
V
IIL
Low Level Input Current
VI<VIL, DVDD=AVDD=3.6V
-
-
75
µA
IIH
High Level Input Current
VI>VIH, DVDD=AVDD=3.6V
-
-
75
µA
IDD
3.3V Supply Current
(AVDD+DVDD)
Normal Mode (No LC, No load)
-
14
20
Reset (No LC, No load)
-
14
20
Full Bridge Stage Supply Current
(PVDD_X)
Normal Mode (No LC, No load)
-
18
36
Reset (No LC, No load)
-
0.5
1.6
TJ=25oC, includes metallization
resistance
-
180
-
mΩ
IPVDD
Drain to source resistance,LS
rDS(ON)
mA
o
Drain to source resistance,HS
TJ=25 C, includes metallization
resistance
-
180
-
mΩ
VUVP
Undervoltage protection limit
PVDD falling
-
6.8
-
V
VUVP,hyst
Undervoltage protection limit
PVDD rising
V
TTP
-
7.2
-
Thermal Protection Threshold
-
150
-
Thermal Protection Threshold
Hysteresis
-
30
-
o
Copyright  ANPEC Electronics Corp.
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C
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APA3169
Electrical Characteristics (Cont.)
ο
TA=25 C, VPVDD=18V, VAVDD = VDVDD = 3.3V, RL=8Ω, BD Mode, fS=48kHz (unless otherwise noted)
Symbol
Parameter
APA3169
Test Conditions
Unit
Min.
Typ.
Max.
DC CHARACTERISTICS (CONT.)
OLPC
Overload protection counter
fPWM=384kHz
-
0.63
-
ms
IOC
Overcurrent limit protection
Resistor - programmable, max.
current
-
4.5
-
A
IOCT
Overcurrent response time
-
150
-
ns
-
3
-
kΩ
14.5
16
-
ROUT
Internal pull-down resistance at
each OUT_X
Ccaopnanceitcoter dchwahrgeen.
drivers are tristated to provide
bootstrap
AC CHARACTERISTICS
VPVDD=18V
BTL,THD+N=1%,
fin=1kHz,RL=8Ω
BTL,THD+N=10
%,fin=1kHz,RL=8
Ω
PO
Output Power
PBTL,THD+N=1
%,fin=1kHz,RL=4
Ω
PBTL,THD+N=1
0%,fin=1kHz,RL=
4Ω
SE,THD+N=1%,fi
n=1kHz,RL=4Ω
SE,THD+N=10%
,fin=1kHz,RL=4Ω
THD+N
Vn
Total Harmonic Distortion Plus
Noise
Noise Output Voltage
VPVDD=12V
6.5
7.2
-
VPVDD=8V
2.9
3.2
-
VPVDD=18V
-
20
-
VPVDD=12V
-
9
-
VPVDD=8V
-
4
-
VPVDD=18V
-
30.5
-
VPVDD=12V
-
13.7
-
VPVDD=18V
-
37.1
-
VPVDD=12V
-
16.9
-
VPVDD=18V
-
7.5
-
VPVDD=12V
-
3.4
-
VPVDD=18V
-
9.5
-
VPVDD=12V
-
4.3
-
-
0.06
-
-
0.13
-
-
0.2
-
-
200
-
VPVDD=18V,
Po=1W
VPVDD =12V,
fin=1kHz,RL=8Ω
Po=1W
VPVDD=8V,
Po=1W
With A-Weighting Filter
(Volume=0dB)
Crosstalk
Channel Separation
PO=0.25W, RL=8Ω, fin=1kHz
-
-72
-
SNR
Signal to Noise Ratio
RL=8Ω, Po=16W, A-Weighting
Filter (Volume =0dB)
-
95
-
AttMute
Mute Attenuation
fin=1kHz, RL=8Ω, VO=1Vrms
-
-70
-
Shutdown Attenuation
fin=1kHz, RL=8Ω, VO=1Vrms
-
-110
-
Attshutdown
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
5
W
%
µVms
dB
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APA3169
Serial Audio Ports Slave Mode
Over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
APA3169
Test Conditions
Min.
Typ.
Max.
1.024
-
12.288
Unit
fSCLK
Frequency, SCLK 32xfS, 48xfS,
64xfS
tSetup1
Setup Time, LRCLK to SCLK
Rising Edge
10
-
-
tHold1
Hold Time, LRCLK to SCLK
Rising Edge
10
-
-
tSetup2
Setup Time, SDIN to SCLK
Rising Edge
10
-
-
Hold Time, SDIN to SCLK Rising
Edge
10
-
-
LRCLK Frequency
32
48
192
LRCLK Duty Cycle
40
50
60
SCLK Duty Cycle
40
50
60
SCLK Rising Edges Between
LRCLK Riding Edges
32
-
64
SCLK
edges
LRCLK Clock Edge With Respect
To The Falling Edge of SCLK
-1/4
-
1/4
SCLK
period
-
-
8
ns
tHold
t(edge)
tr/tf
CL=30pF
MHz
ns
Rise/Fall Time for SCLK/LRCLK
kHz
%
(SCLK/LRCLK)
tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
Figure 1. Slave Mode Serial Data Interface Timing
Copyright  ANPEC Electronics Corp.
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APA3169
I2C Serial Control Port Operation
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
Symbol
Parameter
Test Conditions
APA3169
Min.
Typ.
Max.
fSCL
Frequency, SCL
-
-
400
tW(H)
Pulse Duration, SCL High
No Wait States
0.6
-
-
tW(L)
Pulse Duration, SCL Low
1.3
-
-
tr
Rise Time, SCL and SDA
-
-
300
tf
Fall Time, SCL and SDA
-
-
300
tsetup1
Setup Time, SCL to SDA
100
-
-
thold1
Hold Time, SCL to SDA
0
-
-
t(buf)
Bus Free Time Between Stop
and Start Condition
1.3
-
-
tsetup2
Setup Time, SCL to Start
Condition
0.6
-
-
thold2
Hold Time, Start condition to SCL
0.6
-
-
tsetup3
Setup Time, SCL to Stop
Condition
0.6
-
-
-
-
400
Load Capacitance for Each Bus
Line
CL
tw(H)
tf
tw(L)
Unit
kHz
µs
ns
µs
pF
tr
SCL
tsu1
th1
SDA
Figure 2. SCL and SDA Timing
SCL
tsu2
th2
t(buf)
tsu3
SDA
Stop Condition
Start Condition
Figure 2. SCL and SDA Timing
Copyright  ANPEC Electronics Corp.
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APA3169
Reset Timing
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to “Recommended Use Model” section on usage of all terminals.
Symbol
tp(RST)
td(12C_Ready)
Parameter
Pulse Duration, RESET Active.
Test Conditions
No Load
Time to Enable I2C
APA3169
Min.
Typ.
Max.
Unit
100
-
-
µs
-
-
13.5
ms
RESET
tw(RESET)
2
I2C Active
I C Active
td(I2C_Ready)
Figure 4. Reset Timing
Copyright  ANPEC Electronics Corp.
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APA3169
Typical Operating Characteristics, BTL Configuration
THD+N vs. Frequency
THD+N vs. Frequency
10
10
Po=0.5W
0.1
PVDD=8V
RL=8Ω
AUX-0025
AES-17(20kHz)
0.01
0.001
20
50 100
Po=5W
1
THD+N (%)
THD+N (%)
Po=1W
Po=2.5W
1
2k
5k
PVDD=12V
RL=8Ω
AUX-0025
AES-17(20kHz)
0.001 20
20k
50 100
5k
20k
10
Po=5W
Po=2.5W
Po=1W
0.1
PVDD=18V
RL=8Ω
AUX-0025
AES-17(20kHz)
0.01
20
50 100
2k
5k
0.001
20 k
PVDD=24V
RL=8Ω
AUX-0025
AES-17(20kHz)
20
50 100
Frequency (Hz)
THD+N vs. Output Power
1
THD+N (%)
1
0.1
0.001
10m
100m
1
PVDD=8V
RL=8Ω
Duty=97.7%
AUX-0025
AES-17(20kHz)
2
5k
20 k
5
10
0.1
0.01
PVDD=12V
RL=8Ω
Duty=97.7%
AUX-0025
AES-17(20kHz)
Fin=10kHz
Fin=1kHz
Fin=20Hz
0.001 10m
50
Output Power (W)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
2k
THD+N vs. Output Power
10
Fin=10kHz
Fin=1kHz
Fin=20Hz
500 1 k
Frequency (Hz)
10
0.01
Po=1W
0.1
0.01
500 1 k
Po=2.5W
Po=5W
1
THD+N (%)
1
THD+N (%)
2k
THD+N vs. Frequency
THD+N vs. Frequency
10
THD+N (%)
500 1 k
Frequency (Hz)
Frequency (Hz)
0.001
Po=1W
0.1
0.01
500 1k
Po=2.5W
100m
1
2
5
10
50
Output Power (W)
9
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APA3169
Typical Operating Characteristics, BTL Configuration(Cont.)
THD+N vs. Output Power
THD+N vs. Output Power
THD+N (%)
1
10
PVDD=18V
RL=8Ω
Duty=97.7%
AUX-0025
AES-17(20kHz)
0.1
0.1
0.01
0.01
Fin=10kHz
Fin=1kHz
Fin=20Hz
Fin=10kHz
Fin=1kHz
Fin=20Hz
0.001
10 m
100 m
1
2
5
10
0.001
10m
50
100m
Output Power (W)
5
10
50
+0
PVDD=8V
Po=1W
RL=8Ω
AUX-0025
10~22kHz
PVDD=12V
Po=1W
RL=8Ω
AUX-0025
10~22kHz
- 20
Crosstalk (dB)
- 20
Crosstalk (dB)
2
Crosstalk vs. Frequency
Crosstalk vs. Frequency
- 40
Left to Right
Right to Left
- 60
- 40
Left to Right
Right to Left
- 60
- 80
- 80
20
50 100
500 1 k
2k
5k
- 100
20 k
20
50 100
Crosstalk vs. Frequency
5k
20 k
+0
PVDD=18V
Po=1W
RL=8Ω
AUX-0025
10~22kHz
Crosstalk (dB)
- 20
- 40
Left to Right
Right to Left
- 60
- 80
-100
20
2k
Crosstalk vs. Frequency
+0
- 20
500 1 k
Frequency (Hz)
Frequency (Hz)
Crosstalk (dB)
1
Output Power (W)
+0
-100
T
PVDD=24V
RL=8Ω
Duty=97.7%
AUX-0025
AES-17(20kHz)
1
THD+N (%)
10
PVDD=24V
Po=1W
RL=8Ω
AUX-0025
10~22kHz
- 40
Left to Right
Right to Left
- 60
- 80
50 100
500 1 k
2k
5k
-100
20
20 k
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
50 100
500 1 k
2k
5k
20 k
Frequency (Hz)
10
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APA3169
Typical Operating Characteristics, BTL Configuration(Cont.)
Output Power vs. Supply
Voltage
Efficiency vs. Output Power
100
RL=8Ω
Duty=97.7%
35
90
80
PVDD=24V
30
Efficiency(%)
BTL Output Power_OutAB(W)
40
25
20
THD+N=10%
15
PVDD=18V
70
PVDD=12V
60
PVDD=8V
50
40
30
10
20
THD+N=1%
5
RL=8Ω
Duty=97.7%
10
0
0
8
10
12
14
16
18
20
22
24
26
0
Supply Voltage(V)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
2
4
6
8
10 12 14 16 18 20 22 24
OutAB Output Power(W)
11
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APA3169
Typical Operating Characteristics, SE Configuration
THD+N vs. Frequency
10
1
1
THD+N (%)
THD+N (%)
THD+N vs. Frequency
10
0.1
Po=1W
Po=2.5W
Po=0.5W
0.001
20
50 100
500 1 k
2k
5k
20k
PVDD=18V
RL=4Ω
AUX-0025
AES-17(20kHz)
20
1
1
0.1
Po=1W
0.01 PVDD=24V
RL=4Ω
AUX-0025
AES-17(20kHz)
0.001
20
50 100
0.1
0.01
500 1 k
2k
2k
500 1k
5k
20k
THD+N vs. Output Power
10
THD+N (%)
THD+N (%)
THD+N vs. Frequency
10
Po=2.5W
50 100
Frequency (Hz)
Frequency (Hz)
Po=5W
Po=1W
Po=2.5W
Po=5W
0.01
0.01 PVDD=12V
RL=4Ω
AUX-0025
AES-17(20kHz)
0.001
0.1
5k
0.001
10 m
20k
Frequency (Hz)
PVDD=24V
PVDD=18V
PVDD=12V
Fin=1kHz
PVDD=8V
RL=4Ω
Duty=97.7%
AUX-0025
AES-17(20kHz)
100 m
1
2
5
10 20 50
Output Power (W)
Output Power vs. Supply Voltage
22
RL=4Ω
Duty=97.7%
SE Output Power_OutA(W)
20
18
16
14
12
10
THD+N=10%
8
6
4
THD+N=1%
2
0
8
10
12
14
16
18
20
22
24
26
Supply Voltage(V)
Copyright  ANPEC Electronics Corp.
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APA3169
Typical Operating Characteristics, PBTL Configuration
THD+N vs. Frequency
THD+N vs. Frequency
10
10
Po=1W
0.1
0.001
20
50 100
500 1 k
2k
5k
0.001
20 k
PVDD=12V
RL=4Ω
AUX-0025
AES-17(20kHz)
20
50 100
500 1 k
Frequency (Hz)
Po=1W
0.001
50 100
500 1 k
2k
5k
PVDD=24V
RL=4Ω
AUX-0025
AES-17(20kHz)
20k
20
50 100
2k
5k
20k
THD+N vs. Output Power
THD+N vs. Output Power
10
10
PVDD=12V
RL=4Ω
Duty=97.7%
1 AUX-0025
AES-17(20kHz)
THD+N (%)
PVDD=8V
RL=4Ω
Duty=97.7%
1 AUX-0025
AES-17(20kHz)
THD+N (%)
500 1 k
Frequency (Hz)
Frequency (Hz)
0.1
0.01
0.1
0.01
Fin=1kHz
Fin=10kHz
Fin=1kHz
Fin=20Hz
0.001
10 m
Po=1W
0.1
0.01
0.01 PVDD=18V
RL=4Ω
AUX-0025
AES-17(20kHz)
Po=2W
Po=5W
1
0.1
0.001
20
20k
THD+N vs. Frequency
THD+N (%)
THD+N (%)
Po=2W
5k
10
10
Po=5W
2k
Frequency (Hz)
THD+N vs. Frequency
1
Po=1W
1
0.01
0.01 PVDD=8V
RL=4Ω
AUX-0025
AES-17(20kHz)
Po=2W
Po=5W
1
THD+N (%)
THD+N (%)
Po=2W
Po=5W
1
Fin=10kHz
Fin=20Hz
100 m
1
2
5
10
0.001
10 m
50
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
100 m
1
2
5
10
50
Output Power (W)
Output Power (W)
13
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APA3169
Typical Operating Characteristics, PBTL Configuration(Cont.)
THD+N vs. Output Power
THD+N vs. Output Power
10
10
THD+N (%)
THD+N (%)
PVDD=18V
RL=4Ω
Duty=97.7%
1 AUX-0025
AES-17(20kHz)
0.1
0.01
PVDD=24V
RL=4Ω
Duty=97.7%
1 AUX-0025
AES-17(20kHz)
0.1
0.01
Fin=1kHz
Fin=10kHz
0.001
10 m
Fin=10kHz
Fin=1kHz
Fin=20Hz
Fin=20Hz
100 m
1
2
5
0.001
10 m
10 20 50
100 m
1
2
5
10 20 50
Output Power (W)
Output Power (W)
Output Power vs. Supply
Voltage
PBTL Output Power_OutABCD(W)
60
50
40
30
20
10
0
8
10
12
14
16
18
20
22
24
26
Supply Voltage(V)
Copyright  ANPEC Electronics Corp.
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APA3169
Pin Description
PIN
FUNCTION
I/O/P
NO.
NAME
1
OUT_A
2,3
PVDD_A
P
Power supply input
4
BS_A
P
High-side bootstrap supply for half-bridge A
5
VCLAB
P
internal 3.3V reference voltage
6
TM1
I
Test mode input
7
TM2
I
Test mode input
8
PBTL
I
low means BTL or SE mode;high means PBTL mode
O
Output,half-bridge A
9
AVSS
P
analog 3.3V supply ground
10
PLL_FLTM
O
PLL negative loop filter
11
PLL_FLTP
O
PLL postive loop filter
12
VR_ANA
P
analog regulator
13
AVDD
P
3.3V amalog power supply
14
A_SEL
I/O
15
MCLK
I
Master clock input
16
TP1
I/O
Test mode probe
17
TP2
I/O
18
VR_DIG
P
digital regulator
19
PDN_N
I
Power down,active low
20
LRCLK
I
input serial audio data left/right clock
21
SCLK
I
Serial audio data clock.
22
SDIN
I
Serial audio data input
23
SDA
I/O
24
SCL
I
I2C serial control clock input
25
RESET_N
I
Reset,active low
26
TP3
I/O
Test mode probe
27
DVDD
P
3.3V digital power supply
28
DVSS
P
Digital ground
29
DGND
P
digital ground for power stage
30
AGND
P
analog ground for power stage
31
VREG
P
Not to be used for powering external circuitry
32
VCLCD
P
internal 3.3V reference voltage
33
BS_D
P
High-side bootstrap supply for half-bridge D
34,35
PVDD_D
P
Power supply input
36
OUT_D
O
output,half bridge D
37,38
PGND_CD
P
Power ground for half-bridge C and D
39
OUT_C
O
output,half-bridge C
input: device address, output : fault
Test mode probe
I2C serial control data interface input/output
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
15
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APA3169
Pin Description
PIN
I/O/P
FUNCTION
NO.
NAME
40,41
PVDD_C
42
BS_C
P
High-side bootstrap supply for half-bridge C
43
BS_B
P
High-side bootstrap supply for half-bridge B
44,45
PVDD_B
P
Power supply input
46
OUT_B
O
output ,half bridge B
47,48
PGND_AB
P
Power ground for half-bridge A and B
Power supply input
TP1
TP2
TP3
OutA
OutB
OutC
OutD
Block Diagram
IIS
Test Out
REGULATOR
OutC
OutD
Valid
Error_B
OTW
OutA
OutB
Power Stage
Output-map
Register
DAP
FIR
CKG
R
L
LFE
Interpolation
PWM Processor
SDM
PWR_SEQ
PCM to
PWM
PLL
P
PRE_DIV
MCLK
TM2
TM1
IIC
Serial
Control
SDA
SCL
A_SEL
R
SDIN
SCLK
LRCLK
RESETN
PDN
IIS
Serial
Audio
Port
L
FIFO
Figure 5. Block Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
16
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APA3169
L
R
Sub_channel
Block Diagram
Mix0
Mixer
Mix1
Mix0
Mix2
Mixer
Mix1
Mix0
Mix1
Mix2
Mixer
0x60
0x52
0x51
Post_scale
DRC1
DRC1
Master_Vol
Ch3_vol
0x5E~5F
0x55
Mix1
Mix2
Mix0
1BQ
0x5B
0x5A
0x31
Mix3
1BQ
0x54
1BQ
0x32~34
3BQ
De_emphasis
De_emphasis
DC_Blocking
DC_Blocking
Mix1
Mixer
Mix0
0x30
1BQ
Mix1
Mix0
Mixer
0x61
0x54
Mix1
1BQ
0x29
Mix0
Mixer
Mixer
Mixer
Mix2
0x2A
1BQ
Mix3
0x53
0x5C~5D
2BQ
0x58~59
0x2B~2D
3BQ
2BQ
0x53
Mix2
Mixer
Ch4_vol
2BQ
Ch2_vol
Ch1_vol
L
R
Pre_scale
Figure 6. DAP Block Diagram
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
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APA3169
Typical Application Circuit
2.0 Channel
AVDD
10kO
470 O
470 O
JP1
0.047 µF
4700pF
0. 047µF
2200 pF
1µF
4700 pF
VR_ANA
PLL_FLTP
PLL_FLTM
AVSS
PBTL
TM2
TM1 22.1kO
VCLAB
BS_A
PVDD_A
PVDD_A
OUT_A
AVDD
10µ F
0.1µF
0.1µ F
/PDN
LRCK
SCLK
SDIN
SDA
SCL
0.1µ F
22µH
0. 68µF
220µ F
AVDD
A_SEL
10kO MCLK
18. 2kO TP1
TP2
10kO VR_DIG
/PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
0. 68µF
48
47
46
45
44
43
42
41
40
39
38
37
APA3169
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
22µH
0.033µ F
0.033µ F
0.1µ F
PVDD
0.1µ F
22µH
0.68µF
/RESET_N
TP3
DVDD
DVSS
DGND
AGND
VRE G
VCLCD
BS_D
PVDD_D
PVDD_D
O UT_D
25
26
27
28
29
30
31
32
33
34
35
36
4.7µ F
AVDD
PVDD
12
11
10
9
8
7
6
5
4
3
2
1
0O
A_SEL
MCLK
0.033µ F
/RESET
DVDD
10µ F
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
0.1µF
PVDD
0.68µF
0.1µ F
220µ F
22µH
0.1µ F
1µF
18
0.033 µF
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APA3169
Typical Application Circuit
2.1 Channel
AVDD
VDD
10kO
470 O
10kO
0.047 µF
220µ F
10kO
4700pF
0.047µF
470 O
JP1
1µF
4700 pF
0.1µF
0.1µ F
/PDN
LRCK
SCLK
SDIN
SDA
SCL
0.1µ F
22µH
AVDD
A_SEL
10kO MCLK
18. 2kO TP1
TP2
10kO VR_DIG
/PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
0.68µF
220µ F
10kO
220µ F
0.68µF
48
47
46
45
44
43
42
41
40
39
38
37
APA3169
VDD
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
10kO
220µ F
22µH
0.033µ F
0.033µ F
0.1µ F
PVDD
0.1µ F
22µH
0.68µF
/RESET_N
TP3
DVDD
DVSS
DGND
AGND
VRE G
VCLCD
BS_D
PVDD_D
PVDD_D
O UT_D
25
26
27
28
29
30
31
32
33
34
35
36
4.7µ F
AVDD
PVDD
12
11
10
9
8
7
6
5
4
3
2
1
0O
A_SEL
MCLK
0.033µ F
VR_ANA
PLL_FLTP
PLL_FLTM
AVSS
PBTL
TM2
TM1 22.1kO
VCLAB
BS_A
PVDD_A
PVDD_A
OUT_A
AVDD
10µ F
220µ F
2200 pF
/RESET
DVDD
10µ F
0.1µF
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
PVDD
0.68µF
0. 1µ F
220µ F
22µH
0.1µ F
1µF
0.033 µF
19
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APA3169
Typical Application Circuit
PBTL
AVDD
10kO
470 O
4700pF
0.047µF
470 O
JP1
0.047 µF
2200 pF
1µF
4700 pF
VR_ANA
PLL_FLTP
PLL_FLTM
AVSS
PBTL
TM2
TM1 22.1kO
VCLAB
BS_A
PVDD_A
PVDD_A
OUT_A
AVDD
10µ F
0.033µ F
0.1µF
A_SEL
MCLK
0.1µ F
/PDN
LRCK
SCLK
SDIN
SDA
SCL
0.68µ F
220µ F
AVDD
A_SEL
10kO MCLK
18. 2kO TP1
TP2
10kO VR_DIG
/PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
APA3169
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
0.033µ F
0.033µ F
0.1µ F
PVDD
0.1µ F
/RESET_N
TP3
DVDD
DVSS
DGND
AGND
VRE G
VCLCD
BS_D
PVDD_D
PVDD_D
O UT_D
25
26
27
28
29
30
31
32
33
34
35
36
4.7µ F
AVDD
0.1µ F
22µH
12
11
10
9
8
7
6
5
4
3
2
1
0O
PVDD
/RESET
DVDD
10µ F
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
0.1µF
PVDD
0.68µ F
0. 1µ F
220µ F
22µ H
0.1µ F
1µF
20
0.033 µF
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APA3169
Function Description
POWER SUPPLY
To facilitate system design, the APA3169 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply.
An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring
only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BS_x), and power-stage supply pins (PVDD_x). The gate drive voltages (VCLAB and VCLCD) are
derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their
associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must
be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BS_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is charged
through an internal diode connected between the gate-drive regulator output pin (VCL_x) and the bootstrap pin. When
the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus
provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in
the range from 256 kHz to 384 kHz, it is recommended to use 33-nF 50-V X7R capacitors, size 0603 or 0805, for the
bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to
keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For
optimal electrical performance, EMC compliance, and system reliability, it is important that each PVDD_x pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The APA3169 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function,
rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load
impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second
protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z)
state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed.
Current limiting and overcurrent protection are not independent for half-bridges.
That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are
shut down.
Overtemperature Protection
The APA3169 has over temperature-protection system. If the device junction temperature exceeds 150OC (nominal),
the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)
state and /FAULT being asserted low. The APA3169 recovers automatically once the temperature drops approximately
30 oC
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
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PWM Section
APA3169
Function Description (Cont.)
Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the APA3169 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit and ensures that all circuits are fully operational when
the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and AVDD are independently
monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge
outputs immediately being set in the high-impedance (Hi-Z) state and /FAULT being asserted low.
SERIAL DATAINTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The APA3169 DAP accepts serial data in 16-,
20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
PWM Section
The APA3169 DAP device uses noise-shaping to achieve high power efficiency and high-performance digital audio
reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The
PWM section accepts PCM data from the DAP and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters are included and can be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 98.4%.
SERIAL INTERFACE CONTROL AND TIMING
The I2S mode is set by writing to register 0x04.
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48,
or 64xfs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising
edge of bit clock. The DAP masks unused trailing data bit positions.
32 Clks
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
1
0
23 22
20-Bit Mode
19 18
LSB
9
8
5
4
5
4
1
0
1
0
1
0
20-Bit Mode
5
4
1
0
19 18
16-Bit Mode
16-Bit Mode
15 14
MSB
24-Bit Mode
1
0
15 14
Figure 7. I2S 64 fS Format
Copyright  ANPEC Electronics Corp.
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APA3169
Function Description (Cont.)
24 Clks
24 Clks
LRCLK (Note Reversed Phase)
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
17 16
9
8
5
4
3
2
LSB
MSB
24-Bit Mode
1
0
20-Bit Mode
23 22
17 16
9
8
5
4
13 12
5
4
1
0
1
0
3
2
1
20-Bit Mode
19 18
13 12
5
4
1
0
19 18
16-Bit Mode
15 14
16-Bit Mode
9
8
1
0
15 14
9
8
Figure 8. I2S 48 fS Format
16 Clks
16Clks
LRCLK (Note Reversed Phase)
Right Channel
Left Channel
SCLK
SCLK
MSB
16-Bit Mode
LSB
15 14 13 12 11 10
9
8
5
4
3
2
LSB
MSB
16-Bit Mode
1
0
15 14 13 12 11 10
9
8
5
4
3
2
1
Figure 9. I2S 32 fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define the data for the left channel and the right channel when the data being
transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK is low. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines when LRCLK toggles. The data
is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.
32Clks
LRCLK
32Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
1
0
MSB
24-Bit Mode
23 22
20-Bit Mode
19 18
9
8
5
4
5
4
1
0
1
0
1
0
20-Bit Mode
5
4
1
0
19 18
16-Bit Mode
16-Bit Mode
15 14
LSB
1
0
15 14
Figure 10. Left-Justified 64 fS Format
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
23
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APA3169
Function Description (Cont.)
24Clks
LRCLK
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
17 16
9
8
5
4
3
2
1
0
23 22
20-Bit Mode
19 18
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
20-Bit Mode
13 12
5
4
1
0
19 18
16-Bit Mode
15 14
LSB
MSB
24-Bit Mode
16-Bit Mode
9
8
1
0
15 14
8
Figure 11. Left-Justified 48 fS Format
16 Clks
LRCLK
16Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
LSB MSB
16-Bit Mode
15 14 13 12 11 10
9
8
5
4
3
2
1
0
LSB
15 14 13 12 11 10
9
8
5
4
3
2
1
0
Figure 12. Left-Justified 32 fS Format
Right-Justified
Right-justified (RJ) timing uses LRCLK to define the data for the left channel and the right channel when the data
being transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK low. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. After LRCLK toggles, for 24bit data, the first bit of data appears on the data
8 bit-clock. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is
written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.
32 Clks
LRCLK
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
MSB
24-Bit Mode
0
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit
Mode
20-Bit
Mode
19 18
15 14
1
0
16-Bit
Mode
16-Bit
Mode
15 14
1
0
Figure 13. Right-Justified 64 fS Format
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APA3169
Function Description (Cont.)
24 Clks
LRCLK
24 Clks
Right Channel
Left Channel
SCLK
SCLK
LS
B
MSB
24-Bit Mode
23 22
20-Bit
Mode
19 18
15 14
19 18
15 14
16-Bit
Mode
15 14
6
6
6
5
2
5
2
5
2
1
1
1
LS
B
MSB
24-Bit Mode
0
23 22
20-Bit
Mode
0
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
16-Bit
Mode
0
Figure 14. Right-Justified 48 fS Format
16 Clks
LRCLK
16Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12 11 10
LSB MSB
16-Bit Mode
9
8
5
4
3
2
1
0
15 14 13 12 11 10
LSB
9
8
5
4
3
2
1
0
Figure 15. Right-Justified 32 fS Format
I2C Serial Control Interface
The APA3169 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol. Besides, it
provides both 100kHz and 400kHz data transfer rates to single and multiple bytes write and read operations.
This is a slave only device, and it doesn’t support a multi-master bus environment or wait state insertion. The function
of the control interface is to read device status and to program the registers of the device.
The DAP supports the standard-mode I2C bus operation (100kHz maximum) and the fast I2C bus operation (400kHz
maximum). Without I2C wait cycles, the DAP performs I2C operations.
General I2C Operation
The I2C bus uses SDA (data) and SCL (clock) to communicate between integrated circuits in a system. Data is
transferred on the bus serially one bit at a time. With the most significant bit (MSB) transferred first, the address and
data can be transferred in byte (8bit) format. In addition, each byte transferred on the bus is acknowledged by the
receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start
condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the SDA when the clock is high to indicate start and stop conditions. A high-to-low
transition on SDA indicates a start, and a low-to-high transition indicates a stop. Normal data bit transitions must
occur within the low time of the clock. These conditions are shown in Figure 10. The master generates the 7bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The APA3169 holds SDA low during the acknowledge clock to indicate an acknowledgment. When this
occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA
and SCL signals to set the high level for the bus.
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APA3169
Function Description (Cont.)
SDA
7-Bit Slave Address
R/
W
7 6 5 4 3 2 1 0
A
8-Bit Register Address (N)
A
7 6 5 4 3 2 1 0
8-Bit Register Data for
Address (N)
7 6 5 4 3 2 1 0
A
8-Bit Register Data for
Address (N)
A
7 6 5 4 3 2 1 0
SCL
Start
Stop
Figure 16. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word
transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in
Figure 16.
Pin A_SEL defines the I2C device address. An external 15kΩ pulldown on this pin gives a device address of
0x34 and a 15kΩ pullup gives a device address of 0x36. The 7-bit address is 0011 010 (0x34) or 0011 011
(0x36).
Single- and Multiple-Byte Transfers
The serial control interface supports single-byte and multiple-byte (R/W) operations for sub-addresses 0x00 to 0x1F.
However, for the sub-addresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write
operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the sub-address
assigned, as long as the master device continues to respond with acknowledges. If a particular sub-address does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that
are required for each specific sub-address.
Supplying a sub-address for each sub-address transaction is referred to as random I2C addressing. The APA3169
also supports sequential I2C addressing. For write transactions, if a sub-address is issued and followed by data for
that sub-address and the 15 sub-addresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 sub-addresses is successfully received by the APA3169. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is
transmitted, determines how many sub-addresses are written. As was true for random addressing, sequential
addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last sub-address is discarded. However, if all other data written is accepted, only the
incomplete data is discarded.
Single-Byte Write
As shown in Figure 17, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device address and the
read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes
corresponding to the APA3169 internal memory address being accessed. After receiving the address byte, the APA3169
again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory
address being accessed. After receiving the data byte, the APA3169 again responds with an acknowledge bit. Finally,
the master device transmits a stop condition to complete the single-byte data write transfer.
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APA3169
Function Description (Cont.)
Start
Condition
Acknowledge
Acknowledge
Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address
and Read/ Write Bit
Stop
Condition
Data Byte
Sub-address
Figure 17. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are
transmitted by the master device to the DAP as shown in Figure 18. After receiving each data byte, the APA3169
responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
I2C Device Address
and Read/ Write Bit
A2
A1
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
Sub-address
First Data Byte
Acknowledge
Acknowledge
D0 ACK D7
Other Data Bytes
D0 ACK
Last Data Byte
Stop
Condition
Figure 18. Multiple-Byte Write Transfer
Single-Byte Read
As shown in Figure 19, a single-byte data read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. For the data read transfer, both a write followed by a read are
actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read.
As a result, the R/W bit becomes a 0. After receiving the APA3169 address and the read/write bit, APA3169 responds
with an acknowledge bit. Besides, after sending the internal memory address byte or bytes, the master device
transmits another start condition followed by the APA3169 address and the read/write bit again. This time the read/
write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the APA3169 again
responds with an acknowledge bit. And then, the APA3169 transmits the data byte from the memory address being
read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to
complete the single byte data read transfer.
Start
Condition
Acknowledge
A6 A5
Acknowledge
A1 A0 R/W ACK A7 A6
I2C Device Address
and Read/ Write Bit
A1 A0 ACK
Sub-address
Acknowledge
A6 A5
Repeat Start
Condition
Not Acknowledge
A1 A0 R/W ACK D7 D6
I2C Device Address
and Read/ Write Bit
D1 D0 ACK
Data Byte
Stop
Condition
Figure 19. Single-Byte Read Transfer
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APA3169
Function Description (Cont.)
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are
transmitted by the APA3169 to the master device as shown in Figure 20. Except for the last data byte, the master device
responds with an acknowledge bit after receiving each data byte.
Start
Condition
Repeat Start
Condition
Acknowledge
Acknowledge
A6
A0 R/WACK A7 A6
I2C Device Address
and Read/ Write Bit
A1 A0 ACK
A6
Acknowledge
A0 R/WACK D7
I2C Device Address
and Read/ Write Bit
Subaddress
Acknowledge
Acknowledge Not Acknowledge
D0 ACK D7
First Data
Byte
D0 ACK D7
Other Data
Bytes
D0 ACK
Last Data
Byte
Stop
Condition
Figure 20. Multiple-Byte Read Transfer
Output Mode and MUX Selection
PWM1
CH1_audio
2.0 BTL BD
PWM2
Reg Setting
0x05 (2) = 0
PWM3
CH2_audio
PWM4
PWM1
CH1_audio
PWM2
2.1 SE,BTL- BD
CH2_audio
Reg Setting
0x05 (2) = 1
PWM3
CH3_audio
PWM4
Figure 21. Output Mode and MUX Selection
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APA3169
Function Description (Cont.)
2.1-Mode Support
The APA3169 supports 2.0-mode and 2.1-mode operation.To enable 2.1 mode, register 0x05 bit D2 must be set to 1.
Single-Filter PBTL-Mode Support
The APA3169 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC
filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of halfbridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge.
There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating.
PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be
written with a value of 0x01 10 32 45.
Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/
Output Level (dB)
right channels.
The DRC input/output diagram is shown in Figure 22.
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• The DRC has adjustable threshold, offset, and compression levels.
K
O
T
Input Level (dB)
1:1 Transfer Function
Implemented Transfer Function
Figure 22. Dynamic Range Control
BiQuad Structure
All biquads use a 2nd order IIR filter structure as shown below. Each biquad has 3 coefficients on the direct path (b0,
b1, b2) and 2 coefficients on feedback path (a1 and a2) which is shown in the diagram.
b0
x(n)
Magnitude
Trunction
Σ
y(n)
Z-1
b1
a1
Z-1
Z-1
b2
a2
Z-1
Figure 24. Biquad Filter
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APA3169
Function Description (Cont.)
26Bit 3.23 Number Format
All mixer gain coefficients are 26 bit coefficients and use a 3.23 number format. Numbers formatted as 3.23 numbers
means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown
in Figure 18.
2-23 Bit
2-5 Bit
2-1 Bit
20 Bit
21 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
Figure 25. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting and is shown in Figure 25. If the
MSB is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the MSB is a
logic 1, and then the number is a negative number. In this case, every bit must be inverted, a 1 added to the result, and
then the weighting shown in Figure 26 applied to obtain the magnitude of the negative number.
21 Bit
20 Bit
2-1 Bit
2-4 Bit
2-23 Bit
(1 or 0) x21+
(1 or 0) x20+
(1 or 0) x2 -1+
(1 or 0) x2-4+
(1 or 0) x2-23
Figure 26. Conversion Weighting Facroes 3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32 bit binary numbers. The format of the 32 bit number
(4 byte or 8 digit hexadecimal number) is shown in Figure 27.
Sign Bit
Integer
Digit 1
u u u
u
Coefficient
digit 8
u
u S x
Coefficient
digit 7
Fraction
Digit 1
x
x
x
x
Coefficient
digit 6
Fraction
Digit 2
x
x
x
x
Coefficient
digit 5
Fraction
Digit 3
x
x
x
x
Coefficient
digit 4
Fraction
Digit 4
x
x
x
x
Coefficient
digit 3
Fraction
Digit 5
x
x
x
x
Coefficient
digit 2
Fraction
Digit 6
x
x
x
x
0
Coefficient
digit 1
Figure 27. Alignment of 3.23 Coefficient in 32Bit I2C Word
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APA3169
Function Description (Cont.)
Sample Calculation for 3.23 Format
dB
Linear
Decimal
Hex (3.23 Format)
0
1
8388608
00800000
5
1.7782794
14917288
00E39EA8
-5
0.5623413
4717260
0047FACC
X
L = 10(X/20)
D = 8388608 × L
H = dec2hex (D, 8)
dB
Linear
Decimal
Hex (9.17 Format)
0
1
131072
00020000
5
1.7782794
233082.6
00038E7A
-5
0.5623413
X
L = 10
Sample Calculation for 9.17 Format
(X/20)
73707.2
00011FEB
D = 131072 × L
H = dec2hex (D, 8)
Recommended Use Model
Normal Operation
Intialization
Power Down
Shutdown
AVDD/DVDD 3V
3V
tDL-VDDH
tVDDH-DL
SD
tPOR
I2S
MCLK
LRCLK
SCLK
SDIN
I2C
SCL
SDA
tPOR
Clock Errors and
Rate Changes OK
Stable and Valid Clocks
texitSD
Trim
tautodetect
DAP
Config
Other
Config
Stable and
Valid Clocks
tautodetect
Volume and Mute
Commands
Reconfigure DAP After Shutdown
Reconfigure DAP After Shutdown
Exit SD
tenterSD
Enter
SD
tRL-DV
tDV-RH tRH-I2C
RST
tVDD-PVCCL
PVDD/AVCC
tRL-PVCCH
tPVCCH-I2C
tPVCCL-VDDH
10V
7.5V
10V
7.5V
Figure 28. Recommended Command Sequence
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APA3169
Function Description (Cont.)
Recommended Use Model (Cont.)
3V
AVDD/DVDD
/PDN
SCL
SDA
I2C
/RESET
PVDD
Figure 29. Power Loss Sequence
Recommended Command Sequences
The DAP has two groups of commands. One set is for configuration and is intended for use only during initialization.
The other set has built-in click and pop protection and may be used during normal operation while audio is streaming.
The following supported command sequences illustrate how to initialize, operate, and shutdown the device.
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVDD supply as follows:
• Drive RESET=0, PDN=1, and other digital inputs to their desired state while ensuring that all are never more than
2.5V above AVDD/DVDD. Drive RESET =1.
• Ramp up PVDD to at least 8V.
2
3. Configure the DAP via I C.
4. Configure remaining registers.
5. Exit shutdown.
Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown
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APA3169
Function Description (Cont.)
Shutdown Sequence
Enter:
1. Write 0x40 to register 0x05.
2. If desired, reconfigure by returning to step 4 of initialization sequence.
Exit:
1. Write 0x00 to register 0x05.
2. Proceed with normal operation.
Power-down Sequence
Use the following sequence to power-down the device and its supplies:
1. If time permits, enter shutdown ; else, in case of sudden power loss, assert PDN=0.
2. Assert RESET=0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
• Drive all digital inputs low after RESET has been low.
• Ramp down PVDD while ensuring that it remains above 8V until RESET has been low.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and that it is never more
than 2.5V below the digital inputs.
Table 1. Serial Control Interface Register Summary
Sub Address
Register Name
No. of Bytes
Contents
Initialization Values
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x69
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0x80
0x04
Serial data interface
1
Description shown in subsequent section
0x05
A u indicates unused bits.
0x05
1
Description shown in subsequent section
0x4C
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0dB)
0x0B - 0X0D
0x0E
Reserved
Volume configuration register
0x0F
0x10
Modulation limit register
0x11-0x19
0x1A
Start/stop period register
0x1B-0x1F
(1)
1
Description shown in subsequent section
1
Reserved(1)
1
Description shown in subsequent section
1
Reserved(1)
1
Description shown in subsequent section
1
Reserved(1)
0x91
0x02
0x0F
0x20
Input MUX register
4
Description shown in subsequent section
0x0089 7772
0x21
CH4 Source select register
4
Description shown in subsequent section
0x0000 4303
1
Reserved(1)
0x22-0x24
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APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
0x25
Register Name
PWM output MUX register
0x26-0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
ch1_bq[0]
ch1_bq[1]
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
No. of Bytes
Contents
4
Description shown in subsequent section
4
Reserved(1)
20
20
20
20
20
20
20
Initialization Values
0x0102 1345
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
0x30
0x31
0x32
0x33
0x34
0x35
0x36
Register Name
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
ch2_bq[5]
ch2_bq[6]
Copyright  ANPEC Electronics Corp.
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No. of Bytes
20
20
20
20
20
20
20
Contents
Initialization Values
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
Register Name
No. of Bytes
0x37~ 0x3F
Contents
Initialization Values
Reserved(1)
0x40
DRC1-T
4
T[31:0] (9.23 format)
0x007F FFFF
0x41
DRC1-K
4
u[31:26], K[25:0]
0x0080 0000
0x42
DRC1-O
4
u[31:26], O[25:0]
0x0080 0000
0x43
DRC2-T
4
T[31:0] (9.23 format)
0x007F FFFF
0x44
DRC2-K
4
u[31:26], K[25:0]
0x0080 0000
0x45
DRC2-O
4
u[31:26], O[25:0]
0x0080 0000
0x46
DRC control
4
Description shown in subsequent section
0x0000 0000
0x47–0x4F
Reserved(1)
0x50
EQ Control
4
0x51
Ch1 output mixer
12
0x52
0x53
0x54
0x55
Ch2 output mixer
Ch1 input mixer
Ch2 input mixer
Ch3 input mixer
12
16
16
12
Description shown in subsequent section
0x0000 0000
ch1_output_mixer2
0x0707 0707
ch1_output_mixer1
0x0707 0707
ch1_output_mixer0
0x0707 0707
ch2_output_mixer2
0x0707 0707
ch2_output_mixer1
0x0707 0707
ch2_output_mixer0
0x0707 0707
ch1_input_mixer3
0x0808 0808
ch1_input_mixer2
0x0808 0808
ch1_input_mixer1
0x0808 0808
ch1_input_mixer0
0x0808 0808
ch2_input_mixer3
0x0808 0808
ch2_input_mixer2
0x0808 0808
ch2_input_mixer1
0x0808 0808
ch2_input_mixer0
0x0808 0808
ch3_input_mixer2
0x0707 0707
ch3_input_mixer1
0x0707 0707
ch3_input_mixer0
0x0707 0707
0x56
Output Post scale
4
9.17 format
0x0002 0000
0x57
Input Pre scale
4
Description shown in subsequent section
0x0080 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x58
ch1_bq[7]
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
20
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APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
Register Name
ch1_bq[8]
subchannel bq[0]
subchannel bq[1]
ch2_bq[7]
ch2_bq[8]
pseudo_ch2_bq[0]
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
No. of Bytes
20
20
20
20
20
20
Contents
Initialization Values
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
37
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APA3169
Function Description (Cont.)
Table 1. Serial Control Interface Register Summary (Cont.)
Sub Address
0x5F
Register Name
No. of Bytes
pseudo_ch2_bq[1]
0x60
20
Ch4 output mixer
0x61
8
Ch4 input mixer
8
0x62-0xF0
Contents
Initialization Values
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
ch4_output_mixer1
0x0000 0000
ch4_output_mixer0
0x0080 0000
ch4_input_mixer1
0x0040 0000
ch4_input_mixer0
0x0040 0000
Reserved(1)
Note (1): Reserved register should not be accessed
All DAP coefficients are 3.23 format unless specified otherwise.
Clock Control Register (0x00)
The clocks and data rates are automatically determined by the APA3169. The clock control register contains the autodetected clock status. Bits D7-D5 reflect the sample rate. Bits D4-D2 reflect the MCLK frequency.
Table 2. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
-
-
-
-
-
fS=32kHz sample rate
0
0
1
-
-
-
-
-
fS=88.2/96kHz sample rate
0
1
0
-
-
-
-
-
fS=176.4/192kHz sample rate
0
1
1
-
-
-
-
-
fS=44.1/48kHz sample rate (2)
1
0
0
-
-
-
-
-
Reserved
1
0
1
-
-
-
-
-
Reserved(1)
1
1
0
-
-
-
-
-
Reserved(1)
1
1
1
-
-
-
-
-
Reserved(1)
-
-
-
0
0
0
-
-
MCLK frequency=64xfS (3)
-
-
-
0
0
1
-
-
MCLK frequency=128xfS (3)
-
-
-
0
1
0
-
-
MCLK frequency=192xfS (4)
-
-
-
0
1
1
-
-
MCLK frequency=256xfS (2)
-
-
-
1
0
0
-
-
MCLK frequency=384xfS
-
-
-
1
0
1
-
-
MCLK frequency=512xfS
-
-
-
1
1
0
-
-
Reserved (1)
-
-
-
1
1
1
-
-
Reserved (1)
-
-
-
-
-
-
0
-
Reserved (1)
-
-
-
-
-
-
-
0
Reserved (1)
(1)
Note (1): Reserved registers should not be accessed.
Note (2): Default values are in bold
Note (3): Only available for 44.1kHz and 48kHz rates.
Note (4): Rate only available for 32/44.1/48kHz sample rates.
Copyright  ANPEC Electronics Corp.
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APA3169
Function Description (Cont.)
Device Id Register (0x01)
The Anpec ID register contains the ID code for the firmware revision.
Table 3. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
0
1
FUNCTION
Identification code
Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register
(write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
SCLK Error: The number of SCLKs per LRCLK is changing.
LRCLK Error: LRCLK frequency is changing.
Table 4. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
-
-
-
-
-
-
-
MCLK error
-
1
-
-
-
-
-
-
PLL auto clock error
-
-
1
-
-
-
-
-
SCLK error
-
-
-
1
-
-
-
-
LRCLK error
-
-
-
-
0
-
-
-
Reserved
-
-
-
-
-
0
-
-
Reserved
-
-
-
-
-
-
1
-
Over Current, Over Temperature, Over Voltage or Under Voltage
errors
-
-
-
-
-
-
-
1
Over temperature warning (sets around 150OC)
0
0
0
0
0
0
0
0
No errors
Note: Default values are in bold.
System Control Register 1 (0x03)
The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter ( -3dB cutoff < 1Hz ) for each
channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same time as volume
ramp defined in reg 0x0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp
Bits D1-D0: Select de-emphasis.
Table 5. System Control Register 1 (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
0
-
-
-
-
-
-
-
PWM high-pass (dc blocking) disenabled
1
-
-
-
-
-
-
-
PWM high-pass (dc blocking) enabled
-
0
0
0
0
0
-
-
Reserved
-
-
-
-
-
-
0
0
No de-emphasis
-
-
-
-
-
-
0
1
De-emphasis for fS=32kHz
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
FUNCTION
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APA3169
Function Description (Cont.)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
-
-
-
-
-
-
1
0
De-emphasis for fS=44.1kHz
-
-
-
-
-
-
1
1
De-emphasis for fS=48kHz
Note: Default values are in bold.
Serial Data Interface Register (0x04)
As shown in Table 6, the APA3169 supports 9 serial data modes. The default is 24bit, I2S mode.
Table 6. Serial Data Interface Control Register (0x04) Format
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
-
-
-
-
Word Length
Receive Serial Data Interface Format
-
-
-
-
0
0
0
0
16
Right-justified
-
-
-
-
0
0
0
1
20
Right-justified
-
-
-
-
0
0
1
0
24
Right-justified
-
-
-
-
0
0
1
1
16
I2S
-
-
-
-
0
1
0
0
20
I2S
-
-
-
-
0
1
0
0
24
I2S
-
-
-
-
0
1
1
0
16
Left-justified
-
-
-
-
0
Reserved
1
1
20
Left-justified
1
0
0
0
24
Left-justified
-
-
-
-
1
0
0
1
Reserved
-
-
-
-
1
0
1
0
Reserved
-
-
-
-
1
0
1
1
Reserved
-
-
-
-
1
1
0
0
Reserved
-
-
-
-
1
1
0
1
Reserved
-
-
-
-
1
1
1
0
Reserved
-
-
-
-
1
1
1
1
Reserved
Note: Default values are in bold.
System Control Register 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are
shut down (hard mute).
Table 7. System Control Register 2 (0x05)
D7
D6
D5
D4
D3
D2
D1
D0
0
-
-
-
-
-
-
-
Reserved
-
1
-
-
-
-
-
-
Enter all channel shut down (hard mute)
-
0
-
-
-
-
-
-
Exit all channel shut down (Normal operation)
-
-
0
0
1
-
-
-
Reserved
-
-
-
-
-
0
-
-
2.0 mode (2 BTL)
-
-
-
-
-
1
-
-
2.1 mode (2 SE + 1 BTL)
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
FUNCTION
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APA3169
Function Description (Cont.)
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
0
-
A_SEL configured as input
-
-
-
-
-
-
1
-
A_SEL configured as FAULT output
-
-
-
-
-
-
-
0
Reserved
FUNCTION
Note: Default values are in bold.
Soft Mute Register (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 8. Soft Mute Register (0x06)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
-
-
-
Reserved
-
-
-
-
-
1
-
-
Soft mute channel 3
-
-
-
-
-
0
-
-
Soft un-mute channel 3
-
-
-
-
-
-
1
-
Soft mute channel 2
-
-
-
-
-
-
0
-
Soft un-mute channel 2
-
-
-
-
-
-
-
1
Soft mute channel 1
-
-
-
-
-
-
-
0
Soft un-mute channel 1
Note: Default values are in bold.
Volume Registers (0x07, 0x08, 0x09)
Step size is 0.5 dB.
Master volume
- 0x07 (default is mute)
Channel-1 volume - 0x08 (default is 0 dB)
Channel-2 volume - 0x09 (default is 0 dB)
Channel-3 volume - 0x0A (default is 0 dB)
Table 9. Volume Registers (0x07, 0x08, 0x09)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
24dB
0
0
1
1
0
0
0
0
0dB
1
1
1
1
1
1
1
0
-103dB
1
1
1
1
1
1
1
1
MUTE (default for master volume)
Note: Default values are in bold.
Volume Configuration Register (0x0E)
Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the D2-D0: number
of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows.
Sample Rate (kHz)
Approximate Ramp Rate
8/16/32
125µs/step
11.025/22.05/44.1
90.7µs/step
12/24/48
83.3µs/step
Copyright  ANPEC Electronics Corp.
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APA3169
Function Description (Cont.)
Table 10. Volume Control Register (0x0E)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
-
1
0
-
-
-
0
FUNCTION
Reserved
Subchannel (ch4) volume = ch1 volume (default)
1
Subchannel volume = register 0x.A
0
Ch3 volume = ch2_volume (default)
1
Ch3 volume = register 0x.A
-
-
-
-
-
0
0
0
Volume slew 512 steps (43ms volume ramp time at 48kHz)
-
-
-
-
-
0
0
1
Volume slew 1024 steps (43ms volume ramp time at 48kHz)
-
-
-
-
-
0
1
0
Volume slew 2048 steps (43ms volume ramp time at 48kHz)
-
-
-
-
-
0
1
1
Volume slew 256 steps (43ms volume ramp time at 48kHz)
-
-
-
-
-
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Volume slew 0 step (Disable)
Note: Default values are in bold.
Modulation Limit Register (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform.
Table 11. Modulation Limit Register (0x10)
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION LIMIT
0
0
0
0
0
–
–
–
Reserved
-
-
-
-
-
0
0
0
Reserved
-
-
-
-
-
0
0
1
98.4%
-
-
-
-
-
0
1
0
97.7%
-
-
-
-
-
1
0
0
96.9%
-
-
-
-
-
0
1
1
96.1%
-
-
-
-
-
1
0
1
95.3%
-
-
-
-
-
1
1
0
94.5%
-
-
-
-
-
1
1
1
93.8%
Note: Default values are in bold.
Start/Stop Period Register (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are
only approximate and vary depending on device activity level and I2S clock stability.
Table 12. Start/Stop Period Register (0x1A)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
-
-
-
-
-
-
0
-
-
-
-
-
Reserved
0
0
-
-
-
No 50% duty cycle start/stop period
1
0
0
0
16.5ms 50% duty cycle start/stop period
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
FUNCTION
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APA3169
Function Description (Cont.)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
-
-
-
0
1
0
0
1
23.9ms 50% duty cycle start/stop period
-
-
-
0
1
0
1
0
31.4ms 50% duty cycle start/stop period
-
-
-
0
1
0
1
1
40.4ms 50% duty cycle start/stop period
-
-
-
0
1
1
0
0
53.9ms 50% duty cycle start/stop period
-
-
-
0
1
1
0
1
70.3ms 50% duty cycle start/stop period
-
-
-
0
1
1
1
0
94.2ms 50% duty cycle start/stop period
-
-
-
0
1
1
1
1
125.7ms 50% duty cycle start/stop period
-
-
-
1
0
0
0
0
164.6ms 50% duty cycle start/stop period
-
-
-
1
0
0
0
1
239.4ms 50% duty cycle start/stop period
-
-
-
1
0
0
1
0
314.2ms 50% duty cycle start/stop period
-
-
-
1
0
0
1
1
403.9ms 50% duty cycle start/stop period
-
-
-
1
0
1
0
0
538.6ms 50% duty cycle start/stop period
-
-
-
1
0
1
0
1
703.4ms 50% duty cycle start/stop period
-
-
-
1
0
1
1
0
942.5ms 50% duty cycle start/stop period
-
-
-
1
0
1
1
1
1256.6ms 50% duty cycle start/stop period
-
-
-
1
1
0
0
0
1728.1ms 50% duty cycle start/stop period
-
-
-
1
1
0
0
1
2513.6ms 50% duty cycle start/stop period
-
-
-
1
1
0
1
0
3299.1ms 50% duty cycle start/stop period
-
-
-
1
1
0
1
1
4241.7ms 50% duty cycle start/stop period
-
-
-
1
1
1
0
0
5655.6ms 50% duty cycle start/stop period
-
-
-
1
1
1
0
1
7383.7ms 50% duty cycle start/stop period
-
-
-
1
1
1
1
0
9897.3ms 50% duty cycle start/stop period
-
-
-
1
1
1
1
0
13196.4ms 50% duty cycle start/stop period
Note: Default values are in bold.
Input Multiplexer Register (0x20)
This register controls the routing of I2S audio to the internal channels.
Table 13. Input Multiplexer Register (0x20)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved
FUNCTION
1
-
-
-
-
-
-
-
Reserved
-
0
0
0
-
-
-
-
SDIN-L to Channel 1
-
0
0
1
-
-
-
-
SDIN-R to Channel 1
-
0
1
0
-
-
-
-
Reserved
-
0
1
1
-
-
-
-
Reserved
-
1
0
0
-
-
-
-
Reserved
-
1
0
1
-
-
-
-
Reserved
-
1
1
0
-
-
-
-
Ground (0) to channel 1
Copyright  ANPEC Electronics Corp.
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APA3169
Function Description (Cont.)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
-
1
1
1
-
-
-
-
Reserved
-
-
-
-
1
-
-
-
Reserved
-
-
-
-
-
0
0
0
SDIN-L to Channel 2
-
-
-
-
-
0
0
1
SDIN-R to Channel 2
-
-
-
-
-
0
1
0
Reserved
-
-
-
-
-
0
1
1
Reserved
-
-
-
-
-
1
0
0
Reserved
-
-
-
-
-
1
0
1
Reserved
-
-
-
-
-
1
1
0
Ground (0) to channel 2
-
-
-
-
-
1
1
1
Reserved
D15
D14
D13
D12
D11
D10
D9
D8
0
1
1
1
0
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
0
FUNCTION
Reserved
FUNCTION
Reserved
Note: Default values are in bold.
CHANNEL 4 SOURCE SELECT REGISTER (0x21)
This register selects the channel 4 source.
Table 14. Subchannel Control Register (0x21)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
1
0
0
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
1
1
FUNCTION
Reserved
FUNCTION
Reserved
FUNCTION
Reserved
FUNCTION
Reserved
Note: Default values are in bold.
Pwm Output Mux Register (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to
any external output pin.
Bits D21-D20: Selects which PWM channel is output to OUT_A
Bits D17-D16: Selects which PWM channel is output to OUT_B
Bits D13-D12: Selects which PWM channel is output to OUT_C
Bits D09-D08: Selects which PWM channel is output to OUT_D
Note that channels are enclosed so that channel 1=0x00, channel 2=0x01, channel 1=0x02, and channel 2=0x03.
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APA3169
Function Description (Cont.)
Table 15. PWM Output Mux Register (0x25)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
0
0
-
-
-
-
-
-
Reserved
-
-
0
0
-
-
-
-
Multiplex channel 1 to OUT_A
-
-
0
1
-
-
-
-
Multiplex channel 2 to OUT_A
-
-
1
0
-
-
-
-
Multiplex channel 1 to OUT_A
-
-
1
1
-
-
-
-
Multiplex channel 2 to OUT_A
-
-
-
-
0
0
-
-
Reserved
-
-
-
-
-
-
0
0
Multiplex channel 1 to OUT_B
-
-
-
-
-
-
0
1
Multiplex channel 2 to OUT_B
-
-
-
-
-
-
1
0
Multiplex channel 1 to OUT_B
-
-
-
-
-
-
1
1
Multiplex channel 2 to OUT_B
D15
D14
D13
D12
D11
D10
D9
D8
0
0
-
-
-
-
-
-
Reserved
-
-
0
0
-
-
-
-
Multiplex channel 1 to OUT_C
-
-
0
1
-
-
-
-
Multiplex channel 2 to OUT_C
-
-
1
0
-
-
-
-
Multiplex channel 1 to OUT_C
-
-
1
1
-
-
-
-
Multiplex channel 2 to OUT_C
-
-
-
-
0
0
-
-
Reserved
-
-
-
-
-
-
0
0
Multiplex channel 1 to OUT_D
-
-
-
-
-
-
0
1
Multiplex channel 2 to OUT_D
-
-
-
-
-
-
1
0
Multiplex channel 1 to OUT_D
-
-
-
-
-
-
1
1
Multiplex channel 2 to OUT_D
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
1
Reserved
FUNCTION
FUNCTION
FUNCTION
Reserved
Note: Default values are in bold.
DRC Control (0x46)
Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.
Table 16. DRC Control Register
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
FUNCTION
Reserved
FUNCTION
Reserved
FUNCTION
Reserved
45
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APA3169
Function Description (Cont.)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FUNCTION
0
-
-
Reserved
-
0
-
DRC2 turned OFF
-
-
1
-
DRC2 turned ON
-
-
-
-
0
DRC1 turned OFF
-
-
-
-
1
DRC1 turned ON
Note: Default values are in bold.
EQ Control (0x50)
Table 1. EQ Control Register
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
-
-
-
-
-
-
-
FUNCTION
Reserved
FUNCTION
Reserved
FUNCTION
Reserved
FUNCTION
EQ ON
1
-
-
-
-
-
-
-
EQ OFF
-
0
0
0
0
0
0
0
Reserved
Note: Default values are in bold.
Copyright  ANPEC Electronics Corp.
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APA3169
Application Information
Land Pattern Recommendation
5.5mm
Via diameter
=0.3mm X16
1.7mm
0.28mm
5.0mm
0.5mm
Exposed for
thermal PAD
connected
Ground plane
for
ThermalPAD
TQFP7X7-48 Land Pattern Recommendation
Copyright  ANPEC Electronics Corp.
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APA3169
Application Information (Cont.)
Layout Recommendation
AVDD
Power stage block, please use
high voltage -bearing component .
10kO
470O
0.047µ F
4700 pF
0.047µ F
470O
2200 pF
1µ F
4700 pF
0.1µ F
0.1µF
/PDN
LRCK
SCLK
SDIN
SDA
SCL
0.1µF
22µ H
0.68µ F
220µF
AVDD
A_SEL
10kO MCLK
18.2kO TP1
TP2
10kO VR_DIG
/PDN_N
LRCLK
SCLK
SDIN
SDA
SCL
13
14
15
16
17
18
19
20
21
22
23
24
0.68µ F
48
47
46
45
44
43
42
41
40
39
38
37
APA3169
PGND_AB
PGND_AB
OUT_B
PVDD_B
PVDD_B
BS_B
BS_C
PVDD_C
PVDD_C
OUT_C
PGND_CD
PGND_CD
22µ H
0. 033µF
0. 033µF
0.1µF
PVDD
0.1µF
22µ H
0.68µ F
/RESET_N
TP3
DVDD
DVSS
DGND
AGND
VREG
VCLCD
BS_D
PVDD_D
PVDD_D
OUT_D
25
26
27
28
29
30
31
32
33
34
35
36
4. 7µ F
AV DD
PVDD
12
11
10
9
8
7
6
5
4
3
2
1
0O
A_SEL
MCLK
0.033 µF
VR_ANA
PLL_FLTP
PLL_FLTM
AVSS
PBTL
TM2
TM1 22.1kO
VCLA B
BS_A
PVDD_A
PVDD_A
OUT_A
AVDD
10µ F
Output & VDD traces width
=40mil, should be as short as
they can, and symmetric.
JP1
/RESET
DVDD
10µF
AVDD cap. & DVDD cap.
should be close to the chip .
0.68µ F
0.1µF
220 µF
22µ H
0.1µF
1µ F
0.1µ F
Thermal pad should be soldered
on ground plane of the PCB .
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
PVDD
48
0.033µ F
PVDD cap. and bootstrap cap .
should be close to the chip .
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APA3169
Package Information
TQFP7x7-48P
D
0.25
E
E2
EXPOSED
PAD
E1
c
A1
D2
A
A2
D1
L
b
S
Y
M
B
O
L
0
GAUGE PLANE
SEATING PLANE
e
TQFP7x7-48P
MILLIMETERS
MIN.
INCHES
MIN.
MAX.
A
MAX.
0.047
1.20
A1
0.05
0.15
0.002
0.006
A2
0.95
1.05
0.037
0.041
b
0.17
0.27
0.007
0.011
c
0.09
0.20
0.004
0.008
D
8.80
9.20
0.346
0.362
0.280
D1
6.90
7.10
0.272
D2
3.00
5.50
0.118
0.177
E
8.80
9.20
0.346
0.362
E1
6.90
7.10
0.272
0.280
E2
3.00
5.50
0.118
0.177
0.75
0.018
e
L
0.50 BSC
0.45
0
o
0.020 BSC
o
o
7
0
0.030
7o
Note : 1. Followed from JEDEC MS-026 ABC.
2. Dimension "D1" and "E1" do not include mold protrusions.
Allowable protrusions is 0.25 mm per side. "D1" and "E1" are
maximun plasticbody size dimensions including mold mismatch.
Copyright  ANPEC Electronics Corp.
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APA3169
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFP7x7-48P
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.5±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
9.4±0.20
9.4±0.20
1.8±0.20
4.0±0.10
12.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFP7x7-48P
Tape & Reel
2500
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APA3169
Taping Direction Information
TQFP7x7-48P
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
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APA3169
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak
(Tp)*
package
body
Temperature
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. A.4 - Jan., 2013
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
52
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APA3169
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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