CY7C1481V33 CY7C1483V33 CY7C1487V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Functional Description[1] Features • • • • • Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 3.3V core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times — 6.5 ns (133 MHz version) • Provide high-performance 2-1-1-1 access rate • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self timed write • Asynchronous output enable • CY7C1481V33, CY7C1483V33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1487V33 available in Pb-free and non-Pb-free 209 ball FBGA package • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode option The CY7C1481V33/CY7C1483V33/CY7C1487V33 is a 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481V33/CY7C1483V33/CY7C1487V33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1481V33/CY7C1483V33/CY7C1487V33 operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. Selection Guide 133 MHz 100 MHz Unit Maximum Access Time 6.5 8.5 ns Maximum Operating Current 335 305 mA Maximum CMOS Standby Current 150 150 mA Note 1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05284 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 01, 2007 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Logic Block Diagram – CY7C1481V33 (2M x 36) ADDRESS REGISTER A 0, A1, A A [1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQ D , DQP D DQ D , DQP D BW D BYTE BYTE WRITE REGISTER WRITE REGISTER DQ C, DQP C DQ C, DQP C BW C BYTE BYTE WRITE REGISTER WRITE REGISTER DQ B , DQP B BW B DQ B , DQP B BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQ s DQP A DQP B DQP C DQP D WRITE REGISTER DQ A , DQP A BW A BWE DQ A , DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE ZZ SLEEP CONTROL Logic Block Diagram – CY7C1483V33 (4M x 18) A0,A1,A ADDRESS REGISTER A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BW B DQ B ,DQP B WRITE REGISTER BW A DQ A ,DQP A WRITE REGISTER DQ B ,DQP B WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQP A DQP B DQ A ,DQP A WRITE DRIVER BWE GW CE 1 CE 2 CE 3 ENABLE REGISTER INPUT REGISTERS OE ZZ SLEEP CONTROL Document #: 38-05284 Rev. *H Page 2 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Logic Block Diagram – CY7C1487V33 (1M x 72) ADDRESS REGISTER A0, A1,A A[1:0] MODE Q1 BINARY COUNTER CLR Q0 ADV CLK ADSC ADSP BW H DQ H , DQPH WRITE DRIVER DQ H , DQPH WRITE DRIVER BW G DQ F, DQPF WRITE DRIVER DQ G , DQPG WRITE DRIVER BW F DQ F, DQPF WRITE DRIVER DQ F, DQPF WRITE DRIVER BW E DQ E , DQPE WRITE DRIVER DQ E , DQP BYTE “a” E WRITE DRIVER BW D DQ D, DQPD WRITE DRIVER DQ D, DQPD WRITE DRIVER BW C DQ C, DQPC WRITE DRIVER DQ C, DQPC WRITE DRIVER MEMORY ARRAY SENSE AMPS BW B BW A BWE GW CE1 CE2 CE3 OE ZZ DQ B , DQPB WRITE DRIVER DQ B , DQPB WRITE DRIVER OUTPUT BUFFERS E DQ A , DQPA WRITE DRIVER DQ A , DQPA WRITE DRIVER ENABLE REGISTER OUTPUT REGISTERS PIPELINED ENABLE INPUT REGISTERS DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H SLEEP CONTROL Document #: 38-05284 Rev. *H Page 3 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Pin Configurations NC NC NC CY7C1483V33 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05284 Rev. *H A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 A A VSS VDD DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1481V33 (2Mx 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 A A VSS VDD A A A A A A A A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP Pinout Page 4 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1481V33 (2M x 36) 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/288M 1 A CE1 BWC BWB CE3 BWE ADSC ADV A NC NC/144M A CE2 BWD BWA CLK GW OE ADSP A NC/576M DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC/1G DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDD VDD VDD VDD VDDQ VDDQ NC VDDQ DQB VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VSS VSS VSS VSS VSS DQC NC DQD VDDQ VDDQ NC VDDQ DQB NC DQA DQB DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC A A A TDI A1 TDO A A A A R MODE A A A TMS A0 TCK A A A A 9 10 11 CY7C1483V33 (4M x 18) 1 2 3 4 5 6 7 8 A B C D E F G H J K L M N P NC/288M A CE1 BWB NC/144M A CE2 NC NC CE3 BWE ADSC ADV A BWA CLK GW OE ADSP A NC NC NC DQB VDDQ VSS VDD VSS VDDQ VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC/1G NC DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB NC NC DQB DQB NC NC VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC R A NC/576M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC A A A TDI A1 TDO A A A A MODE A A A TMS A0 TCK A A A A Document #: 38-05284 Rev. *H Page 5 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1487V33 (1M × 72) 1 2 3 A DQG DQG B DQG DQG BWSC BWSG NC/288M C DQG DQG BWSH BWSD NC/144M CE1 D DQG DQG VSS NC NC/1G OE E DQPG DQPC VDDQ VDDQ VDD VDD F DQC DQC VSS VSS VSS G DQC VDDQ VDDQ H DQC DQC J DQC K A 4 CE2 5 6 ADSP ADSC 7 ADV 8 9 10 11 CE3 A DQB DQB A BWSB BWSF DQB DQB NC/576M BWSE BWSA DQB DQB NC VSS DQB DQB VDD VDDQ VDDQ DQPF DQPB NC VSS VSS VSS DQF DQF VDD NC VDD VDDQ VDDQ DQF DQF VSS VSS VSS NC VSS VSS VSS DQF DQF DQC VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQF DQF NC NC CLK NC VSS VSS VSS NC NC NC NC L DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA M DQH DQH VSS VSS VSS NC VSS VSS VSS DQA DQA N DQH DQH VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQA DQA P DQH DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA R DQPD DQPH VDDQ VDDQ VDD VDD VDD VDDQ VDDQ T DQD DQD VSS NC NC MODE NC NC VSS DQE DQE U DQD DQD A A A A A A A DQE DQE V DQD DQD A A A A1 A A A DQE DQE W DQD DQD TMS TDI A A0 A TCK DQE DQE DQC Document #: 38-05284 Rev. *H BW GW TDO DQPA DQPE Page 6 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Pin Definitions Pin Name IO Description A0, A1, A InputSynchronous Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. BWA,BWB,BWC,BWD, BWE,BWF,BWG,BWH InputSynchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. GW InputSynchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). CLK InputClock Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW during a burst operation. CE1 InputSynchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. CE2 InputSynchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. CE3 InputSynchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. OE InputAsynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV InputSynchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. ADSP InputSynchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH ADSC InputSynchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. BWE InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. ZZ InputAsynchronous ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs IOSynchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX IOSynchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQPx is controlled by BWX correspondingly. MODE Input-Static Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating, selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode Pin has an internal pull up. Document #: 38-05284 Rev. *H Page 7 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Pin Definitions (continued) Pin Name VDD IO Power Supply VDDQ Ground [2} TDO Power supply inputs to the core of the device. IO Power Supply Power supply for the IO circuitry. VSS VSSQ Description I/O Ground JTAG Serial Output Synchronous Ground for the core of the device. Ground for the IO circuitry. Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin should be left unconnected. This pin is not available on TQFP packages. TDI JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS JTAG Serial Input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG Synchronous feature is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG Clock Clock Input to the JTAG Circuit. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1481V33/CY7C1483V33/CY7C1487V33 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data is available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see “Truth Table for Read/Write” on page 11 for appropriate states that indicate a write) on the next clock rise, the appropriate data is latched and written into the device. Byte writes are supported. All IOs are tri-stated during a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated before the presentation of data to DQs. As a safety precaution, the data lines are tri-stated after a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQs will be written into the specified address location. Byte writes are supported. Note 2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry. Document #: 38-05284 Rev. *H Page 8 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 All IOs are tri-stated when a write is detected, even a byte write. Because this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated before the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE selects a linear burst sequence. A HIGH on MODE selects an interleaved burst order. Leaving MODE unconnected causes the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Fourth Address A1: A0 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 150 mA tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled Document #: 38-05284 Rev. *H 2tCYC ns 2tCYC 0 ns ns Page 9 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Truth Table The truth table for CY7C1481V33, CY7C1483V33, and CY7C1487V33 follows.[3, 4, 5, 6, 7] Cycle Description ADDRESS CE CE CE ZZ 1 2 3 Used ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle, Power Down None H X X L X L X X X L-H Tri-State Deselected Cycle, Power Down None L L X L L X X X X L-H Tri-State Deselected Cycle, Power Down None L X H L L X X X X L-H Tri-State Deselected Cycle, Power Down None L L X L H L X X X L-H Tri-State Deselected Cycle, Power Down None X X X L H L X X X L-H Tri-State Sleep Mode, Power Down None X X X H X X X X X X Tri-State Read Cycle, Begin Burst External L H L L L X X X L L-H Q Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes 3. X = Do Not Care, H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a do not care for the remainder of the write cycle. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW). Document #: 38-05284 Rev. *H Page 10 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Truth Table for Read/Write The read-write truth table for CY7C1481V33 follows.[3, 8] Function GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A (DQA, DQPA) H L H H H L Write Byte B(DQB, DQPB) H L H H L H Write Bytes A, B (DQA, DQB, DQPA, DQPB) H L H H L L Write Byte C (DQC, DQPC) H L H L H H Write Bytes C, A (DQC, DQA, DQPC, DQPA) H L H L H L Write Bytes C, B (DQC, DQB, DQPC, DQPB) H L H L L H Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB, DQPA) H L H L L L Write Byte D (DQD, DQPD) H L L H H H Write Bytes D, A (DQD, DQA, DQPD, DQPA) H L L H H L Write Bytes D, B (DQD, DQA, DQPD, DQPA) H L L H L H Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L H L L Write Bytes D, B (DQD, DQB, DQPD, DQPB) H L L L H H Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC, DQPA) H L L L H L Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB, DQPA) H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Truth Table for Read/Write The read-write truth table for CY7C1483V33 follows.[3, 8] Function GW BWE Read H H X X Read H L H H Write Byte A - (DQA and DQPA) H L H L Write Byte B - (DQB and DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X GW BWE BWx[9] Read H H X Read H L All BW = H Write Byte x – (DQx and DQPx) H L L Write All Bytes H L All BW = L Write All Bytes L X X BWB BWA Truth Table for Read/Write The read-write truth table for CY7C1487V33 follows.[3, 8] Function Notes 8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. An appropriate write is performed based on which byte write is active. 9. BWx represents any byte write signal BWX.To enable any byte write BWx , a Logic LOW signal must be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write. Document #: 38-05284 Rev. *H Page 11 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1481V33/CY7C1483V33/CY7C1487V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V IO logic levels. The CY7C1481V33/CY7C1483V33/CY7C1487V33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball serially clocks data-out from the registers. Whether the output is active depends on the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) TAP Controller Block Diagram 0 Bypass Register TAP Controller State Diagram 1 2 1 0 TEST-LOGIC RESET TDI Selection Circuitry RUN-TEST/ IDLE Selection Circuitry TDO 31 30 29 . . . 2 1 0 0 0 Instruction Register 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 x . . . . . 2 1 0 CAPTURE-IR Boundary Scan Register 0 SHIFT-DR 0 SHIFT-IR 1 0 1 EXIT1-DR 1 TCK EXIT1-IR 0 1 TM S TAP CONTROLLER 0 PAUSE-DR 0 PAUSE-IR 1 0 Performing a TAP Reset 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 Identification Register 0 1 CAPTURE-DR 0 0 1 0 UPDATE-IR 1 0 To perform a RESET, force TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this Document #: 38-05284 Rev. *H Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in the “TAP Controller Block Diagram” on page 12. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the Page 12 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to enable fault isolation of the board level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register, and the x18 configuration has a 54-bit-long register. The boundary scan register is loaded with the contents of the RAM I/ ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page 15. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state, when the instruction register is placed between TDI and TDO. During this state, instructions are shifted Document #: 38-05284 Rev. *H through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction, which is to be executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction is loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Page 13 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[10,11] Parameter Description Min Max Unit 20 MHz Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 0 ns ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 Hold Times tTMSH TMS hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 n.s. Document #: 38-05284 Rev. *H Page 14 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.135V to 3.6V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Conditions Output LOW Voltage Unit IOH = –4.0 mA VDDQ = 3.3V 2.4 V VDDQ = 2.5V 2.0 V VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V IOL = 100 µA Input HIGH Voltage Input LOW Voltage Input Load Current Max IOH = –1.0 mA IOH = –100 µA Output LOW Voltage Min VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND < VIN < VDDQ Identification Register Definitions Bit# 24 is “1” in the ID Register definitions for both 2.5V and 3.3V versions of the device. Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1481V33 (2M x 36) CY7C1483V33 (4M x18) CY7C1487V33 (1M x72) 000 000 000 01011 01011 01011 000001 000001 000001 Description Describes the version number Reserved for internal use Defines memory type and architecture 100100 010100 110100 00000110100 00000110100 00000110100 Enables unique identification of SRAM vendor Defines width and density 1 1 1 Indicates the presence of an ID register Note 12. All voltages refer to VSS (GND). Document #: 38-05284 Rev. *H Page 15 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Scan Register Sizes Register Name Bit Size (X36) Bit Size (X18) Bit Size (X72) 3 3 3 Instruction Bypass 1 1 1 ID 32 32 32 Boundary Scan Order -165FBGA 73 54 - Boundary Scan Order -209 BGA - - 112 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 41 L10 61 B8 2 D1 22 P2 42 K11 62 A7 3 E1 23 R4 43 J11 63 B7 4 D2 24 P6 44 K10 64 B6 5 E2 25 R6 45 J10 65 A6 6 F1 26 N6 46 H11 66 B5 7 G1 27 P11 47 G11 67 A5 8 F2 28 R8 48 F11 68 A4 9 G2 29 P3 49 E11 69 B4 10 J1 30 P4 50 D10 70 B3 11 K1 31 P8 51 D11 71 A3 12 L1 32 P9 52 C11 72 A2 13 J2 33 P10 53 G10 73 B2 14 M1 34 R9 54 F10 15 N1 35 R10 55 E10 16 K2 36 R11 56 A10 17 L2 37 N11 57 B10 18 M2 38 M11 58 A9 19 R1 39 L11 59 B9 20 R2 40 M10 60 A8 Document #: 38-05284 Rev. *H Page 16 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 D2 19 R8 37 C11 2 E2 20 P3 38 A11 3 F2 21 P4 39 A10 4 G2 22 P8 40 B10 5 J1 23 P9 41 A9 6 K1 24 P10 42 B9 7 L1 25 R9 43 A8 8 M1 26 R10 44 B8 9 N1 27 R11 45 A7 10 R1 28 M10 46 B7 11 R2 29 L10 47 B6 12 R3 30 K10 48 A6 13 P2 31 J10 49 B5 14 R4 32 H11 50 A4 15 P6 33 G11 51 B3 16 R6 34 F11 52 A3 17 N6 35 E11 53 A2 18 P11 36 D11 54 B2 Document #: 38-05284 Rev. *H Page 17 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 V10 85 C11 2 A2 30 T2 58 U11 86 C10 3 B1 31 U1 59 U10 87 B11 4 B2 32 U2 60 T11 88 B10 5 C1 33 V1 61 T10 89 A11 6 C2 34 V2 62 R11 90 A10 7 D1 35 W1 63 R10 91 A9 8 D2 36 W2 64 P11 92 U8 9 E1 37 T6 65 P10 93 A7 10 E2 38 V3 66 N11 94 A5 11 F1 39 V4 67 N10 95 A6 12 F2 40 U4 68 M11 96 D6 13 G1 41 W5 69 M10 97 B6 14 G2 42 V6 70 L11 98 D7 15 H1 43 W6 71 L10 99 K3 16 H2 44 U3 72 P6 100 A8 17 J1 45 U9 73 J11 101 B4 18 J2 46 V5 74 J10 102 B3 19 L1 47 U5 75 H11 103 C3 20 L2 48 U6 76 H10 104 C4 21 M1 49 W7 77 G11 105 C8 22 M2 50 V7 78 G10 106 C9 23 N1 51 U7 79 F11 107 B9 24 N2 52 V8 80 F10 108 B8 25 P1 53 V9 81 E10 109 A4 26 P2 54 W11 82 E11 110 C6 27 R2 55 W10 83 D11 111 B7 28 R1 56 V11 84 D10 112 A3 Document #: 38-05284 Rev. *H Page 18 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.3V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA Operating Range Ambient VDD VDDQ Temperature Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Range Electrical Characteristics Over the Operating Range[13, 14] Parameter Description VDD Power Supply Voltage VDDQ IO Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage[13] VIL Input LOW Voltage[13] Test Conditions Min Max Unit 3.135 3.6 V For 3.3V I/O 3.135 VDD V For 2.5V I/O 2.375 2.625 V For 3.3V I/O, IOH = –4.0 mA 2.4 V For 2.5V I/O, IOH = –1.0 mA 2.0 V For 3.3V I/O, IOL = 8.0 mA For 2.5V I/O, IOL = 1.0 mA IX Input Leakage Current Except ZZ and MODE V 0.4 V 2.0 VDD + 0.3V V For 2.5V I/O 1.7 VDD + 0.3V V For 3.3V I/O –0.3 0.8 V For 2.5V I/O –0.3 0.7 V –5 5 µA For 3.3V I/O GND ≤ VI ≤ VDDQ Input Current of MODE Input = VSS µA –30 Input = VDD Input Current of ZZ 0.4 5 µA –5 Input = VSS Input = VDD µA 30 µA 5 µA IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IDD VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 335 mA 10-ns cycle, 100 MHz 305 mA Automatic CE Power Down Current—TTL Inputs Max VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 200 mA 10-ns cycle, 100 MHz 200 mA ISB1 –5 ISB2 Automatic CE Max VDD, Device Deselected, All speeds Power Down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—CMOS Inputs f = 0, inputs static 150 mA ISB3 Max VDD, Device Deselected, 7.5-ns cycle, 133 MHz Automatic CE Power Down VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 10-ns cycle, 100 MHz Current—CMOS Inputs f = fMAX, inputs switching 200 mA 200 mA 165 mA ISB4 Automatic CE Power Down Current—TTL Inputs Max VDD, Device Deselected, All Speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Notes 13. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2). 14. TPower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05284 Rev. *H Page 19 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description CADDRESS Address Input Capacitance CDATA Data Input Capacitance Test Conditions 100 TQFP Max 165 FBGA Max 209 FBGA Max TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 6 6 6 pF 5 5 5 pF Unit CCTRL Control Input Capacitance 8 8 8 pF CCLK Clock Input Capacitance 6 6 6 pF CI/O Input/Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit ΘJA Thermal Resistance (Junction to Ambient) 24.63 16.3 15.2 °C/W ΘJC Thermal Resistance (Junction to Case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 2.28 2.1 1.7 °C/W AC Test Loads and Waveforms 3.3V IO Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω VL = 1.5V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) (b) 2.5V IO Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 1538Ω VL = 1.25V (a) Document #: 38-05284 Rev. *H ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) Page 20 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Switching Characteristics Over the Operating Range.[15, 16] Parameter tPOWER Description VDD(Typical) to the First Access[17] 133 MHz Min Max 100 MHz Min Max Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.0 ns Output Times tCDV Data Output Valid After CLK Rise 6.5 tDOH Data Output Hold After CLK Rise 2.5 Low-Z[18, 19, 20] 3.0 8.5 2.5 ns ns tCLZ Clock to tCHZ Clock to High-Z[18, 19, 20] 3.8 4.5 ns tOEV OE LOW to Output Valid 3.0 3.8 ns tOELZ tOEHZ OE LOW to Output Low-Z[18, 19, 20] OE HIGH to Output High-Z[18, 19, 20] 3.0 0 ns 0 3.0 ns 4.0 ns Setup Times tAS Address Setup Before CLK Rise 1.5 1.5 ns tADS ADSP, ADSC Setup Before CLK Rise 1.5 1.5 ns tADVS ADV Setup Before CLK Rise 1.5 1.5 ns tWES GW, BWE, BWX Setup Before CLK Rise 1.5 1.5 ns tDS Data Input Setup Before CLK Rise 1.5 1.5 ns tCES Chip Enable Setup 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns tWEH GW, BWE, BWX Hold After CLK Rise 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns Hold Times Notes 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted. 17. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 18. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV from steady-state voltage. 19. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. Document #: 38-05284 Rev. *H Page 21 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Timing Diagrams Figure 1. Read Cycle Timing[21] tCYC CLK t t ADS t CL CH tADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t WES t WEH GW, BWE, BWX t CES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CDV t OELZ t CHZ t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document #: 38-05284 Rev. *H Page 22 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Timing Diagrams (continued) Figure 2. Write Cycle Timing[21, 22] t CYC CLK t t ADS CH t CL tADH ADSP t ADS ADSC extends burst tADH t ADS tADH ADSC t AS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst t WES tWEH BWE, BW X t WES t WEH GW t CES tCEH CE t ADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t DS t DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) OEHZ Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW. Document #: 38-05284 Rev. *H Page 23 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Timing Diagrams (continued) Figure 3. Read/Write Cycle Timing[21, 23, 24] tCYC CLK t t ADS CH t CL tADH ADSP ADSC t AS ADDRESS A1 tAH A2 A3 A4 t WES t A5 A6 WEH BWE, BW X t CES tCEH CE ADV OE t DS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH t OELZ D(A3) D(A5) Q(A4) Q(A2) Back-to-Back READs D(A6) t CDV Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 23. The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH. Document #: 38-05284 Rev. *H Page 24 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Timing Diagrams (continued) Figure 4. ZZ Mode Timing[25, 26] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 25. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device. 26. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05284 Rev. *H Page 25 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1481V33-133AXC Package Diagram Operating Range Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial CY7C1483V33-133AXC CY7C1481V33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1483V33-133BZC CY7C1481V33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1483V33-133BZXC CY7C1487V33-133BGC CY7C1487V33-133BGXC CY7C1481V33-133AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial CY7C1483V33-133AXI CY7C1481V33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1483V33-133BZI CY7C1481V33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1483V33-133BZXI CY7C1487V33-133BGI CY7C1487V33-133BGXI 100 CY7C1481V33-100AXC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free Commercial CY7C1483V33-100AXC CY7C1481V33-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1483V33-100BZC CY7C1481V33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1483V33-100BZXC CY7C1487V33-100BGC CY7C1487V33-100BGXC CY7C1481V33-100AXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-free lndustrial CY7C1483V33-100AXI CY7C1481V33-100BZI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1483V33-100BZI CY7C1481V33-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-free CY7C1483V33-100BZXI CY7C1487V33-100BGI CY7C1487V33-100BGXI Document #: 38-05284 Rev. *H 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-free Page 26 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Package Diagrams Figure 5. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05284 Rev. *H A 51-85050-*B Page 27 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Package Diagrams (continued) Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE Document #: 38-05284 Rev. *H 1.40 MAX. 0.36 C 51-85165-*A Page 28 of 30 [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Package Diagrams (continued) Figure 7. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 51-85167-** i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05284 Rev. *H Page 29 of 30 © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1481V33 CY7C1483V33 CY7C1487V33 Document History Page Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Document Number: 38-05284 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114671 08/12/02 PKS New Data Sheet *A 118283 01/27/03 HGK Updated Ordering Information Updated the features for package offering Changed from Advance Information to Preliminary *B 233368 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 150-MHz speed grade offering Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering *C 299452 See ECN SYT Removed 117-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 21 Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Lead-free BG packages availability’ below the Ordering Information *D 323080 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified VOL, VOH test conditions Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table *E 416193 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Changed the IX current values of MODE on page # 19 from -5 µA and 30 µA to -30 µA and 5 µA Changed the IX current values of ZZ on page # 19 from -30 µA and 5 µA to -5 µA and 30 µA Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering Information table *F 470723 See ECN VKN Converted from Preliminary to Final Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table *G 486690 See ECN VKN Corrected the typo in the 209-Ball FBGA pinout. (Corrected the ball name H9 to VSS from VSSQ). *H 1062041 See ECN Document #: 38-05284 Rev. *H VKN/KKVTMP Added footnote #2 related to VSSQ Page 30 of 30 [+] Feedback