Evaluation Board for G = 1, 2, 5, 10; 10 MHz, 20 V/μs Programmable Gain In-Amp AD8250-EVALZ FEATURES GENERAL DESCRIPTION Quick evaluation On-board gain control switches SMA connectors for high speed gain testing The AD8250-EVALZ is designed to enable quick evaluation of the AD8250 programmable gain instrumentation amplifier (PGIA). The evaluation board includes on-board gain setting switches to quickly demonstrate the AD8250’s software gain programmability. In addition, an external logic generator can be connected to the AD8250-EVALZ SMA ports to test the PGIA’s gain control. +VS HI R6 2kΩ W2 TP3 DGND SW1 R7 2kΩ A0 JP3 C10 TP4 W1 TP5 W3 R8 0Ω HI TP7 U2 1 5 2 ADR392 SW2 3 A1 4 HI C9 0.1µF –VS WR TP6 DGND 2 C6 R1 6 VOUT 5 10 IN+ 4 TP1 R2 C5 1 IN– R3 7 U1 AD8250 OUT 9 C7 R4 3 GND2 C3 0.1µF C8 +VS 8 GND1 R5 JP1 C4 0.1µF +VS –VS –VS + VREF C1 10µF + C2 10µF 06701-001 TP2 Figure 1. Schematic Rev. 0 Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Analog Devices reserves the right to change devices or specifications at any time without notice. Trademarks and registered trademarks are the property of their respective owners. Evaluation boards are not authorized to be used in life support devices or systems. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD8250-EVALZ EVALUATION BOARD HARDWARE QUICK START GUIDE GAIN SELECTION (FROM AD8250 DATA SHEET) By default, the AD8250-EVALZ is configured for gain change using the on-board switches, SW1 and SW2, as shown in Table 1. This section shows users how to configure the AD8250 for basic operation. Logic low and logic high voltage limits are listed in the Specifications section of the AD8250 data sheet. Typically, logic low is 0 V and logic high is 5 V; both voltages are measured with respect to DGND. Refer to the specifications table of the AD8250 for the permissible voltage range of DGND. The gain of the AD8250 can be set using two methods. Table 1. Gain Setting Using the On-Board Switches SW2 Low Low High High SW1 Low High Low High Gain 1 2 5 10 Transparent Gain Mode Table 2. Default Settings (From the Factory) Name W1, W2, W3 JP1, JP3, R1, R2, R3, R5 Default Status In place (tied) Shorted by design (on trace) USING EXTERNAL LOGIC TO CHANGE GAIN The AD8250-EVALZ accepts external logic signals such as those from logic generators or FPGAs. To change gains using external logic signals, Jumpers W1, W2, and W3 must be removed. Only then will the A0, A1, and WR pins on the AD8250 be directly tied to TP3, TP4, and TP5 (and to the respective SMA connectors). External logic can be tied via the test points TP3, TP4 and TP5, or via the respective SMA connector. The easiest way to set the gain is to program it directly via a logic high or logic low voltage applied to A0 and A1. Figure 2 shows an example of this gain setting method, referred to throughout the data sheet as transparent gain mode. Tie WR to the negative supply to engage transparent gain mode. (On the AD8250-EVALZ board, put the W3 jumper in place.) In this mode, any change in voltage applied to A0 and A1 from logic low to logic high, or vice versa, immediately results in a gain change. Table 3 is the truth table for transparent gain mode and Figure 2 shows the AD8250 configured in transparent gain mode. +15V 10μF 0.1µF WR A1 A0 +IN –15V +5V +5V G = 10 AD8250 REF TERMINATION –IN The AD8250-EVALZ has 50 Ω traces leading to the A0, A1, and WR pins. However, it does not have terminations to those pins. If terminations are added, remove Jumper W1, Jumper W2, and Jumper W3. DGND 10μF –15V NOTE: 1. IN TRANSPARENT GAIN MODE, WR IS TIED TO −VS. THE VOLTAGE LEVELS ON A0 AND A1 DETERMINE THE GAIN. IN THIS EXAMPLE, BOTH A0 AND A1 ARE SET TO LOGIC HIGH, RESULTING IN A GAIN OF 10. RFI FILTER An RFI filter pattern is included at the input traces of the AD8250-EVALZ. R1 and R2 are shorted. The shorted traces must be cut before R1 and R2 are placed on the board. DGND 0.1µF 06701-002 W3 (Jumper) In place In place In place In place Figure 2. Transparent Gain Mode, A0 and A1 = High, G = 10 Table 3. Truth Table Logic Levels for Transparent Gain Mode OUTPUT FILTER An output filter pattern is included at the output trace of the AD8250-EVALZ. To use R3 or R5 in a filter, cut the shorted traces prior to placing resistors in those locations. REFERENCE WR (W3) A1 (SW2) A0 (SW1) Gain −VS (in place) −VS (in place) −VS (in place) −VS (in place) Low Low High High Low High Low High 1 2 5 10 To level shift the output, a nonzero reference voltage can be applied to REF. By default, REF is tied to analog GND. Cutting the trace at JP1 opens the connection between REF and analog GND. ANALOG AND DIGITAL GROUND Analog and digital grounds are tied at JP3. To sever the connection between them, JP3 can be cut with a knife to open the connection between the two grounds. Rev. 0 | Page 2 of 4 AD8250-EVALZ Latched Gain Mode Timing for Latched Gain Mode Some applications have multiple programmable devices such as multiplexers or other programmable gain instrumentation amplifiers on the same PCB. In such cases, devices can share a data bus. The gain of the AD8250 can be set using WR as a latch, allowing other devices to share A0 and A1. Figure 3 shows a schematic using this method, known as latched gain mode. (On the AD8250-EVALZ, remove the W1, W2, and W3 jumpers, and drive A0, A1, and WR with external logic to test this gain setting mode.) The AD8250 is in this mode when WR is held at logic high or logic low, typically 5 V and 0 V, respectively. The voltages on A0 and A1 are read on the downward edge of the WR signal as it transitions from logic high to logic low. This latches in the logic levels on A0 and A1, resulting in a gain change. See the truth table listing in Table 4 for more information on these gain changes. In latched gain mode, logic levels at A0 and A1 have to be held for a minimum setup time, tSU, before the downward edge of WR latches in the gain. Similarly, they must be held for a minimum hold time of tHD after the downward edge of WR to ensure that the gain is latched in correctly. After tHD, A0 and A1 may change logic levels but the gain does not change (until the next downward edge of WR). The minimum duration that WR can be held high is t WR-HIGH, and t WR-LOW is the minimum duration that WR can be held low. Digital timing specifications are listed in the Specification section of the AD8250 data sheet. The time required for a gain change is dominated by the settling time of the amplifier. A timing diagram is shown in Figure 4. +15V WR 10μF 0.1µF A1 A0 +IN +5V 0V +5V 0V WR A1 + A0 G = PREVIOUS STATE When sharing a data bus with other devices, logic levels applied to those devices can potentially feed through to the output of the AD8250. Feedthrough can be minimized by decreasing the edge rate of the logic signals. Furthermore, careful layout of the PCB also reduces coupling between the digital and analog portions of the board. +5V 0V G = 10 t WR-HIGH WR AD8250 REF – –IN t W R-LOW tSU tHD 10μF 06701-004 A0, A1 DGND DGND 0.1µF –15V NOTE: 1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0 AND A1 ARE READ AND LATCHED IN, RESULTING IN A GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10. 06701-003 Figure 4. Timing Diagram for Latched Gain Mode Figure 3. Latched Gain Mode, G = 10 Table 4. Truth Table Logic Levels for Latched Gain Mode WR1 A11 A01 Gain High to low High to low High to low High to low Low to low Low to high High to high Low Low High High X2 X2 X2 Low High Low High X2 X2 X2 Change to 1 Change to 2 Change to 5 Change to 10 No change No change No change 1 Jumper W1, Jumper W2, and Jumper W3 must be removed and external logic must be used to test latched gain mode. 2 X = Don’t care. On power-up, the AD8250 defaults to a gain of 1 when in latched gain mode. In contrast, if the AD8250 is configured in transparent gain mode, it starts at the gain indicated by the voltage levels on A0 and A1 upon power-up. Rev. 0 | Page 3 of 4 AD8250-EVALZ ORDERING INFORMATION ORDERING GUIDE Model AD8250-EVALZ1 1 Package Description Evaluation Board ESD CAUTION Z = RoHS Compliant Part. ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. EB06701-0-6/07(0) Rev. 0 | Page 4 of 4