ON NCP1395BDR2G High performance resonant mode controller Datasheet

NCP1395A/B
High Performance Resonant
Mode Controller
The NCP1395A/B offers everything needed to build a reliable and
rugged resonant mode power supply. Its unique architecture includes
a 1.0 MHz Voltage Controller Oscillator whose control mode brings
flexibility when an ORing function is a necessity, e.g. in multiple
feedback paths implementations. Protections featuring various
reaction times, e.g. immediate shutdown or timer−based event,
brown−out, broken optocoupler detection etc., contribute to a safer
converter design, without engendering additional circuitry
complexity. An adjustable deadtime also helps lowering the
shoot−through current contribution as the switching frequency
increases.
Finally, an onboard operational transconductance amplifier allows
for various configurations, including constant output current working
mode or traditional voltage regulation.
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MARKING
DIAGRAMS
16
16
NCP1395xP
AWLYYWWG
1
PDIP−16
P SUFFIX
CASE 648
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Frequency Operation from 50 kHz up to 1.0 MHz
Selectable Minimum Switching Frequency with "3% Accuracy
Adjustable Deadtime from 150 ns to 1.0 ms
Startup Sequence via an Adjustable Soft−Start
Brown−Out Protection for a Simpler PFC Association
Latched Input for Severe Fault Conditions, e.g. Overtemperature
or OVP
Timer−Based Input with Auto−Recovery Operation for Delayed
Event Reaction
Enable Input for Immediate Event Reaction or Simple ON/OFF
Control
Operational Transconductance Amplifier (OTA) for Multiple
Feedback Loops
VCC Operation up to 20 V
Low Startup Current of 300 mA Max
Common Collector Optocoupler Connection
Internal Temperature Shutdown
B Version Features 10 V VCC Startup Threshold for Auxiliary
Supply Usage
Easy No−Load Operation and Low Standby Power Due to
Programmable Skip−Cycle
These are Pb−Free Devices*
16
1395xDR2G
AWLYWW
1
SO−16
D SUFFIX
CASE 751B
x
A
WL
YY, Y
WW
G
= A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Fmin 1
16 NINV
Fmax 2
15 Out
DT 3
14 Slow Fault
Css 4
13 Fast Fault
FB 5
12 Vcc
Ctimer 6
11 B
BO 7
10 A
AGnd 8
9
PGnd
(Top View)
Typical Applications
•
•
•
•
ORDERING INFORMATION
LCD/Plasma TV Converters
High Power Ac−DC Adapters for Notebooks
Industrial and Medical Power Sources
Offline Battery Chargers
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 1
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the ON
Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
1
Publication Order Number:
NCP1395/D
BO
Timer
Soft−start
Deadtime
Fmax
Fmin
2
8
7
9
10
11
12
5
6
13
14
15
16
4
3
2
1
NCP1395
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Figure 1. Typical Application Example
Analog Ground
Power Ground
Slow Fault
4
3
2
1
NCP5181
VCC = 15 V
5
6
7
8
HV
+
Vout
NCP1395A/B
NCP1395A/B
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
Fmin
Timing Resistor
2
Fmax
Frequency Clamp
3
DT
Deadtime
A simple resistor adjusts the deadtime length.
4
Css
Soft−Start
Select the soft−start duration.
5
FB
Feedback
Applying a voltage above 1.3 V on this pin increases the oscillation frequency
up to Fmax.
6
Ctimer
Timer Duration
7
BO
Brown−Out
8
Agnd
Analog Ground
−
9
Pgnd
Power Ground
−
10
A
Low Side Output
Drives the low side power MOSFET.
Drives the upper side power MOSFET.
Connecting a resistor to this pin, sets the minimum oscillator frequency
reached for VFB is below 1.3 V.
A resistor sets the maximum frequency excursion.
Sets the timer duration in presence of a fault.
Detects low input voltage conditions. When brought above Vlatch, it fully
latches off the controller.
11
B
High Side Output
12
Vcc
Supplies the Controller
−
13
Fast Fault
Quick Fault Detection
Fast shutdown pin, stops all pulses when brought high. Please look in the
description for more details about the fast−fault sequence.
14
Slow Fault
Slow Fault Detection
When asserted, the timer starts to countdown and shuts down the controller at
the end of its time duration.
15
OUT
OPAMP Output
16
NINV
OPAMP Noninverting
Internal transconductance amplifier.
Non−inverting pin of the OPAMP.
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3
NCP1395A/B
Vdd
Temperature
Shutdown
D
+
−
Vref
Q
−
R
+
50% DC
DT Adj.
I = Imax for Vfb = 5 V
I = 0 for Vfb < Vfb_off
Vdd
SS
gm
OUT
BO
Reset
Slow
Fault
+
−
+
Vref Fault
Fault
Vdd
+
FF
PON
Reset
Imax
Vfb = 5
NINV
+
Vref
VCC
Management
IDT
Q
Clk
Fmin
C
Vref_FB
S
Imin
Vfb = < Vfb_off
Timeout
Fault
Vref
Itimer
Fast
Fault
+
−
SS Reset on
A Version Only
Fmax
If FAULT Itimer else 0
+
Vref Fault
+
−
Timer
Timeout
Fault
+
Vref
PON
Reset
Fault
Vdd
20 V
VCC
UVLO
Fault
ISS
SS
B
A
+
−
FB
G=1
RFB
> 0 only if
V(FB) > Vfb_off
Vdd
−
+
+
Vfb_fault
PGND
+
Vfb_off
Vref
Deadtime
Adjustment
IDT
DT
Vdd
+
−
+
VBO
+
Vlatch
R
+
−
S
BO
Q
Q
IBO
20 ms Noise
Filter
AGND
Figure 2. Internal Circuit Architecture
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4
PON Reset
NCP1395A/B
MAXIMUM RATINGS
Rating
Power Supply Voltage, Pin 12
Transient Current Injected into VCC when Internal Zener is Activated –
Pulse Width < 10 ms
Power Supply Voltage, All Pins (Except Pins 10 and 11)
Symbol
Value
Unit
VCC
20
V
−
10
mA
−
−0.3 to 10
V
Thermal Resistance, Junction−to−Air, PDIP Version
RqJA
TBD
°C/W
Thermal Resistance, Junction−to−Air, SOIC Version
RqJA
TBD
°C/W
Storage Temperature Range
−
−60 to +150
°C
ESD Capability, HBM Model (All Pins Except VCC and HV)
−
2
kV
ESD Capability, Machine Model
−
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per Mil−Std−883, Method 3015
Machine Model Method 200 V.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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5
NCP1395A/B
ELECTRICAL CHARACTERISTICS (For typical values Tj = 25°C, for min/max values Tj = 0°C to +125°C, Max TJ = 150°C,
VCC = 11 V, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Turn−On Threshold Level, VCC Going Up – A Version
12
VCCON
12.3
13.3
14.3
V
Turn−On Threshold Level, VCC Going Up – B Version
12
VCCON
9.3
10.3
11.3
V
Minimum Operating Voltage after Turn−On
12
VCC(min)
8.3
9.3
10.3
V
Minimum Hysteresis between VCCON and VCC(min) − A Version
12
VhysteA
−
3.0
−
V
Minimum Hysteresis between VCCON and VCC(min) − B Version
12
VhysteB
−
1.0
−
V
Startup Current, VCC < VCCON
12
Istartup
−
−
300
mA
VCC Level at which the Internal Logic gets Reset
12
VCCreset
−
5.9
−
V
Internal IC Consumption, No Output Load on Pins 11/12, Fsw = 300 kHz
12
ICC1
−
1.6
−
mA
Internal IC consumption, 100 pF output load on pin 11 / 12, Fsw = 300 kHz
12
ICC2
−
2.3
−
mA
Consumption in fault mode (All drivers disabled, Vcc > VCC(min) )
12
ICC3
−
1.3
−
mA
Minimum Switching Frequency, Rt = 120 kW on Pin 1, Vpin 5 = 0 V,
DT = 300 ns
1
Fsw min
48.5
50
51.5
kHz
Maximum Switching Frequency, Rfmax = 22 kW on Pin 2, Vpin 5 >
6.0 V, DT = 300 ns − Tj = 25°C (Note 3)
2
Fsw max
0.9
1.0
1.11
MHz
Feedback Pin Swing above which Df = 0
5
FBSW
−
6.0
−
V
VCO VCC Rejection, DVCC = 1.0 V, in Percentage of Fsw
−
PSRR
−
0.2
−
%/V
11−10
DC
48
50
52
%
1, 3
VREF
1.86
2.0
2.14
V
−
Tdel
−
20
−
ms
Internal Pulldown Resistor
5
Rfb
−
20
−
kW
OTA Internal Offset Voltage
16
VREF_FB
2.325
2.5
2.675
V
Voltage on Pin 5 below which the FB Level has no VCO Action
5
Vfb_off
−
1.3
−
V
Voltage on Pin 5 below which the Controller Considers a Fault
5
Vfb_fault
−
0.6
−
V
Input Bias Current
16
IBias
−
−
100
nA
DC Transconductance Gain
15
OTAG
−
250
−
mS
Gain Product Bandwidth, Rload = 5.0 kW
15
GBW
−
1.0
−
MHz
Output Voltage Rise Time @ CL = 100 pF, 10−90% of Output Signal
11−10
Tr
−
20
−
ns
Output Voltage Fall−Time @ CL = 100 pF, 10−90% of Output Signal
11−10
Tf
−
20
−
ns
Source Resistance
11−10
ROH
20
60
120
W
Sink Resistance
11−10
ROL
30
60
130
W
SUPPLY SECTION
VOLTAGE CONTROL OSCILLATOR (VCO)
Operating Duty Cycle
Reference Voltage for all Current Generations (Fosc, DT)
Delay before any Driver Restart in Fault Mode
FEEDBACK SECTION
DRIVE OUTPUT
Deadtime with RDT = 127 kW from Pin 3 to GND
3
T_dead
270
300
390
ns
Maximum Deadtime with RDT = 540 kW from Pin 3 to GND
3
T_dead−max
−
1.0
−
ms
Minimum Deadtime, RDT = 30 kW from Pin 3 to GND
3
T_dead−min
−
150
−
ns
3. Room temperature only, please look at characterization data for evolution versus junction temperature.
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NCP1395A/B
ELECTRICAL CHARACTERISTICS (continued) (For typical values Tj = 25°C, for min/max values Tj = 0°C to +125°C,
Max TJ = 150°C, VCC = 11 V, unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Timer Charge Current
6
Itimer
−
150
−
mA
Timer Duration with a 1.0 mF Capacitor and a 1.0 MW Resistor
6
T−timer
−
25
−
ms
Timer Recurrence in Permanent Fault, Same Values as Above
6
T−timerR
−
1.4
−
s
Voltage at which Pin 6 Stops Output Pulses
6
VtimerON
3.7
4.1
4.5
V
Voltage at which Pin 6 Restarts Output Pulses
6
VtimerOFF
0.9
1.0
1.1
V
Soft−Start Ending Voltage, VFB = 1.0 V
4
VSS
−
2.0
−
V
Soft−Start Charge Current
4
ISS
75
Note 5
95
115
mA
Soft−Start Duration with a 220 nF Capacitor (Note 4)
4
T−SS
−
5.0
−
ms
Reference Voltage for Fast Input
13
VrefFaultF
1.0
1.05
1.1
V
Reference Voltage for Slow Input
14
VrefFaultS
0.98
1.03
1.08
V
Hysteresis for Fast Input
13
HysteFaultF
−
50
−
mV
Hysteresis for Slow Input
14
HysteFaultS
−
40
−
mV
Propagation Delay for Fast Fault Input Drive Shutdown
13
TpFault
−
70
120
ns
Brown−Out Input Bias Current
7
IBObias
−
0.02
−
mA
Brown−Out Level
7
VBO
0.98
1.03
1.08
V
Hysteresis Current, Vpin 7 > VBO – A Version
7
IBO_A
23
28
33
mA
Hysteresis Current, Vpin 7 > VBO – B Version
7
IBO_B
70
83
96
mA
Latching Voltage
7
Vlatch
3.7
4.1
4.5
V
Temperature Shutdown
−
TSD
140
−
−
°C
Hysteresis
−
TSDhyste
−
40
−
°C
TIMERS
PROTECTION
4. The A version does not activate soft−start when the fast−fault is released, this is for skip cycle implementation. The B version does activate
the soft−start upon release of the fast−fault input.
5. Minimum current occurs at TJ = 0°C.
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7
NCP1395A/B
13.5
10
13.4
9.8
VOLTAGE (V)
VOLTAGE (V)
TYPICAL CHARACTERISTICS − A VERSION
13.3
13.2
13.1
13.0
−40
9.6
9.4
9.2
−20
0
20
40
60
80
100
120
9.0
−40
140
−20
0
TEMPERATURE (°C)
50
1.1
49.5
1.0
49
48.5
−20
0
20
40
60
80
40
60
80
100
120
140
100
120
140
100
120
140
Figure 4. VCCmin
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 3. VCCon A
48
−40
20
TEMPERATURE (°C)
100
120
0.9
0.8
0.7
−40
140
−20
0
TEMPERATURE (°C)
20
40
60
80
TEMPERATURE (°C)
Figure 5. Fsw min
Figure 6. Fsw max
23
2.70
22
Vref_FB (V)
RFB (kW)
2.65
21
20
2.55
19
18
−40
2.60
−20
0
20
40
60
80
100
120
2.50
−40
140
TEMPERATURE (°C)
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 8. Pulldown Resistor (RFB)
Figure 7. Reference (Vref_FB)
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8
NCP1395A/B
TYPICAL CHARACTERISTICS − A VERSION
110
100
100
90
90
ROL (W)
ROH (W)
80
70
60
70
60
50
40
−40
80
50
−20
0
20
40
60
80
100
120
40
−40
140
−20
0
TEMPERATURE (°C)
Figure 9. Source Resistance (ROH)
210
DT_nom (ns)
DT_min (ns)
80
100
120
140
340
190
170
330
320
310
150
−20
0
20
40
60
80
100
120
300
−40
140
−20
0
TEMPERATURE (°C)
20
40
60
80
100
120
140
120
140
TEMPERATURE (°C)
Figure 11. T_dead_min A
Figure 12. T_dead_A
1300
1.10
1200
1.08
1100
VrefFaultFF (V)
DT_max (ns)
60
350
230
1000
900
1.06
1.04
1.02
800
700
−40
40
Figure 10. Sink Resistance (ROL)
250
130
−40
20
TEMPERATURE (°C)
−20
0
20
40
60
80
100
120
1.00
−40
140
TEMPERATURE (°C)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 14. T_dead_max A
Figure 13. Fast Fault (VrefFault FF)
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NCP1395A/B
TYPICAL CHARACTERISTICS − A VERSION
30
1.04
29
IBO (mA)
VBO (V)
1.035
1.03
28
27
1.025
26
−20
0
20
40
60
80
100
120
140
25
−40
−20
0
20
TEMPERATURE (°C)
4.15
4.1
4.05
−20
60
80
100
120
140
Figure 16. Brown−Out Hysteresis Current (IBO)
4.2
4.0
−40
40
TEMPERATURE (°C)
Figure 15. Brown−Out Reference (VBO)
Vlatch (V)
1.02
−40
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. Latch Level (Vlatch)
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10
120
140
NCP1395A/B
11
10
10.8
9.8
VCCmin (V)
VCCon (V)
TYPICAL CHARACTERISTICS − B VERSION
10.6
10.4
10.2
10
−40
9.6
9.4
9.2
−20
0
20
40
60
80
100
120
9.0
−40
140
−20
0
TEMPERATURE (°C)
50
1.1
49.5
1.0
49
48.5
−20
0
20
40
60
80
40
60
80
100
120
140
100
120
140
100
120
140
Figure 19. VCCmin
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 18. VCCon B
48
−40
20
TEMPERATURE (°C)
100
120
0.9
0.8
0.7
−40
140
−20
0
TEMPERATURE (°C)
20
40
60
80
TEMPERATURE (°C)
Figure 20. Fsw min
Figure 21. Fsw max
23
2.70
22
Vref_FB (V)
RFB (kW)
2.65
21
20
2.55
19
18
−40
2.60
−20
0
20
40
60
80
100
120
140
2.50
−40
TEMPERATURE (°C)
−20
0
20
40
60
80
TEMPERATURE (°C)
Figure 23. Pulldown Resistor (RFB)
Figure 22. Reference (Vref_FB)
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11
NCP1395A/B
TYPICAL CHARACTERISTICS − B VERSION
110
100
100
90
90
ROL (W)
ROH (W)
80
70
60
70
60
50
40
−40
80
50
−20
0
20
40
60
80
100
120
40
−40
140
−20
0
TEMPERATURE (°C)
Figure 24. Source Resistance (ROH)
210
DT_nom (ns)
DT_min (ns)
80
100
120
140
340
190
170
330
320
310
150
−20
0
20
40
60
80
100
120
300
−40
140
−20
0
TEMPERATURE (°C)
20
40
60
80
100
120
140
120
140
TEMPERATURE (°C)
Figure 26. T_dead_min B
Figure 27. T_dead_B
1300
1.10
1200
1.08
1100
VrefFaultFF (V)
DT_max (ns)
60
350
230
1000
900
1.06
1.04
1.02
800
700
−40
40
Figure 25. Sink Resistance (ROL)
250
130
−40
20
TEMPERATURE (°C)
−20
0
20
40
60
80
100
120
140
1.00
−40
TEMPERATURE (°C)
−20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 29. T_dead_max B
Figure 28. Fast Fault (VrefFault FF)
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12
NCP1395A/B
TYPICAL CHARACTERISTICS − B VERSION
1.035
85
IBO (mA)
90
VBO (V)
1.04
1.03
1.025
75
−20
0
20
40
60
80
100
120
140
70
−40
−20
0
20
TEMPERATURE (°C)
4.15
4.1
4.05
−20
60
80
100
120
140
Figure 31. Brown−Out Hysteresis Current (IBO)
4.2
4.0
−40
40
TEMPERATURE (°C)
Figure 30. Brown−Out Reference (VBO)
Vlatch (V)
1.02
−40
80
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 32. Latch Level (Vlatch)
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13
120
140
NCP1395A/B
APPLICATION INFORMATION
The NCP1395A/B includes all necessary features to help
build a rugged and safe switch−mode power supply
featuring an extremely low standby power. The below
bullets detail the benefits brought by implementing the
NCP1395A/B controller:
• Wide Frequency Range: A high−speed Voltage
Control Oscillator allows an output frequency
excursion from 50 kHz up to 1.0 MHz on A and B
outputs.
• Adjustable Deadtime: Due to a single resistor wired
to ground, the user has the ability to include some
deadtime, helping to fight cross−conduction between
the upper and the lower transistor.
• Adjustable Soft−Start: Every time the controller
starts to operate (power on), the switching frequency is
pushed to the programmed maximum value and slowly
moves down toward the minimum frequency, until the
feedback loop closes. The soft−start sequence is
activated in the following cases: a) normal startup
b) back to operation from an off state: during hiccup
faulty mode, brown−out or temperature shutdown
(TSD). In the NCP1395A, the soft−start is not
activated back to operation from the fast fault input,
unless the feedback pin voltage reaches 0.6 V. To the
opposite, in the B version, the soft−start is always
activated back from the fast fault input whatever the
feedback level is.
• Adjustable Minimum and Maximum Frequency
Excursion: In resonant applications, it is important to
stay away from the resonating peak to keep operating
the converter in the right region. Due to a single
external resistor, the designer can program its lowest
frequency point, obtained in lack of feedback voltage
(during the startup sequence or in short−circuit
conditions). Internally trimmed capacitors offer a
"3% precision on the selection of the minimum
switching frequency. The adjustable upper stop being
less precise to "15%.
• Low Startup Current: When directly powered from
the high−voltage DC rail, the device only requires
300 mA to startup. In case of an auxiliary supply, the
B version offers a lower startup threshold to cope with
a 12 V dc rail.
• Brown−Out Detection: To avoid operation from a
low input voltage, it is interesting to prevent the
controller from switching if the high−voltage rail is
not within the right boundaries. Also, when teamed
with a PFC front−end circuitry, the brown−out
detection can ensure a clean startup sequence with
soft−start, ensuring that the PFC is stabilized before
energizing the resonant tank. The A version features a
•
•
•
•
•
•
28 mA hysteresis current for the lowest consumption
and the B version slightly increases this current to
83 mA in order to improve the noise immunity.
Adjustable Fault Timer Duration: When a fault is
detected on the slow fault input or when the FB path is
broken, a timer starts to charge an external capacitor.
If the fault is removed, the timer opens the charging
path and nothing happens. When the timer reaches its
selected duration (via a capacitor on pin 6), all pulses
are stopped. The controller now waits for the
discharge via an external resistor of pin 6 capacitor to
issue a new clean startup sequence with soft−start.
Cumulative Fault Events: In the NCP1395A/B, the
timer capacitor is not reset when the fault disappears.
It actually integrates the information and cumulates
the occurrences. A resistor placed in parallel with the
capacitor will offer a simple way to adjust the
discharge rate and thus the auto−recovery retry rate.
Fast and Slow Fault Detection: In some application,
subject to heavy load transients, it is interesting to
give a certain time to the fault circuit, before
activating the protection. On the other hand, some
critical faults cannot accept any delay before a
corrective action is taken. For this reason, the
NCP1395A/B includes a fast fault and a slow fault
input. Upon assertion, the fast fault immediately stops
all pulses and stays in the position as long as the
driving signal is high. When released low (the fault
has gone), the controller has several choices: in the
A version, pulses are back to a level imposed by the
feedback pin without soft−start, but in the B version,
pulses are back through a regular soft−start sequence.
Skip Cycle Possibility: The absence of soft−start on
the NCP1395A fast fault input offers an easy way to
implement skip cycle when power saving features are
necessary. A simple resistive connection from the
feedback pin to the fast fault input, and skip can be
implemented.
Onboard Transconductance Op Amp: A
transconductance amplifier is used to implement
various options, like monitoring the output current and
maintaining it constant.
Broken Feedback Loop Detection: Upon startup or
any time during operation, if the FB signal is missing,
the timer starts to charge a capacitor. If the loop is
really broken, the FB level does not grow up before
the timer ends counting. The controller then stops all
pulses and waits that the timer pin voltage collapses to
1.0 V typically before a new attempt to restart, via the
soft−start. If the optocoupler is permanently broken, a
hiccup takes place.
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14
NCP1395A/B
• Finally, Two Circuit Versions, A and B: The A and
more recommended for industrial/medical
applications where a 12 V auxiliary supply
directly powers the chip.
2. The A version does not activate the soft−start
upon release of the fast fault input. This is to let
the designer implement skip cycle. To the
opposite, the B version goes back to operation
upon the fast fault pin release via a soft−start
sequence.
B versions differ because of the following changes:
1. The startup thresholds are different, the A starts
to pulse for VCC = 12.8 V whereas the B pulses
for VCC = 10 V. The turn off levels are the
same, however. The A is recommended for
consumer products where the designer can use
an external startup resistor, whereas the B is
Voltage−Controlled Oscillator
The VCO section features a high−speed circuitry
allowing an internal operation from 100 kHz up to
2.0 MHz. However, as a division by two internally creates
the two Q and Qbar outputs, the final effective signal on
output A and B switches between 50 kHz and 1.0 MHz.
The VCO is configured in such a way that if the feedback
pin goes up, the switching frequency also goes up.
Figure 33 shows the architecture of this oscillator.
FBinternal
Vdd
+
−
max
Fsw
max
Imin
0 to I_Fmax
Vref
Fmin
S
D
+
−
Rt−m sets
Fmin for V(FB) < Vfb_off
Q
Clk
Cint
Q
R
+
Vdd
IDT
A
Vref
Imin
DT
Rdt sets
the deadtime
Vdd
Fmax
Vcc
Rt−max sets
the maximum Fsw
FB
−
+
Rfb
20 k
Vb_fault
Figure 33. Simplified VCO Architecture
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15
+
Vfb < Vb_fault
start fault timer
B
NCP1395A/B
The designer needs to program the maximum switching
frequency and the minimum switching frequency. In LLC
configurations, for circuits working above the resonant
frequency, a high precision is required on the minimum
frequency, hence the "3% specification. This minimum
switching frequency is actually reached when no feedback
closes the loop. It can happen during the startup sequence,
a strong output transient loading or in a short−circuit
condition. By installing a resistor from pin 1 to AGND, the
minimum frequency is set. Using the same philosophy,
wiring a resistor from pin 2 to AGND will set the maximum
frequency excursion. To improve the circuit protection
features, we have purposely created a dead zone, where the
feedback loop has no action. This is typically below 1.3 V.
Figure 34 details the arrangement where the internal
voltage (that drives the VCO) varies between 0 and 3.6 V.
However, to create this swing, the feedback pin (to which
the optocoupler emitter connects), will need to swing
typically between 1.3 V and 6.0 V.
Figures 35 and 36 portray the frequency evolution
depending on the feedback pin voltage level in a different
frequency clamp combination.
FA&B
ÑÑÑÑ
ÏÏÏÏ
ÏÏÏÏ
ÑÑÑÑ
ÏÏÏÏ
ÑÑÑÑ
No variations
1 MHz
Fmax
DFsw = 950 kHz
Fmin
Fault
area
Î
Ì
50 kHz
VFB
6V
1.3 V D
VFB = 4.7V
0.6 V
Figure 35. Maximal default excursion, Rt = 120 kW
on pin 1 and Rfmax = 35 kW on pin 2.
VCC
FA&B
VFB = 1.3−6 V
FB
+
−
To VCO
0 to 3.6 V
ÒÒÒÒ
ÔÔÔÔ
ÔÔÔÔ
ÒÒÒÒ
No variations
450 kHz
Fmax
Rfb
DFsw = 300 kHz
+
1.3 V
Fmin
Fault
area
Figure 34. The OPAMP arrangement limits the VCO
internal modulation signal between 0 and 5.0 V.
150 kHz
VFB
6V
1.3 V D
VFB = 4.7 V
0.6 V
Figure 36. Here a different minimum frequency
was programmed as well as a different maximum
frequency excursion.
This technique allows us to detect a fault on the converter
in case the FB pin cannot rise above 1.3 V (to actually close
the loop) in less than a duration imposed by the
programmable timer. Please refer to the fault section for
detailed operation of this mode.
As shown in Figure 34, the internal dynamics of the
VCO control voltage will be constrained between 0 V and
3.6 V, whereas the feedback loop will drive pin 5 (FB)
between 1.3 V and 6.0 V. If we take the external excursion
numbers, 1.3 V = 50 kHz, 6.0 V = 1.0 MHz, then the VCO
slope will then be
Ö
Ó
Ó
Ö
Please note that the previous small signal VCO slope has
now been reduced to 300 k/5.0 = 62.5 kHz/V. This offers
a mean to magnify the feedback excursion on systems
where the load range does not generate a wide switching
frequency excursion. Due to this option, we will see how
it becomes possible to observe the feedback level and
implement skip cycle at light loads. It is important to note
that the frequency evolution does not have a real linear
relationship with the feedback voltage. This is due to the
deadtime presence which stays constant as the switching
period changes.
1 Meg−50 k
+ 202 kHzńV.
4.7
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16
NCP1395A/B
1100
The selection of the three setting resistors (Fmax, Fmin
and deadtime) requires the usage of the selection charts
displayed below:
1000
VCC = 11 V
900
800
1100
700
900
DT (ns)
VCC = 11 V
FB = 6.5 V
DT = 300 ns
600
500
Fmax (kHz)
400
700
300
200
100
0
0
500
Fmin = 200 kHz
100
200
300
Fmin = 50 kHz
100
20
400
500
600
70
120
170
220
Figure 39. Dead−Time Resistor Selection
270
320
370
RFmax (kW)
ORing Capability
If for a particular reason, there is a need for having a
frequency variation linked to an event appearance (instead
of abruptly stopping pulses), then the FB pin lends itself
very well to the addition of other sweeping loops. Several
diodes can easily be used to perform the job in case of
reaction to a fault event or to regulate on the output current
(CC operation). Figure 40 shows how to do it.
Figure 37. Maximum switching frequency resistor
selection depending on the adopted minimum
switching frequency.
200
VCC = 11 V
FB = 1 V
DT = 300 ns
180
160
Fmin (kHz)
300
Rdt (kW)
VCC
140
120
100
In1
80
In2
FB
VCO
20 k
60
40
20
40
60
80
100
120
Figure 40. Due to the FB configuration, loop ORing
is easy to implement.
RFmin (kW)
Figure 38. Minimum Switching Frequency Resistor
Selection
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NCP1395A/B
Deadtime Control
Deadtime control is an absolute necessity when the
half−bridge configuration comes to play. The deadtime
technique consists of inserting a period during which both
high and low side switches are off. Of course, the deadtime
amount differs depending on the switching frequency,
hence the ability to adjust it on this controller. The option
ranges between 150 ns and 1.0 ms. The deadtime is actually
made by controlling the oscillator discharge current.
Figure 41 portrays a simplified VCO circuit based on
Figure 33.
Vdd
Icharge:
Fsw min + Fsw max
S
D
+
Clk
−
Idis
Ct
Q
Q
R
+
3 V−1 V
Vref
DT
RDT
A
B
Figure 41. Deadtime Generation
During the discharge time, the clock comparator is high
and unvalidates the AND gates: both outputs are low. When
the comparator goes back to the high level, during the
timing capacitor Ct recharge time, A and B outputs are
validated. By connecting a resistor RDT to ground, it
creates a current whose image serves to discharge the Ct
capacitor: we control the deadtime. The typical range
evolves between 150 ns (RDT = 30 kW) and 1.0 ms (RDT
= 600 kW). Figure 44 shows the typical waveforms
obtained on the output.
circuit. In this controller, a soft−start capacitor connects to
pin 4 and offers a smooth frequency variation upon startup:
when the circuit starts to pulse, the VCO is pushed to the
maximum switching frequency imposed by pin 2. Then, it
linearly decreases its frequency toward the minimum
frequency selected by a resistor on pin 1. Of course,
practically, the feedback loop is suppose to take over the
VCO lead as soon as the output voltage has reached the
target. If not, then the minimum switching frequency is
reached and a fault is detected on the feedback pin
(typically below 600 mV). Figure 43 depicts a typical
frequency evolution with soft−start.
Soft−Start Sequence
In resonant controllers, a soft−start is needed to avoid
suddenly applying the full current into the resonating
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18
NCP1395A/B
1 ires1 2 vout
Plot1
ires1 in amperes
20.0
10.0
0
1
−10.0
−20.0
Ires
SS Action
Plot2
vout in volts
177
Target is
reached
175
2
Vout
173
171
169
200u
Figure 42. Soft−Start Behavior
600u
1.00m
time in seconds
1.40m
1.80m
Figure 43. A Typical Startup Sequence on an LLC
Converter
Please note that the soft−start will be activated in the
following conditions:
• A startup sequence
• During auto−recovery burst mode
• A brown−out recovery
• A temperature shutdown recovery
The fast fault input undergoes a special treatment. Since
we want to implement skip cycle through the fast fault
input on the NCP1395A, we cannot activate the soft−start
every time the feedback pin stops the operations in low
power mode. Therefore, when the fast fault pin is released,
no soft−start occurs to offer the best skip cycle behavior.
However, it is very possible to combine skip cycle and true
fast fault input, e.g. via ORing diodes driving pin 13. In that
case, if a signal maintains the fast fault input high long
enough to bring the feedback level down (that is to say
below 0.6 V) since the output voltage starts to fall down,
then the soft−start is activated after the release of the pin.
In the B version tailored to operate from an auxiliary
12 V power supply, the soft−start is always activated upon
the fast fault input release, whatever the feedback
condition is.
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19
NCP1395A/B
1 vct
2 clock
5 difference
plot1
vct in volts
4.00
3.00
2.00
1
1.00
0
plot2
clock in volts
16.0
12.0
8.00
4.00
2
0
Plot3
difference in volts
8.00
5
4.00
0
−4.00
−8.00
56.2u
65.9u
75.7u
time in seconds
85.4u
95.1u
Figure 44. Typical Oscillator Waveforms
Brown−Out Protection
The Brown−Out circuitry (BO) offers a way to protect the
resonant converter from low DC input voltages. Below a
given level, the controller blocks the output pulses, above
it, it authorizes them. The internal circuitry, depicted by
Figure 42, offers a possibility to observe the high−voltage
(HV) rail. A resistive divider made of Rupper and Rlower,
brings a portion of the HV rail on pin 7. Below the turn−on
level, a current source IBO is off. Therefore, the turn−on
level solely depends on the division ratio brought by the
resistive divider.
1 vin 2 vcmp
450 16.0
351 volts
350 12.0
Vbulk
ON/OFF
IBO
BO
+
−
BO
250
vcmpin volts
250 volts
Plot1
vin in volts
Rupper
Vdd
Vin
8.00
150 4.00
Rlower
+
VBO
50.0
0
2
BO
1
20.0u
Figure 45. The Internal Brown−Out
Configuration with an Offset Current Source
60.0u
100u
time in seconds
140u
180u
Figure 46. Simulation Results for 350/250 ON/OFF Levels
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20
NCP1395A/B
To the contrary, when the internal BO signal is high
(A and B pulse), the IBO source is activated and creates
a hysteresis. The hysteresis level actually depends
on the circuit: NCP1395A features a 28 mA whereas
the NCP1395B uses a 83 mA current. Changes are
implemented to a) reduce the standby power on the
NCP1395A b) improve the noise immunity on the
NCP1395B. Knowing these values, it becomes possible to
select the turn−on and turn−off levels via a few lines of
algebra:
IBO is off
Rlower
Rlower ) Rupper
V()) + Vbulk1
(eq. 1)
IBO is on
V()) + Vbulk2
Rlower
) IBO
Rlower ) Rupper
Rlower + VBO
Vbulk1−VBO
VBO
Vbulk1−Vbulk2
IBO (Vbulk1−VBO)
If we decide to turn on our converter for Vbulk1 equals
350 V, and turn it off for Vbulk2 equals 250 V, then we
obtain:
Latch−Off Protection
There are some situations where the converter shall be
fully turned off and stay latched. This can happen in
presence of an overvoltage (the feedback loop is drifting)
or when an overtemperature is detected. Due to the addition
of a comparator on the BO pin, a simple external circuit can
lift up this pin above VLATCH (5.0 V typical) and
permanently disable pulses. The VCC needs to be cycled
down below 5.0 V typically to reset the controller.
IBO = 28 mA
Rupper = 3.6 MW
Rlower = 10 kW
The bridge power dissipation is 4002/3.601 MW =
45 mW when the front−end PFC stage delivers 400 V.
VCC
(eq. 2)
IBO = 83 mA
Rupper = 1.2 MW
Rlower = 3.4 kW
The bridge power dissipation is 132 mW when the
front−end PFC stage delivers 400 V. Figure 46 simulation
result confirms our calculations.
We can now extract Rlower from Equation 1 and plug it
into Equation 2, then solve for Rupper:
Rupper + Rlower
Rupper
ǒRlower
Ǔ
Rlower ) Rupper
Vbulk
20 ms
RC
+
−
Q1
Vout
To permanent
latch
+
Vlatch
Rupper
IBO
Vdd
BO
NTC
Rlower
+
−
BO
+
VBO
Figure 47. Adding a comparator on the BO pin offers a way to latch−off the controller.
In Figure 47, Q1 is blocked and does not bother the BO
measurement as long as the NTC and the optocoupler are
not activated. As soon as the secondary optocoupler senses
an OVP condition, or the NTC reacts to a high ambient
temperature, Q1 base is brought to ground and the BO pin
goes up, permanently latching off the controller.
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21
NCP1395A/B
Protection Circuitry
This resonant controller differs from competitors due to
its protection features. The device can react to various
inputs like:
• Fast events input: Like an overcurrent condition, a
need to shutdown (sleep mode) or a way to force a
controlled burst mode (skip cycle at low output
power): as soon as the input level exceeds 1.0 V
typical, pulses are immediately stopped. On the
A version, when the input is released, the controller
performs a clean startup sequence without soft−start
unless the feedback voltage goes down below 0.6 V
•
during fault time (please see above for details). The
B version restarts with a soft−start sequence.
Slow events input: This input serves as a delayed
shutdown, where an event like a transient overload
does not immediately stopped pulses but start a timer.
If the event duration lasts longer than what the timer
imposes, then all pulses are disabled. The voltage on
the timer capacitor (pin 3) starts to decrease until it
reaches 1.0 V. The decrease rate is actually depending
on the resistor the user will put in parallel with the
capacitor, giving another flexibility during design.
Figure 48 depicts the architecture of the fault circuitry.
Vdd
Itimer
Ctimer
UVLO
Reset
1 = fault
0 = ok
Rtimer
+
+ −
VtimerON
VtimerOFF
+
−
Vref Fault
1 = ok
0 = fault
Output
Current
Image
NINV
Vref
ON/OFF
Ctimer
+
+
−
+
CC Regulation
Out
−
+
Vref Fault
Compensation
+
Slow Fault
1 = ok
0 = fault
Reset
DRIVING
LOGIC
Fast Fault
SS
A
A
B
B
To FB
Figure 48. This Circuit Combines a Slow and Fast Input for Improved Protection Features
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22
Fast
Input
NCP1395A/B
In this figure, the internal OPAMP is used to perform a
kind of constant current operation (CC) by taking the lead
when the other voltage loop is gone (CV). Due to the ORing
capability on the FB pin, the OPAMP regulates in constant
current mode. When the output reaches a low level close to
a complete short−circuit, the OPAMP output is maximum.
With a resistive divider on the slow fault, this condition can
be detected to trigger the delayed fault. If no OPAMP shall
be used, its input must be grounded.
reaches the VtimerON level (4.0 V typical), then all pulses
are stopped. Itimer turns off and the capacitor slowly
discharges to ground via a resistor installed in parallel with
it. As a result, the designer can easily determine the time
during which the power supply stays locked by playing on
Rtimer. Now, when the timer capacitor voltage reaches
1.0 V typical (VtimerOFF), the comparator instructs the
internal logic to issues pulses as on a clean soft−start
sequence (soft−start is activated). Please note that the
discharge resistor cannot be lower than 4.0 V/Itimer,
otherwise the voltage on Ctimer will never reach the
turn−off voltage of 4.0 V.
In both cases, when the fault is validated, both outputs A
and B are internally pulled down to ground.
Slow Input
On this circuit, the slow input goes to a comparator.
When this input exceeds 1.0 V typical, the current source
Itimer turns on, charging the external capacitor Ctimer. If
the fault duration is long enough, when Ctimer voltage
VCC
FB
Fast Fault
Figure 49. A resistor can easily program the capacitor discharge time.
Fast Input
Figure 50. Skip cycle can be
implemented via two
resistors on the FB pin to the
fast fault input.
Startup Behavior
When the VCC voltage grows up, the internal current
consumption is kept to Istup, allowing to crank up the
converter via a resistor connected to the bulk capacitor.
When VCC reaches the VCCON level, output A goes high
first and then output B. This sequence will always be the
same, whatever triggers the pulse delivery: fault, OFF to
ON etc… Pulsing the output A high first gives an
immediate charge of the bootstrap capacitor when an
integrated high voltage half−bridge driver is implemented
such as ON Semiconductor’s NCP5181. Then, the rest of
pulses follow, delivered at the highest switching value, set
by the resistor on pin 2. The soft−start capacitor ensures a
smooth frequency decrease to either the programmed
minimum value (in case of fault) or to a value
corresponding to the operating point if the feedback loop
closes first. Figure 51 shows typical signals evolution at
power on.
The fast input is not affected by a delayed action. As soon
as its voltage exceeds 1.0 V typical, all pulses are off and
maintained off as long as the fault is present. When the pin
is released, pulses come back without soft−start for the
A version, with soft−start for the B version.
Due to the low activation level of 1.0 V, this pin can
observe the feedback pin via a resistive divided and thus
implement skip cycle operation. The resonant converter
can be designed to lose regulation in light load conditions,
forcing the FB level to increase. When it reaches the
programmed level, it triggers the fast fault input and stops
pulses. Then Vout slowly drops, the loop reacts by
decreasing the feedback level which, in turn, unlocks the
pulses: Vout goes up again and so on: we are in skip cycle
mode.
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NCP1395A/B
VCCON
VCC(min)
Vcc from an auxiliary supply
SS
FB
TSS
Fault!
TSS
0.6V
A&B
A
Timer
B
A
B
4V
Slopes are similar
1V
Figure 51. At power on, output A is first activated and the frequency slowly
decreases via the soft−start capacitor.
Figure 51 depicts an auto−recovery situation, where the
timer has triggered the end of output pulses. In that case, the
VCC level was given by an auxiliary power supply, hence
its stability during the hiccup. A similar situation can arise
if the user selects a more traditional startup method,
with an auxiliary winding. In that case, the VCC(min)
comparator stops the output pulses whenever it is activated,
that is to say, when VCC falls below 10.3 V typical. At this
time, the VCC pin still receives its bias current from the
startup resistor and heads toward VCCON via the Vcc
capacitor. When the voltage reaches VCCON, a standard
sequence takes place, involving a soft−start. Figure 52
portrays this behavior.
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24
NCP1395A/B
VCCON
VCC(min)
Vcc from a startup resistor
Fault is
released
Fault!
SS
FB
TSS
TSS
0.6V
A&B
A
Timer
B
A
B
4V
1V
Figure 52. When the VCC is too low, all pulses are stopped until VCC goes back
to the startup voltage.
As described in the data sheet, two startup levels VCCON
are available, via two circuit versions. The NCP1395A
features a large hysteresis to allow a classical startup
method with a resistor connected to the bulk capacitor.
Then, at the end of the startup sequence, an auxiliary
winding is supposed to take over the controller supply
voltage. To the opposite, for applications where the
resonant controller is powered from a standby power
supply, the startup level of the NCP1395B of 10 V typically
allows a direct a connection from a 12 V source. Simple
ON/OFF operation is therefore feasible.
ORDERING INFORMATION
Package
Shipping†
NCP1395APG
Device
PDIP−16
(Pb−Free)
25 Units / Rail
NCP1395ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
NCP1395BPG
PDIP−16
(Pb−Free)
25 Units / Rail
NCP1395BDR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
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25
NCP1395A/B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
SEATING
PLANE
−T−
K
H
D
M
J
G
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
−A−
16
9
1
8
−B−
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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26
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
NCP1395A/B
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NCP1395/D