CAT28C17A 16 kb CMOS Parallel EEPROM Description The CAT28C17A is a fast, low power, 5 V−only CMOS Parallel EEPROM organized as 2K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and a RDY/BSY pin signal the start and end of the self−timed write cycle. Additionally, the CAT28C17A features hardware write protection. The CAT28C17A is manufactured using ON Semiconductor’s advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 28−pin DIP and SOIC or 32−pin PLCC packages. http://onsemi.com SOIC−28 J, K, W, X SUFFIX CASE 751BM Features • Fast Read Access Times: 200 ns • Low Power CMOS Dissipation: • • • • • • • • – Active: 25 mA Max. – Standby: 100 mA Max. Simple Write Operation: – On−chip Address and Data Latches – Self−timed Write Cycle with Auto−clear Fast Write Cycle Time: 10 ms Max End of Write Detection: − DATA Polling − RDY/BSY Pin Hardware Write Protection CMOS and TTL Compatible I/O 10,000 Program/Erase Cycles 10 Year Data Retention Commercial, Industrial and Automotive Temperature Ranges PDIP−28 P, L SUFFIX CASE 646AE PLCC−32 N, G SUFFIX CASE 776AK PIN FUNCTION Pin Name A0−A10 Function Address Inputs I/O0−I/O7 Data Inputs/Outputs RDY/BUSY Ready/BUSY Status CE Chip Enable OE Output Enable WE Write Enable VCC 5 V Supply VSS Ground NC No Connect ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 4 1 Publication Order Number: CAT28C17A/D CAT28C17A PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, K, W, X) 1 2 28 27 VCC WE A7 3 A6 4 26 25 A5 A4 A3 5 6 24 NC A8 A9 23 NC 7 8 22 21 9 20 19 OE A10 CE A2 A1 A0 I/O0 A4−A10 10 11 I/O1 12 I/O2 VSS 13 14 18 17 16 15 I/O7 I/O6 I/O5 A7 NC RDY/BUSY NC VCC WE NC NC A6 A5 A4 A3 A2 A1 A0 NC I/O0 I/O4 I/O3 ROW DECODER ADDR. BUFFER & LATCHES VCC INADVERTENT WRITE PROTECTION CE OE WE CONTROL LOGIC 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 A8 A9 NC NC OE A10 CE I/O7 I/O6 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 RDY/BUSY PLCC Package (N, G) 2,048 x 8 EEPROM ARRAY HIGH VOLTAGE GENERATOR I/O BUFFERS DATA POLLING & RDY/BUSY TIMER I/O0−I/O7 A0−A3 ADDR. BUFFER & LATCHES COLUMN DECODER RDY/BUSY Figure 1. Block Diagram http://onsemi.com 2 CAT28C17A Table 1. MODE SELECTION Mode CE WE OE I/O Power Read L H L DOUT ACTIVE Byte Write (WE Controlled) L H DIN ACTIVE L H DIN ACTIVE Byte Write (CE Controlled) Standby and Write Inhibit H X X High−Z STANDBY Read and Write Inhibit X H H High−Z ACTIVE Max Conditions Units Table 2. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V) Symbol Test CI/O (Note 1) Input/Output Capacitance 10 VI/O = 0 V pF CIN (Note 1) Input Capacitance 6 VIN = 0 V pF 1. This parameter is tested initially and after a design or process change that affects the parameter. Table 3. ABSOLUTE MAXIMUM RATINGS Ratings Units Temperature Under Bias Parameters –55 to +125 °C Storage Temperature –65 to +150 °C –2.0 V to +VCC + 2.0 V V −2.0 to +7.0 V Package Power Dissipation Capability (TA = 25°C) 1.0 W Lead Soldering Temperature (10 secs) 300 °C Output Short Circuit Current (Note 3) 100 mA Voltage on Any Pin with Respect to Ground (Note 2) VCC with Respect to Ground Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. http://onsemi.com 3 CAT28C17A Table 4. RELIABILITY CHARACTERISTICS (Note 4) Symbol NEND Parameter Test Method Min Max Units Endurance MIL−STD−883, Test Method 1033 10,000 Cycles/Byte TDR Data Retention MIL−STD−883, Test Method 1008 10 Years VZAP ESD Susceptibility MIL−STD−883, Test Method 3015 2,000 V Latch−Up JEDEC Standard 17 100 mA ILTH (Note 5) 4. This parameter is tested initially and after a design or process change that affects the parameter. 5. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 5 V ±10%, unless otherwise specified.) Limits Symbol ICC Parameter Test Conditions Min Typ Max Units VCC Current (Operating, TTL) CE = OE = VIL, f = 1/tRC min, All I/O’s Open 35 mA VCC Current (Operating, CMOS) CE = OE = VILC, f = 1/tRC min, All I/O’s Open 25 mA VCC Current (Standby, TTL) CE = VIH, All I/O’s Open 1 mA VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 100 mA ILI Input Leakage Current VIN = GND to VCC −10 10 mA ILO Output Leakage Current VOUT = GND to VCC, CE = VIH −10 10 mA VIH (Note 7) High Level Input Voltage 2 VCC + 0.3 V VIL (Note 6) Low Level Input Voltage −0.3 0.8 V ICCC (Note 6) ISB ISBC (Note 7) VOH High Level Output Voltage IOH = −400 mA VOL Low Level Output Voltage IOL = 2.1 mA VWI Write Inhibit Voltage 2.4 V 0.4 3.0 V V 6. VILC = −0.3 V to +0.3 V 7. VIHC = VCC −0.3 V to VCC + 0.3 V Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V ±10%, unless otherwise specified.) 28C17A−20 Symbol Min Parameter Max 200 Units tRC Read Cycle Time ns tCE CE Access Time 200 ns tAA Address Access Time 200 ns tOE OE Access Time 80 ns tLZ (Note 8) CE Low to Active Output 0 ns tOLZ (Note 8) OE Low to Active Output 0 ns tHZ (Notes 8, 9) CE High to High−Z Output 55 ns tOHZ (Notes 8, 9) OE High to High−Z Output 55 ns tOH (Note 8) Output Hold from Address Change 0 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer. http://onsemi.com 4 ns CAT28C17A 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V Figure 2. A.C. Testing Input/Output Waveform (Note 10) 10. Input rise and fall times (10% and 90%) < 10 ns. 1.3 V 1N914 3.3 K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Figure 3. A.C. Testing Load Circuit (example) Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.) 28C17A−20 Min Parameter Symbol Max Units 10 ms tWC Write Cycle Time tAS Address Setup Time 10 ns tAH Address Hold Time 100 ns tCS CE Setup Time 0 ns tCH CE Hold Time 0 ns tCW (Note 11) CE Pulse Time 150 ns tOES OE Setup Time 15 ns tOEH OE Hold Time 15 ns tWP (Note 11) WE Pulse Width 150 ns tDS Data Setup Time 50 ns tDH Data Hold Time 10 ns tDL Data Latch Time 50 ns Write Inhibit Period After Power−up 5 tINIT (Note 12) tDB Time to Device Busy 11. A write pulse of less than 20 ns duration will not initiate a write cycle. 12. This parameter is tested initially and after a design or process change that affects the parameter. http://onsemi.com 5 20 ms 80 ns CAT28C17A DEVICE OPERATION Read Ready/BUSY (RDY/BUSY) Data stored in the CAT28C17A is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to eliminate bus contention in a system environment. The RDY/BUSY pin is an open drain output which indicates device status during programming. It is pulled low during the write cycle and released at the end of programming. Several devices may be OR−tied to the same RDY/BUSY line. tRC ADDRESS tCE CE tOE OE WE tOLZ VIH tLZ tHZ tOH HIGH−Z DATA OUT tOHZ tAA DATA VALID DATA VALID Figure 4. Read Cycle tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tDL RDY/BUSY tDB DATA OUT DATA IN HIGH−Z DATA VALID tDS tDH Figure 5. Byte Write Cycle [WE Controlled] http://onsemi.com 6 CAT28C17A Byte Write DATA Polling A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self−timed byte write cycle, all I/O’s will output true data during a read cycle. tWC ADDRESS tAS tAH tDL tCW CE tOEH OE tCS tOES tCH WE RDY/BUSY tDB DATA OUT DATA IN HIGH−Z DATA VALID tDS tDH Figure 6. Byte Write Cycle [CE Controlled] http://onsemi.com 7 CAT28C17A ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DOUT = X DIN = X DOUT = X Figure 7. DATA Polling Hardware Data Protection The following is a list of hardware data protection features that are incorporated into the CAT28C17A. 1. VCC sense provides for write protection when VCC falls below 3.0 V min. 2. A power on delay mechanism, tINIT (see AC characteristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0 V min. 3. Write inhibit is activated by holding any one of OE low, CE high or WE high. 4. Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. http://onsemi.com 8 CAT28C17A PACKAGE DIMENSIONS PLCC 32 CASE 776AK−01 ISSUE O PIN#1 IDENTIFICATION E1 E E2 D1 A2 D A3 TOP VIEW END VIEW b1 b e D2 SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-016. SYMBOL MIN A2 0.38 A3 2.54 2.80 9 MAX b 0.33 0.54 b1 0.66 0.82 D 12.32 12.57 D1 11.36 11.50 D2 9.56 11.32 E 14.86 15.11 E1 13.90 14.04 E2 12.10 13.86 e http://onsemi.com NOM 1.27 BSC CAT28C17A PACKAGE DIMENSIONS SOIC−28, 300 mils CASE 751BM−01 ISSUE O SYMBOL MIN A 2.35 E NOM 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 c 0.20 0.33 D 17.78 18.03 E 10.11 10.51 E1 7.34 7.60 e b e PIN #1 IDENTIFICATION MAX 1.27 BSC h 0.25 0.75 L 0.40 1.27 θ 0º 8º θ1 5º 15º TOP VIEW h D A2 A A1 h q1 q q1 c L E1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. http://onsemi.com 10 CAT28C17A PACKAGE DIMENSIONS PDIP−28, 600 mils CASE 646AE−01 ISSUE A SYMBOL MIN NOM A E1 E D 6.35 A1 0.39 A2 3.18 4.95 b 0.36 0.55 b1 0.77 1.77 c 0.21 0.38 D 35.10 39.70 E 15.24 15.87 E1 12.32 e TOP VIEW A2 14.73 2.54 BSC eB 15.24 17.78 L 2.93 5.08 A c A1 b1 e L b eB SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-011. http://onsemi.com 11 MAX CAT28C17A Example of Ordering Information Prefix Device # Suffix CAT 28C17A N Company ID (Optional) Product Number 28C17A I − 20 Tape & Reel (Note 16) T: Tape & Reel Temperature Range Blank = Commercial (0°C to +70°C) I = Industrial (−40°C to +85°C) A = Automotive (−40°C to +105°C) (Note 15) Package P: PDIP (Note 14) N: PLCC (Note 14) J: SOIC (JEDEC) (Note 14) K: SOIC (EIAJ) (Note 14) L: PDIP (Lead Free, Halogen Free) G: PLCC (Lead Free, Halogen Free) W: SOIC (JEDEC) (Lead Free, Halogen Free) X: SOIC (EIAJ) (Lead Free, Halogen Free) T Speed 20: 200 ns 13. The device used in the above example is a CAT28C17ANI−20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel). 14. Solder−plate (tin−lead) packages, contact Factory for availability. 15. −40°C to +125°C is available upon request. 16. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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