HUF76407D3, HUF76407D3S Data Sheet October 1999 File Number 4664.1 11A, 60V, 0.107 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging Features JEDEC TO-251AA DRAIN (FLANGE) JEDEC TO-252AA DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE HUF76407D3S HUF76407D3 • Ultra Low On-Resistance - rDS(ON) = 0.092Ω, VGS = 10V - rDS(ON) = 0.107Ω, VGS = 5V • Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Impedance Models - www.Intersil.com • Peak Current vs Pulse Width Curve Symbol • UIS Rating Curve D • Switching Time vs RGS Curves Ordering Information G PART NUMBER S PACKAGE BRAND HUF76407D3 TO-251AA 76407D HUF76407D3S TO-252AA 76407D NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HUF76407D3ST. Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HUF76407D3, HUF76407D3S UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 60 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V Drain Current Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 135oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 135oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 11 12 6 6 Figure 4 A A A A Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Figures 6, 17, 18 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 0.25 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC NOTE: 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation. SABER© is a Copyright of Analogy Inc. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HUF76407D3, HUF76407D3S TC = 25oC, Unless Otherwise Specified Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ID = 250µA, VGS = 0V (Figure 12) 60 - - V ID = 250µA, VGS = 0V , TC = -40oC (Figure 12) 55 - - V VDS = 55V, VGS = 0V - - 1 µA VDS = 50V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±16V - - ±100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS Gate to Source Leakage Current IGSS ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V Drain to Source On Resistance rDS(ON) ID = 13A, VGS = 10V (Figures 9, 10) - 0.077 0.092 Ω ID = 8A, VGS = 5V (Figure 9) - 0.095 0.107 Ω ID = 8A, VGS = 4.5V (Figure 9) - 0.107 0.117 Ω TO-220 - - 3.94 oC/W - - 100 oC/W - - 170 ns - 8 - ns THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time tON Turn-On Delay Time td(ON) tr - 105 - ns td(OFF) - 22 - ns tf - 39 - ns tOFF - - 92 ns - - 56 ns - 5 - ns - 32 - ns td(OFF) - 43 - ns tf - 45 - ns tOFF - - 132 ns - 9.4 11.3 nC - 5.2 6.2 nC Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 30V, ID = 8A VGS = 4.5V, RGS = 32Ω (Figures 15, 21, 22) SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time VDD = 30V, ID = 13A VGS = 10V, RGS = 32Ω (Figures 16, 21, 22) GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge VDD = 30V, ID = 8A, Ig(REF) = 1.0mA (Figures 14, 19, 20) - 0.36 0.43 nC Gate to Source Gate Charge Qgs - 1.2 - nC Reverse Transfer Capacitance Qgd - 2.5 - nC - 350 - pF - 105 - pF - 23 - pF MIN TYP MAX UNITS CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage ISD =8A - - 1.25 V ISD = 3A - - 1.0 V trr ISD = 8A, dISD/dt = 100A/µs - - 66 ns QRR ISD = 8A, dISD/dt = 100A/µs - - 159 nC VSD Reverse Recovery Time Reverse Recovered Charge 2 TEST CONDITIONS HUF76407D3, HUF76407D3S Typical Performance Curves 15 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 VGS = 10V 10 VGS = 4.5V 5 0.2 0 0 0 25 50 75 100 125 150 175 25 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 200 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 175 - TC I = I25 150 VGS = 5V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 3 10-1 100 101 HUF76407D3, HUF76407D3S Typical Performance Curves (Continued) 100 100µs 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 1ms 10ms SINGLE PULSE TJ = MAX RATED TC = 25oC STARTING TJ = 25oC 10 STARTING TJ = 150oC 0.1 1 1 10 100 200 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 15 15 ID, DRAIN CURRENT (A) 12 ID, DRAIN CURRENT (A) VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 9 TJ = 25oC 6 3 TJ = 175oC VGS = 5V 12 9 VGS = 3.5V 6 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3 TJ = -55oC 0 3 4 5 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS 4 FIGURE 8. SATURATION CHARACTERISTICS 150 2.5 ID = 3A ID = 12A ID = 5A PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) VGS = 3V Tc = 25oC 0 2 VGS = 4V 120 90 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID = 12A 0.5 60 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 HUF76407D3, HUF76407D3S Typical Performance Curves (Continued) 1.2 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250µA 1.0 0.8 1.1 1.0 0.9 0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) -80 200 FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 VGS , GATE TO SOURCE VOLTAGE (V) 1000 CISS = CGS + CGD C, CAPACITANCE (pF) ID = 250µA COSS ≅ CDS + CGD 100 VGS = 0V, f = 1MHz CRSS = CGD 8 6 4 2 0 60 1.0 10 VDS , DRAIN TO SOURCE VOLTAGE (V) WAVEFORMS IN DESCENDING ORDER: ID = 12A ID = 5A ID = 3A 0 10 0.1 VDD = 30V 2 4 6 Qg, GATE CHARGE (nC) 8 10 NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 150 80 VGS = 10V, VDD = 30V, ID = 12A tr SWITCHING TIME (ns) SWITCHING TIME (ns) VGS = 4.5V, VDD = 30V, ID = 6A 100 tf 50 td(OFF) 60 40 tf 20 tr td(OFF) td(ON) td(ON) 0 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE 5 50 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 16. SWITCHING TIME vs GATE RESISTANCE 50 HUF76407D3, HUF76407D3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD VGS = 5V VGS DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 21. SWITCHING TIME TEST CIRCUIT 6 10% 50% 50% PULSE WIDTH FIGURE 22. SWITCHING TIME WAVEFORM HUF76407D3, HUF76407D3S PSPICE Electrical Model .SUBCKT HUF76407 2 1 3 ; rev 28June 1999 CA 12 8 3.9e-9 CB 15 14 4.9e-9 CIN 6 8 3.25e-10 LDRAIN DPLCAP DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DRAIN 2 5 10 RLDRAIN RSLC1 51 + RSLC2 5 51 EBREAK 11 7 17 18 67.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 DBREAK ESLC 11 - RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE IT 8 17 1 GATE 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.42e-9 LSOURCE 3 7 2.57e-9 + 17 EBREAK 18 50 EVTEMP RGATE + 18 22 9 20 21 - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RSOURCE RLSOURCE S2A S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.7e-2 RGATE 9 20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 54.2 RLSOURCE 3 7 25.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.50e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBODY 14 13 13 8 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 - - IT 14 + + EGS 19 VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))} .MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6) .MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81) .MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4 VOFF= -2.5) VON = -2.5 VOFF= -4) VON = -0.5 VOFF= 0) VON = 0 VOFF= -0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 7 HUF76407D3, HUF76407D3S SABER Electrical Model REV 28 June 1999 template huf76407 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.75e-13, cjo = 5.9e-10, tt = 5.45e-8, n=1.03, m = 0.6) d..model dbreakmod = () d..model dplcapmod = (cjo = 3.21e-10, is = 1e-30, m = 0.81 ) m..model mmedmod = (type=_n, vto = 2.02, kp = .83, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.39, kp = 14, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.78, kp = 0.02, is = 1e-30, tox = 1) DPLCAP sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -2.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -4) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5) LDRAIN DRAIN 2 5 RSLC1 51 RLDRAIN RDBREAK RSLC2 c.ca n12 n8 = 3.9e-10 c.cb n15 n14 = 4.9e-10 c.cin n6 n8 = 3.25e-10 72 ISCL EVTHRES + 19 8 + LGATE i.it n8 n17 = 1 GATE 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 5.42e-9 l.lsource n3 n7 = 2.57e-9 RDRAIN 6 8 ESG EVTEMP RGATE + 18 22 9 20 21 DBODY EBREAK + 17 18 MSTRO - 8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u LSOURCE 7 RSOURCE RLSOURCE S1A 12 S2A 13 8 S1B CA RBREAK 15 14 13 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/30))** 3)) } } - IT 14 + + spe.ebreak n11 n7 n17 n18 = 67.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 8 MWEAK MMED CIN 71 11 16 6 RLGATE res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0 res.rdbody n71 n5 = 1.75e-2, tc1 = 1e-4, tc2 = 5e-6 res.rdbreak n72 n5 = 6.50e-1, tc1 = 1.25e-4, tc2 = 1.34e-6 res.rdrain n50 n16 = 3.7e-2, tc1 = 1.23e-2, tc2 = 2.58e-5 res.rgate n9 n20 = 3.37 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 54.2 res.rlsource n3 n7 = 25.7 res.rslc1 n5 n51 = 1e-6, tc1 = 0, tc2 =0 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.50e-2, tc1 = 1e-3, tc2 =0 res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1.0e-7 res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6 DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod RDBODY VBAT 5 8 EDS - + 8 22 RVTHRES SOURCE 3 HUF76407D3, HUF76407D3S SPICE Thermal Model th JUNCTION REV 28June 1999 HUF76407T CTHERM1 th 6 4.5e-4 CTHERM2 6 5 2.5e-3 CTHERM3 5 4 1.9e-3 CTHERM4 4 3 2.6e-3 CTHERM5 3 2 5.5e-3 CTHERM6 2 tl 1.8e-2 RTHERM1 RTHERM1 th 6 3.1e-2 RTHERM2 6 5 15.1e-2 RTHERM3 5 4 4.2e-1 RTHERM4 4 3 8.4e-1 RTHERM5 3 2 8.7e-1 RTHERM6 2 tl 1.5 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF76407T 4 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.5e-4 ctherm.ctherm2 6 5 = 2.5e-3 ctherm.ctherm3 5 4 = 1.9e-3 ctherm.ctherm4 4 3 = 2.6e-3 ctherm.ctherm5 3 2 = 5.5e-3 ctherm.ctherm6 2 tl = 1.8e-2 RTHERM4 CTHERM4 3 RTHERM5 rtherm.rtherm1 th 6 = 3.1e-2 rtherm.rtherm2 6 5 = 15.1e-2 rtherm.rtherm3 5 4 = 4.2e-1 rtherm.rtherm4 4 3 = 8.4e-1 rtherm.rtherm5 3 2 = 8.7e-1 rtherm.rtherm6 2 tl = 1.5 } CTHERM5 2 RTHERM6 CTHERM6 tl CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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