NCP1910 High Performance Combo Controller for ATX Power Supplies Housed in a SO−24WB package, the NCP1910 combines a state−of−the−art circuitry aimed to powering next generation of ATX or flat TVs converters. With a 65 kHz Continuous Conduction Mode Power Factor Controller and a LLC controller hosting a high−voltage driver, the NCP1910 is ready to power 85+ types of offline power supplies. To satisfy stringent efficiency considerations, the PFC circuit implements an adjustable frequency fold back to reduce switching losses as the load is going light. To cope with all the signal sequencing required by the ATX and flat TVs specifications, the controller includes several dedicated pins enabling handshake between the secondary and the primary sides. These signals include a power−good line but also a control pin which turns the controller on and off via an opto coupler. Safety−wise, a second OVP input offers the necessary redundancy in case the main feedback network would drift away. Finally, a fast fault input immediately reacts in presence of an over current condition by triggering an auto−recovery soft−start sequence. • • • • • • • • SO−24WB Less Pin 21 DW SUFFIX CASE 752AB MARKING DIAGRAM NCP1910XXX AWLYYWWG 1 XXXXX A WL YY WW G Features • • • • http://onsemi.com = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Fixed−Frequency 65 kHz CCM Power Factor Controller Average Current−Mode Control for Low Line Distortion Dynamic Response Enhancer Reduces Bulk Undershoot ORDERING INFORMATION See detailed ordering and shipping information in the package Independent Over Voltage Protection Sensing Pin with Latch−off dimensions section on page 36 of this data sheet. Capability Adjustable Frequency Fold Back Improves Light Load Efficiency Adjustable Line Brown−out Protection with 50 ms • on/off Control Pin for Secondary−Based Remote Delay to Help Meeting Hold−up Time Specifications Control Programmable Over current Threshold Leads to an • On−Board 5 V Reference Voltage for Precise Optimized Sensing Resistor Thresholds/Hysteresis Adjustments ±1 A peak Current Drive Capability • Power Good Output Management Signal LLC Controller Operates from 25 kHz to 500 kHz • A Version with Dual Ground Pinout (No Skip), B Version with Single Ground and Skip Operation for On Board 600 V High−Voltage Drivers the LLC Controller 1 A/0.5 A Sink/Source Capability • 20 V Operation Minimum Frequency Precision Down to ±3% Over • These are Pb−Free Devices Temperature Range • Internally Fixed Dead−Time Value of 300 ns • Adjustable Soft−Start Sequence • Fast Fault Input with Soft−Start Trigger for Immediate Typical Applications • Multi Output ATX Power Supplies (A version) • Flat TVs Power Supplies (B version) Auto−Recovery Protection © Semiconductor Components Industries, LLC, 2012 December, 2012 − Rev. 1 1 Publication Order Number: NCP1910/D NCP1910 SS Rt PG out ON/OFF BO adj. Vref PG adj. OVP2 FB VCTRL VM LBO 1 24 Vboot MU Bridge ML VCC DRV GND/PGND Skip/AGND CS/FF CS Fold Figure 1. Pin Connections PIN DESCRIPTION Pin N5 Pin Name Function Pin Description 1 SS Soft−start 2 Rt The LLC feedback pin A resistive arrangement sets the maximum and minimum switching frequencies with opto coupler−based feedback capabilities. 3 PG out The open−collector power good signal This pin is low when Vbulk is ok, opens when Vbulk passes below a level adjusted by PGadj pin. 4 on/off Remote control 5 BO adj. Brown−out adjustment This pin sets the on and off levels for the PFC powering the LLC converter 6 Vref The 5 V reference pin This pin delivers a stable voltage for threshold adjustments 7 PG adj. The power good trip level From the Vref pin, a dc level sets the trip point for the PFC bulk voltage at which the PG out signal is down. 8 OVP2 Redundant OVP A fully latched OVP monitoring the PFC bulk independently from FB pin. 9 FB PFC feedback 10 VCTRL PFC Error amplifier output 11 VM PFC current amplifier output 12 LBO PFC line input voltage sensing 13 Fold PFC fold back 14 CS PFC current sense 15 CS/FF Fast−fault input When pulled above 1 V, the LLC stops and re−starts via a full soft−start sequence. 16 Skip/AGND Skip (B)/AGND (A) This pin is either used as the analog GND for the signal circuit (A) or for skip operation (B). 17 GND/PGND GND (B)/PGND (A) The controller ground for the driving loop (A) or the lump ground pin for all circuits (B) 18 DRV PFC drive signal 19 VCC The controller supply The power supply pin for the controller, 20 V max. 20 ML Lower−side MOSFET Drive signal for the lower side half−bridge MOSFET 22 Bridge Half−bridge 23 MU Upper−side MOSFET 24 Vboot Bootstrapped Vcc A capacitor to ground sets the LLC soft−start duration When pulled low, the circuit operates: the PFC starts first and once FB is in regulation, the LLC is authorized to work. When left open, the controller is in idle mode. Monitors the boost bulk voltage and regulates it. It also serves as a quick auto−recovery OVP PFC error amplifier compensation pin A resistor to ground sets the maximum power level Line feed forward and PFC brown−out This pin selects the power level at which the frequency starts to reduce gradually. This pin senses the inductor current and also programs the maximum sense voltage excursion The driving signal to the PFC power MOSFET This pin connects to the LLC half−bridge Drive signal for the upper side half−bridge MOSFET The bootstrapped VCC for the floating driver http://onsemi.com 2 3 Input Line V32 V33 D7 D3 D8 D4 http://onsemi.com (*) (*) R20 10k X3 R19 10 Q1 D10 D2 C1 FB U2A Bulk C18 1n R12 R22 on/off Power Good U3A C9 1u R13 R15 BO level C16 0.1u R21 Vref R5 3.5M C17 1n 0.1u C6 Vref C8 R23 0.22u 120k R25 24k PG adj. R14 R6 C2 R1 3.5M R32 3.6k R24 24k 22 3 19 12 R27 39k C11 1n R33 1.2k 13 R34 8.4k 14 16 15 9 10 11 17 18 8 7 6 5 20 23 4 24 1 C10 0.1u U100 2 R7 2.2M R3 1.5M R26 24k R4 2.2M R2 1.5M D5 Vcc C12 C3 R28 C13 Over Current 12 V aux. R8 R16 R17 D11 R9 M2 M1 D12 C15 R29 L2 T1 . . C14 . D9 D6 C4 Figure 2. Typical Application Schematic in A Version R10 U1 U2B *It is recommended to separate the traces of power ground and analog ground. The power ground (pin 17) for driving loop (PFC DRV and LLC ML) is connected to the PFC MOSFET directly. The analog ground for adjustment components is routed together first and then connected to the analog ground pin (pin 16) and the PFC sense resistor directly. R35 300 R31 0.1 C5 L1 D1 C7 R18 R30 R11 Vout X2 PAD2 NCP1910 4 Input Line V32 V33 D7 D3 http://onsemi.com R35 300 R31 0.1 C5 (*) (*) R20 10k X3 Q1 D10 D2 R19 10 FB U2A C1 Bulk R36 C19 C18 1n R12 on/off R22 Power Good U3A C9 1u R13 R15 BO level C16 0.1u R21 Vref C8 R23 0.22u 120k R25 24k PG adj. R5 3.5M C17 1n C6 0.1u R14 Vref R6 C2 R1 3.5M R32 3.6k R24 24k R4 2.2M R2 1.5M R26 24k 15 C10 0.1u 12 R27 39k 13 14 10 11 16 17 18 19 20 9 8 7 6 5 21 4 23 24 22 U100 3 2 1 R7 2.2M R3 1.5M C11 1n R33 1.2k R34 8.4k skip D5 Vcc C12 C3 R28 C13 Over Current 12 V aux. R8 R16 R9 D11 R17 M2 M1 D12 C15 R29 L2 C14 T1 . . . D9 D6 C4 U1 U2B R10 C7 R18 Figure 3. Typical Application Schematic in B Version *It is recommended to separate the traces of power ground and analog ground. The analog ground traces for adjustment components are routed together first and then connected to the ground pin (pin 17). The power ground for driving loop (PFC DRV and LLC ML) is connected from ground pin (pin 17) to the PFC sense resistor directly and as short as possible. D8 D4 L1 D1 R30 R11 X2 PAD2 Vout NCP1910 NCP1910 Grand Reset PFC_BO 107% Vpref + “1” OVP2, “0” = ok Latched adjustable OVP2 − PFC_OVP2 latched VOVP2 PFC_OVP Auto−recovery internal OVP + “1” = UVP, “0” ok Vctrl PFC_UVP VDD − + − Grand Reset + FB 8% Vpref − Vctrl(min) − 0.1 V PFC_BO IVLD PFC_OPL Q Q 1 sec delay PFCflag − RFB pull down VOVP VUVP PFC_abnormal latched S Vctrl(max) “1” OVP, “0” = ok + + 105% Vpref R − OVP2 20 us filter PFC_BO Latch Grand Reset If PFC issues an abnormal situation, then latch off PFC_OK Dynamic Response Enhancer “1” = below 5% reg “0” ok − S Grand Reset PFC_BO Closed if “1” − OTA PFC drive signal − “1” = FB > Vpref + Vfold “1” open “0” close Vfold(max) Ict(fold) Grand Reset PFC_BO VCTRL VLBO “1” BO NOTOK, Vctrl(min) “0” BOK PFC_BO BO delay VLBOT + − LBO S Q Q S R ILBO Q Q R PFC_OK A Latch Onoff UVLO TSD PFC_SKIP PFC_OL PFC_OVP PFC_BO VLBO^2 B VDD Multiplier − ICt(min) ICt A/B B ICS x VLBO^2 VLBO2 4(Vctrl * Vctrl(min)) + ICS ICS K1 Vctrl−Vctrl(min) Vdd − B A Vpref SUM 2 K2 CS + VLBO^2 ICS foldback ICS PFC_OK Vctrl + Vpref Q Q + VLD 95% Vpref R PFC_SKIP (0.6 V clamp voltage is activated.) A ICS x VLBO > 275 uA + “1” = OPL − ICS > 200 uA + − “0” / “1” Vpref / 10%Vpref PFC_OPL Oscillator section PFC_OL “1” = OCP PFC_OCP VM Vcc DRV Figure 4. Internal PFC Block Diagram http://onsemi.com 5 The “PFC_OK” toggles high when: − VLD is low − PFC issues a driving pulse The “PFC_OK” toggles low when: − Vctrl stays out of window [Vctrl,min to Vctrl,max] > 1 sec − at this point, the latch is reset and the “PFC_OK” output goes low. NCP1910 Vrt Vboot Q S D + Q Clk Q - Rt S CLK R QN B Mupper A R UVLO Hi side Level shifter Latch Vref Vref Bridge Pulse Trigger Latch Grand Reset Dead time B Vcc UVLO Grand Reset Vdd Vcc management A BO adj "1" BONOT OK + - Mlower delay LLC_BO tBOK tBONOTOK Prop. delay matching PFC_FB GND_LLC PFC_OK "1" is ok "0" notok "1" PGNOT OK "1" enables LLC "0" LLC is locked + PG adj Skip: B version only LLC_BO Skip/GND_PFC + LLC_PG 20 ms delay tdel1 Grand Reset R Vskip LLC_BO PG out R 5 ms delay tdel2 GND Grand Reset Grand Reset "1" after reset "0" when PG out drops after 5 ms PFC_OVP2 SS + S - S Q Q Q Latch Q S VCS2 R CS/FF + Q R Grand Reset Q PFC_BO R LLC_PG - Grand Reset VCS1 + SS_RST Vdd Rpull up on_off UVLO on/off "1" controller is off "0" controller is on Grand Reset PFC_UVP on/off Onoff Thermal Shut Down TSD "1" TSD is on "0" TSD is off TSD Figure 5. Internal LLC Block Diagram http://onsemi.com 6 NCP1910 MAXIMUM RATINGS TABLE Symbol VBridge Rating Value Unit −1 to 600 V −0.3 to 20 V High side output voltage, pin 23 VBRIDGE − 0.3 to VBOOT + 0.3 V Low side output voltage, pin 18, 20 −0.3 to VCC + 0.3 V Allowable output slew rate on the Bridge pin, pin 22 50 V/ns Power Supply voltage, pin 19 20 V −0.3 to 10 V Continuous High Voltage bridge pin, pin 22 VBOOT–VBridge Floating supply voltage, pin 24−22 VMU, VDRV VML dVBridge/dt VCC Pin voltage, all pins (except pin 2, 6, 18 − 24, GND) RθJA Thermal Resistance Junction−to−Air 50 mm2, 1 oz 650 mm2, 1 oz Storage Temperature Range −60 to + 150 °C 2 kV 200 V ESD Capability, Human Body Model (All pins except VCC and HV) ESD Capability, Machine Model VCC °C/W 80 65 Power Supply voltage, pin 19 20 V Pin voltage, all pins (except pin 2, 6, 18 ~ 24, GND) −0.3 to 10 V VRt Rt pin voltage −0.3 to 5 V Vref_out Vref pin voltage −0.3 to 7 V 0.5 mA 5 mA IMAX Pin current on pin 10, 12, and 13 IPGout Pin current on pin 3 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model 200 V per JEDEC Standard JESD22−A115−A 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Rating Pin Min Typ Max Unit VCC(on) Turn−on threshold level, VCC going up 19 9.4 10.4 11.4 V VCC(min) Minimum operating voltage after turn−on 19 8 9 10 V VCC(Hys) Hysteresis between VCC(on) and VCC(min) 19 1.2 − − V VBoot(on) Startup voltage on the floating section 24,22 7.8 8.8 9.8 V VBoot(min) Cutoff voltage on the floating section Symbol COMMON TO BOTH CONTROLLERS SUPPLY SECTION 24,22 7 8 9 V Startup current, VCC < VCC(on) 19 − − 100 mA ICC1 PFC consumption alone, DRV pin unloaded, on/off pin grounded, LLC off (PFC is 65 kHz) 19 − 5.1 6.4 mA ICC2 PFC consumption, DRV pin loaded by 1 nF, on/off pin grounded, LLC off (PFC is 65 kHz) 19 − 5.9 7.4 mA Istartup 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 7 NCP1910 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit COMMON TO BOTH CONTROLLERS SUPPLY SECTION ICC4 IC consumption, both PFC and LLC loaded in no load conditions (PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz)) 19 − 5.9 7.2 mA ICC5 IC consumption, both PFC and LLC loaded 1 nF load conditions (PFC is 65 kHz and Rt = 70 kW (LLC is 25 kHz)) 19 − 6.9 8.6 mA ICC6 IC consumption in fault mode from Vboot (drivers disabled, Vboot > Vboot(min)) 19 − 64 300 mA ICC7 IC consumption in OFF mode from VCC (on/off pin is open) 19 − − 950 mA REFERENCE VOLTAGE Vref−out Reference voltage for external threshold setting @ Iout = 5 mA 6 4.75 5 5.25 V Vref−out Reference voltage for external threshold setting @ Iout = 5 mA – TJ = 25°C 6 4.9 5 5.1 V VrefLineReg Vcc rejection capability, Iout = 5 mA − DVCC = 1 V – TJ = 25°C 6 − 0.01 5 mV VrefLoadReg Reference variation with load changes, 1 mA < Iref < 5 mA – TJ = 25°C 6 − 1.6 7 mV Maximum output current capability 6 5 − − mA Iref−out NOTE: Maximum capacitance directly connected to VREF pin must be under 100 nF. DELAY tDEL1 Turn−on LLC delay after PFC OK signal is asserted − 10 20 30 ms tDEL2 Turn−off LLC after power good pin goes low (Note 3) − 2 5 8 ms on/off pin pull−up resistor 4 − 5 − kW ton/off Propagation delay from on to off (ML & MU are off) (Note 4) 4 − − 1 ms Von Low level input voltage on on/off pin (NCP1910 is enabled) 4 − − 1 V Voff High level input voltage on on/off pin (NCP1910 is disabled) 4 3 − − V Vop Open voltage on on/off pin 4 − 7 − V IPG Maximum Power good pin sink current capability 3 5 − − mA VPG Power good saturation voltage for IPG = 5 mA 3 − − 350 mV Input bias current, PGadj pin 7 − 10 − nA PG comparator hysteresis 7 − 100 − mV Temperature shutdown (Note 4) − 140 − − °C Temperature Hysteresis Shutdown − − 30 − °C PROTECTIONS RPull−up IPGadj VPGadjH TSD TSDhyste POWER FACTOR CORRECTION GATE DRIVE SECTION RPOH Source Resistance @ IDRV = −100 mA 18 − 9 20 W RPOL Sink Resistance @ IDRV = 100 mA 18 − 6.6 18 W tPr Gate Drive Voltage Rise Time from 1.5 V to 10.5 V (CL = 1 nF) 18 − 60 − ns tPf Gate Drive Voltage Fall Time from 10.5 V to 1.5 V (CL = 1 nF) 18 − 40 − ns 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 8 NCP1910 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit PFC Voltage reference − 2.425 2.5 2.575 V IEA Error Amplifier Current Capability 10 − $30 − mA GEA Error Amplifier Gain − 100 200 300 mS Bias Current @ VFB = VPREF 9 0 − 0.3 mA Maximum Control Voltage @ VFB = 2 V Minimum Control Voltage @ VFB = 3 V DVCTRL = VCTRL(max)−VCTRL(min) 10 10 10 − − 2.7 3.6 0.6 3 − − 3.3 VOUTL / VPREF Ratio (VOUT Low Detect Threshold / VPREF) (Note 4) − 94 95 96 % HOUTL / VPREF Ratio (VOUT Low Detect Hysteresis / VPREF) − − 0.5 − % Source Current when (VOUT Low Detect) is activated 10 190 230 260 mA Current Sense Pin Offset Voltage, (ICS = 100 mA) 14 − 10 − mV Over−Current Protection Threshold 14 185 200 215 mA ICSx VLBO Over Power Limitation Threshold − 215 275 335 mVA ICS(OPL1) ICS(OPL2) Over−Power Current Threshold (VLBO = 1.8 V, VM = 0 V) Over−Power Current Threshold (VLBO = 3.6 V, VM = 0 V) − 119 56 153 75 187 99 mA PFC Switching Frequency 18 58 65 72 kHz Minimum Switching Frequency (Vfold = 1.5 V, VCTRL = VCTRL(min) + 0.1 V) 18 34 39 43 kHz DCPmax Maximum PFC Duty Cycle 18 − 97 − % DCPmin Minimum PFC Duty Cycle 18 − − 0 % VCTRL pin voltage to start frequency foldback (Vfold = 1.5 V) 10 1.8 2 2.2 V VCTRL pin voltage as frequency foldback reducing to the minimum (FPSW = FPSW(fold), Vfold = 1.5 V) 10 1.4 1.6 1.8 V Maximum internal fold voltage (Note 4) − 1.97 2 2.03 V POWER FACTOR CORRECTION REGULATION BLOCK VPREF IB VCTRL VCTRL(max) VCTRL(min) DVCTRL IVLD + IEA V CURRENT SENSE VS ICS(OCP) POWER LIMIT PULSE WIDTH MODULATION FPSW FPSW(fold) VCTRL(fold) VCTRL(foldend) Vfold(max) LINE BROWN−OUT DETECTION VLBOT Line Brown−Out Voltage Threshold 12 0.96 1.00 1.04 V ILBOH Line Brown−Out Hysteresis Current Source 12 6 7 8 mA Line Brown−Out Blanking Time − 25 50 75 ms tLBO(window) tLBO(blank) Line Brown−Out Monitoring Window (Note 4) − 25 50 75 ms VLBO(clamp) LBO Pin clamped voltage if VBO < VLBOT during tLBO(BLANK) (ILBO = 100 mA) 12 − 980 − mV Hysteresis (VLBOT – VLBO(clamp)) (Note 4) 12 10 35 60 mV ILBO(clamp) Current Capability of LBO 12 100 − − mA VLBO(PNP) LBO pin voltage when clamped by the PNP Transistor (ILBO = 100 mA) 12 0.4 0.7 0.9 V VLBOH 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 9 NCP1910 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit Pull Down VLBO Threshold 12 1.8 2 2.2 V Pull Down VLBO Time Limitation − 4.5 5 6.1 ms Time Delay to Confirm that VCTRL is the maximum to Pull down VLBO − 2.5 5 7.5 ms Pull Down VLBO Blanking Time − 55 77 90 ms 11 46 58 72 mA 11 15 19 24.5 POWER FACTOR CORRECTION LINE BROWN−OUT DETECTION VLBO(PD) tLBO(Pdlimit) tPFCflag tLBO(Pdblank) CURRENT MODULATION IM1 IM2 Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 3.6 V, ICS = 50 mA) Multiplier Output Current (VCTRL =VCTRL(max) – 0.2 V , VLBO = 1.2 V, ICS = 150 mA) OVER−VOLTAGE PROTECTION VOVP1 Internal Auto Recovery Over Voltage Threshold 9 2.536 2.615 2.694 V VOVP1H Hysteresis of Internal Auto Recovery Over Voltage Threshold (Note 4) 9 − 44 60 mV 9, 18 − 500 − ns tOVP1 Propagation Delay (VFB = 108% VPREF) to Drive Low VOVP2 External Latched Over Voltage Threshold 8 2.595 2.675 2.755 V KOVPH The difference between VOVP2 and VOVP1 over VPREF ((VOVP2 − VOVP1)/VPREF) − − 2 − % External Latched OVP Integrating Filter Time Constant − − 20 − ms Input bias current, OVP2 8 − 10 − nA VUVP(on)/VPREF UVP Activate Threshold Ratio 9 4 8 12 % VUVP(off)/VPREF UVP Deactivate Threshold Ratio 9 6 12 18 % 9 − 4 − % 9 − 18 − 7 − ms − 1 1.5 2.1 sec Minimum switching frequency, Rt = 70 kW on Rt pin 2 24.25 25 25.75 kHz switching frequency, DTL = 300 ns, Rt = 7 kW on Rt pin 2 208 245 282 kHz tDELOVP2 Ib,OVP2 UNDER−VOLTAGE PROTECTION VUVP(H) tUVP UVP Lockout Hysteresis Propagation Delay (VFB < 8 % VPREF) to Drive Low PFC ABNORMAL tPFCabnormal PFC Abnormal Delay Time (VCTRL = VCTRL(max) or VCTRL = VCTRL(min) – 0.1 V) LLC CONTROL SECTION OSCILLATOR FLsw,min FLsw FLsw,max 2 424 500 575 kHz 23, 20 48 50 52 % Reference voltage for oscillator charging current generation 2 3.33 3.5 3.67 V Discharge switch resistance 1 − 70 − W Soft−start reset voltage 1 − 200 − mV Skip cycle threshold, B version only 16 350 400 450 mV Hysteresis level on skip cycle comparator, B version only 16 − 50 − mV Maximum switching frequency, DTL = 300 ns, Rt = 3.5 kW on Rt pin DCL Operating Duty−Cycle symmetry VrefRt RSS SSRST VSkip Vskip,hyste 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 10 NCP1910 ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit − ns LLC CONTROL SECTION DRIVE OUTPUT TLr Output voltage rise−time @ CL = 1 nF, 10−90% of output signal 23, 20 − 40 TLf Output voltage fall−time @ CL = 1 nF, 10−90% of output signal 23, 20 − 20 − ns RLOH Source resistance 23, 20 − 12 26 W RLOL Sink resistance 23, 20 − 5 11 W DTL Dead time, measured between 50% of the rise and fall edge 23, 20 268 327 386 ns 22, 23, 24 − − 5 mA Input bias current, BOadj pin 5 − 15 − nA BO comparator hysteresis 5 − 100 − mV tBOK BO comparator Integrating Filter Time Constant from High to Low 5 − 150 − ms tBONOTOK BO comparator Integrating Filter Time Constant from Low to High 5 − 20 − ms VCS1 Current−sense pin level that resets the soft−start capacitor 15 0.95 1 1.05 V VCS2 Current−sense pin level that permanently latches off the circuit 15 1.42 1.5 1.58 V tCS Propagation delay from VCS1/2 activation to respective action 15 − − 500 ns IHV,leak Leakage current on high voltage pins to GND (600 Vdc) PROTECTIONS IBOadj VBOadjH 3. In normal operation, when the power supply is un−plugged, the bulk voltage goes down. At a first crossed level, the PG pin opens. Later, when the bulk crosses a second level, the LLC turns off. There is no timing link between these events, except the bulk capacitor discharge slope. However, if for an unknown reason the PFC is disabled (fault, short−circuit), the PG pin immediately opens and if sufficient voltage is still present on the bulk (e.g. in high line condition), the LLC will be disabled after a typical time of 5 ms. 4. Guaranteed by design. http://onsemi.com 11 NCP1910 TYPICAL CHARACTERISTICS 10 10 9.5 VCC(min) 9 8.5 8 −50 Istartup (mA) Vboot(on) AND Vboot(min) (V) VCC(on) 10.5 −25 0 25 50 75 100 9.5 Vboot(on) 9 8.5 Vboot(min) 8 7.5 7 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. VCC(on) and VCC(min) vs. Temperature Figure 7. Vboot(on) and Vboot(min) vs. Temperature 100 950 75 850 ICC7 (mA) VCC(on) AND VCC(min) (V) 11 50 750 650 25 0 −50 125 −25 0 25 50 75 100 550 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Istartup vs. Temperature Figure 9. ICC7 vs. Temperature 5.25 100 125 4.99 Vref−out @ 25°C (V) Vref−out (V) 5.15 5.05 4.95 4.989 4.988 4.85 4.75 −50 −25 0 25 50 75 100 4.987 125 0 1 2 3 4 5 TEMPERATURE (°C) TEMPERATURE (°C) Figure 10. Vref-out vs. Temperature Figure 11. Vref-out @ 255C vs. Iref-out http://onsemi.com 12 6 NCP1910 TYPICAL CHARACTERISTICS 10 Voff 2.5 RPOH AND RPOL (W) Von AND Voff (V) 3 2 Von 1.5 1 −50 −25 0 25 50 75 TEMPERATURE (°C) 100 8 RPOL 4 2 −50 125 0 75 100 125 −25 IEA(source) (mA) VOVP2 VOVP1 2.6 VPREF 2.5 −25 0 25 50 −30 −35 75 100 −40 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 14. VPREF, VOVP1, and VOVP2 vs. Temperature Figure 15. IEA(source) vs. Temperature 40 300 35 250 GEA (mS) IEA(sink) (mA) 50 −20 2.7 30 25 20 −50 25 Figure 13. RPOH and RPOL vs. Temperature 2.8 VPREF, VOVP1, AND VOVP2 (V) −25 TEMPERATURE (°C) Figure 12. Von and Voff vs. Temperature 2.4 −50 RPOH 6 200 150 −25 0 25 50 75 100 100 −50 125 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. IEA(sink) vs. Temperature Figure 17. GEA vs. Temperature http://onsemi.com 13 100 125 NCP1910 3.9 3.3 3.8 3.2 3.7 3.1 DVCTR (V) VCTR(max) (V) TYPICAL CHARACTERISTICS 3.6 3.5 2.9 2.8 3.4 3.3 −50 3 −25 0 25 50 75 100 2.7 −50 125 0 25 50 75 100 TEMPERATURE (°C) Figure 18. VCTRL(max) vs. Temperature Figure 19. DVCTRL vs. Temperature 260 215 250 210 ICS(OCP) (mA) IVLD + IEA (mA) 240 230 220 210 125 205 200 195 190 200 190 −50 −25 TEMPERATURE (°C) −25 0 25 50 75 100 185 −50 125 −25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. IVLD+IEA vs. Temperature Figure 21. ICS(OCP) vs. Temperature 190 125 95 180 85 ICS(OPL2) (mA) ICS(OPL1) (mA) 170 160 150 140 75 65 130 120 −50 −25 0 25 50 75 100 55 −50 125 TEMPERATURE (°C) −25 0 25 50 75 100 TEMPERATURE (°C) Figure 22. ICS(OPL1) vs. Temperature Figure 23. ICS(OPL2) vs. Temperature http://onsemi.com 14 125 NCP1910 TYPICAL CHARACTERISTICS 72 44 70 42 FPSW(fold) (kHz) FPSW (kHz) 68 66 64 62 40 38 36 60 58 −50 −25 0 25 50 75 100 34 −50 125 −25 0 50 75 100 125 Figure 25. FPSW(fold) vs. Temperature 1.04 8 1.02 7.5 ILBOH (mA) VLBOT (V) Figure 24. FPSW vs. Temperature 1 0.98 7 6.5 0.96 −50 −25 0 25 50 75 100 125 6 −50 −25 0 TEMPERATURE (°C) 25 50 75 100 125 100 125 TEMPERATURE (°C) Figure 26. VLBOT vs. Temperature Figure 27. ILBOH vs. Temperature 18 26 16 25.5 14 VUVP(off) / VPREF FLSW,min (kHz) VUV(on) / VPREF AND VUP(off) / VPREF (%) 25 TEMPERATURE (°C) TEMPERATURE (°C) 12 10 VUVP(on) / VPREF 8 25 24.5 6 4 −50 −25 0 25 50 75 100 125 24 −50 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 28. VUVP(on)/VPREF and VUVP(off)/VPREF vs. Temperature Figure 29. FLsw,min vs. Temperature http://onsemi.com 15 NCP1910 TYPICAL CHARACTERISTICS 280 525 270 500 FLSW,max (kHz) FLSW (kHz) 260 250 240 230 475 450 220 210 −50 −25 0 25 50 75 100 425 −50 125 −25 0 TEMPERATURE (°C) 50 75 100 125 Figure 31. FLsw,max vs. Temperature 3.7 300 3.6 250 SSRST (mV) VrefRT (V) Figure 30. FLsw vs. Temperature 3.5 3.4 3.3 −50 25 TEMPERATURE (°C) 200 150 −25 0 25 50 75 100 100 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 33. SSRST vs. Temperature Figure 32. VrefRt vs. Temperature 24 450 RLOH,ML AND RLOL,ML (W) 22 Vskip (mV) 425 400 375 20 18 RLOH,ML 16 14 12 10 8 RLOL,ML 6 4 350 −50 −25 0 25 50 75 TEMPERATURE (°C) 100 125 2 −50 Figure 34. Vskip vs. Temperature −25 0 25 50 75 TEMPERATURE (°C) 100 Figure 35. RLOH,ML and RLOL,ML vs. Temperature http://onsemi.com 16 125 NCP1910 TYPICAL CHARACTERISTICS 340 24 20 330 18 RLOH,MU 16 DTL (ns) RLOH,MU AND RLOL,MU (W) 22 14 12 10 8 310 RLOL,MU 6 320 4 2 −50 −25 0 25 50 75 100 300 −50 125 −25 0 TEMPERATURE (°C) Figure 36. RLOH,MU and RLOL,MU vs. Temperature 1.025 1.55 VCS2 (V) 1.6 VCS1 (V) 50 75 100 125 100 125 Figure 37. DTL vs. Temperature 1.05 1 0.975 1.5 1.45 −25 0 25 50 75 TEMPERATURE (°C) 100 125 1.4 −50 −25 Figure 38. VCS1 vs. Temperature 0 25 50 75 TEMPERATURE (°C) Figure 39. VCS2 vs. Temperature 140 120 100 tCS (ns) 0.95 −50 25 TEMPERATURE (°C) 80 60 40 20 −50 −25 0 25 50 75 TEMPERATURE (°C) Figure 40. tCS vs. Temperature http://onsemi.com 17 100 125 NCP1910 APPLICATION INFORMATION The NCP1910 represents a new generation of control circuit, associating two individual cores performing the functions of Continuous Conduction Mode (CCM) Power Factor Correction (PFC) and LLC resonant control. These cores interact together and implement handshake functions in normal operating conditions but also when a fault appears. Based on the ON Semiconductor proprietary high−voltage technology, the LLC section can drive the high−side MOSFET of the LLC half−bridge without the need of a gate−drive transformer. • Power Factor Correction • Compactness and Flexibility: the NCP1910 requires a • • • • minimum of external components to perform a CCM PFC operation. In particular, the circuit scheme simplifies the PFC stage design. In addition, the circuit offers some functions like the line brown−out detection or true power limiting capability that enable the optimization of the PFC design. Low Consumption and Shutdown Capability: the NCP1910 is optimized to consume a small current in all operation modes. The consumed current is particularly reduced during the start−up phase and in shutdown mode so that the power losses are minimized when the circuit is disabled. This feature helps meet stringent stand−by low power specifications. Grounding the Feed−back pin can force the circuit to enter standby but the on/off pin can also serve this purpose. Maximum Current Limit: the circuit permanently senses the inductor current and immediately turns off the power switch if it is higher than the set current limit. The NCP1910 also prevents any turn on of the power switch as long as the inductor current is not below its maximum permissible level. This feature protects the MOSFET from possible excessive stress that could result from the switching of a current higher than the one the power switch is dimensioned for. In particular, this scheme effectively protects the PFC stage during the start−up phase when large in−rush currents charge the bulk capacitor. Under−Voltage Protection for Open Loop Protection: the circuit detects when the feed−back voltage goes below than about 8% of the regulation level. In this case, the circuit turns off and its consumption drops to a very low value. This feature protects the PFC stage from starting operation in case of low ac line conditions or in case of a failure in the feed−back network (i.e. bad connection). In case the UVP circuitry is activated, the Power Good signal is disabled and the LLC circuit stops immediately. Fast Transient Response: given the low bandwidth of the regulation block, the output voltage of PFC stages may exhibit excessive over or under−shoots because of • • • • • • abrupt load or input voltage variations (e.g. at start up). If the bulk voltage is too far from the regulation level: ♦ Over−Voltage Protection: NCP1910 turns off the power switch as soon as Vbulk exceeds the OVP threshold (105% of the regulation level). This is an auto−recovery function. ♦ Dynamic Response Enhancer: NCP1910 drastically speeds up the regulation loop by its internal 200 mA current source, activated when the bulk voltage drops below 95% of its regulation level. Line Brown−Out Detection: the circuit detects low ac line conditions and disables the PFC stage in this case. This protection mainly protects the power switch from the excessive stress that could damage it in such conditions. Over−Power Limitation: the NCP1910 computes the maximum permissible current in dependence of the average input voltage measured by the brown−out block. It is the second OCP with a threshold that is line dependent. When the circuit detects an excessive power transfer, it resets the driver output immediately. Redundant Over−Voltage Protection: As a redundant safety feature, the NCP1910 offers a second latched OVP whose input is available on OVP2 pin. If the voltage on this pin is above the maximum allowable voltage, the PFC and the LCC are latched off. PFC Abnormal Protection: When PFC faces an abnormal situation so that the bulk voltage is under regulation longer than the allowable timing, the PFC and LLC are latched off. Frequency Foldback: in light output loading conditions, the user has the ability to program a point on the VCTRL pin where the oscillator frequency is gradually reduced. This helps to maintain an adequate efficiency on the PFC power stage alone. Soft−Start: to offer a clean start−up sequence and limit both the stress on the power MOSFET and the bulk voltage overshoot, a 30 mA current source charges the compensation network installed on VCTRL pin and makes VCTRL raise gradually. Output Stage Totem Pole: the NCP1910 incorporates a ±1.0 A gate driver to efficiently drive TO220 or TO247 power MOSFETs. LLC Controller • Wide frequency operation: the part can operate to a frequency up to 500 kHz by connecting a resistive network from Rt pin to ground. One resistor sets the maximum switching frequency whereas a second resistor set the minimum frequency. http://onsemi.com 18 NCP1910 • On board dead time: to eliminate the shoot−through • • • • on the half−bridge leg, a dead time is included in the controller (see DTL parameter). Soft−start: a dedicated pin discharges a capacitor to ground upon start−up to offer a smooth output voltage ramp up. The start−up frequency is the maximum set by the resistor connected between Rt pin and SS pin. The capacitor connected from Rt pin to ground fixes the soft start duration. In fault mode, when the voltage on CS/FF pin exceeds a typical value of 1 V, the soft−start pin is immediately discharged and a re−start at high frequency occurs. Skip cycle operation: to avoid any frequency runaway in light conditions but also to improve the standby power consumption, the NCP1910B welcomes a skip input (Skip pin) which permanently observes the opto−coupler collector. If this pin senses a low voltage, it cuts the LLC output pulses until the collector goes up again. The NCP1910A does not offer the skip capability and routes the analog ground on pin 16 instead. High−voltage drivers: capitalizing on ON Semiconductor technology, the LLC controller includes a high−voltage section allowing a direct connection to the high−voltage rail. The MOSFET leg can therefore be directly driven without using a gate−drive transformer. Fault protection: as explained in the above lines, the CS/FF pin combines a two−level protection circuit. If the level crosses the first level (1 V), the LLC converter immediately increases its switching frequency to the maximum set by the external resistive divider connected on Rt pin. This is an auto−recovery protection mode. In case the fault is more severe, the signal on the CS/FF pin crosses the second threshold (1.5 V) and latches off the whole combo controller. Reset occurs via an UVLO detection on VCC, a reset on the on/off pin or a brown−out detection on the PFC stage. This latter confirms that the user has unplugged and re−plugged the power supply. • • • is asserted. This delay is always reset when the combo is started from a Vcc ULVO, line brown−out condition or via the on/off pin. Power good signal: the power good signal (PG) is intended to instruct the downstream circuitry installed on the isolated secondary side that the combo is working. Once the PFC has started, an internal “PFC_OK” signal is asserted. 20 ms later, the PG pin is brought low. This signal can now disappear in two cases: the bulk voltage decreases to an abnormal level, programmed by a reference voltage imposed on PGadj pin. This level is usually above the LLC turn−off voltage, programmed by BOadj pin. Therefore, in a normal turn−off sequence, PG first drops and signals the secondary side that it must be prepared for shutdown. The second event that can drop the PG signal is when the PFC experiences a fault: broken feedback path, severe overload. In this case, the PG signal is immediately asserted high and a 5 ms timer starts. Once this timer is elapsed, the LLC converter can be safely halted. Latched event: in the event of a severe operating condition, the PFC can be latched (OVP2 pin) and/or the LLC controller also (CS/FF pin). In either case, the whole combo controller is locked and can only be reset via a VCC UVLO, line brown−out or a level transition on pin on/off. Thermal Shutdown: an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140°C typically. The circuit resumes operation once the temperature drops below about 110°C (30°C hysteresis). Principle of NCP1910 Scheme PFC Section A CCM PFC boost converter is shown in Figure 41. The input voltage is a rectified 50 Hz or 60 Hz sinusoidal signal. The MOSFET is switching at a high frequency (typically 65 kHz in NCP1910) so that the inductor current IL basically consists of high and low−frequency components. Filter capacitor Cin is an essential and very small value capacitor in order to eliminate the high−frequency component of the inductor IL. This filter capacitor cannot be too bulky because it can pollute the power factor by distorting the rectified sinusoidal input voltage. Combo Management • Start−up delay: the PFC start−up sequence often generates an output overshoot followed by damped oscillations. To make sure the PFC output voltage is fully stabilized before starting the LLC converter, a 20 ms delay is inserted after the internal PFC_ok signal http://onsemi.com 19 NCP1910 I in L Bulk voltage (Vbulk) IL V in C bulk C in R SENSE Figure 41. CCM PFC Boost Converter PFC Methodology Vin is the rectified input voltage, T is the switching period, ♦ t1 is the MOSFET on time, and ♦ t2 is the MOSFET off time. The input filter capacitor Cin and the front−ended EMI filter absorbs the high−frequency component of inductor current IL. It makes the input current Iin a low−frequency signal only of the inductor current. ♦ The NCP1910 uses a proprietary PFC methodology particularly designed for CCM operation. The PFC methodology is described in this section. ♦ I in + I L−50 (eq. 2) Where: Iin is the input AC current. IL is the inductor current. ♦ IL−50 supposes a 50 Hz operation. The suffix 50 means it is with a 50 Hz bandwidth of the original IL. From Equations 1 and 2, the input impedance Zin is formulated. ♦ ♦ Figure 42. Inductor Current in CCM As shown in Figure 42, the inductor current IL in a switching period T includes a charging phase for duration t1 and a discharging phase for duration t2. The voltage conversion ratio is obtained in Equation 1. V bulk V in + V in + t1 ) t2 t2 T * t1 T + T T * t1 Z in + (eq. 1) V in I in + T * t 1 V bulk T I L*50 (eq. 3) where: Zin is input impedance. Power factor is corrected when the input impedance Zin in Equation 3 is constant or varies slowly in the 50 or 60 Hz bandwidth. V bulk Where: ♦ Vbulk is the output voltage of PFC stage, http://onsemi.com 20 NCP1910 VPREF VPREF Figure 43. PFC Duty Modulation and Timing Diagram The PFC modulation and timing diagram is shown in Figure 43. The MOSFET on time t1 is generated by the intersection of reference voltage VPREF and ramp voltage Vramp. A relationship in Equation 4 is obtained. V ramp + V M ) I cht 1 C ramp + V PREF Z in + I ch + (eq. 4) V M + V PREF * t1 C rampV PREF C ramp T + V PREF (eq. 7) Figure 44. Multiplier Voltage Timing Diagram (eq. 5) T V PREF I L−50 Because VPREF and Vbulk are roughly constant versus time, the multiplier voltage VM is designed to be proportional to the IL−50 in order to have a constant Zin for PFC purpose. It is illustrated in Figure 44. Where: ♦ Vramp is the internal ramp voltage, the positive input of the PFC modulation comparator, ♦ VM is the multiplier voltage appearing on VM pin, ♦ Ich is the internal charging current, ♦ Cramp is the internal ramp capacitor, and ♦ VPREF is the internal reference voltage, the negative input of the PFC modulation comparator. Ich, Cramp, and VPREF also act as the ramp signal of switching frequency. Hence the charging current Ich is specially designed as in Equation 5. The multiplier voltage VM is therefore expressed in terms of t1 in Equation 6. C rampV PREF V M V bulk It can be seen in the timing diagram in Figure 43 that VM originally consists of a switching frequency ripple coming from the inductor current IL. The duty ratio can be inaccurately generated due to this ripple. This modulation is the so−called “peak current mode”. Hence, an external capacitor CM connected to the multiplier voltage VM pin is essential to bypass the high−frequency component of VM. The modulation becomes the so−called “average current mode” with a better accuracy for PFC. T * t1 T (eq. 6) From Equation 3 and Equation 6, the input impedance Zin is re−formulated in Equation 7. http://onsemi.com 21 NCP1910 R MI CSǒV LBOǓ 2 VM + VM ǒ 4 V CTRL * V CTRLǒminǓ Ǔ IM 11 CM RM PFC Duty Modulation Figure 45. The Multiplier Voltage Pin Configuration The multiplier voltage VM is generated according to Equation 8. VM + R MI CSǒV LBOǓ VCTRL is the control voltage signal, the output voltage of Operational Trans−conductance Amplifier (OTA), as described in Equation 17. ♦ VCTRL(min) is not only the minimum operating voltage of VCTRL but also the offset voltage for the PFC current modulation. RM directly limits the maximum input power capability. Also, due to the Vin2 feed−forward feature, where the VLBO is squared, the transfer function and the power delivery is independent from the ac line level. The relationship between VCTRL and power delivery will be depicted later on. ♦ 2 (eq. 8) 4ǒV CTRL * V CTRL(min)Ǔ Where: ♦ RM is the external multiplier resistor connected to VM pin, which is constant. ♦ VLBO is the input voltage signal appearing on the LBO pin, which is proportional to the rms input voltage, ♦ ICS is the sense current proportional to the inductor current IL as described in Equation 13. Line Brown−Out Protection Vin Ac line EMI Filter RSENSE LBO comp. RLBOU Cin LBO CLBO VLBOcomp VLBOT RLBOL PFC_BO S Vdd LBO Q R VLBO(clamp) tLBO(blank) reset reset tLBO(window) reset ILBOH Figure 46. The Line Brown−Out Configuration LBO pin voltage when a brown−out condition is detected. This is for hysteresis purpose as required by this function. In nominal operation, the voltage applied to LBO pin must be above the internal reference voltage, VLBOT (1 V typically). In this case, the output of the LBO comparator VLBOcomp is low. As shown in Figure 46, the Line Brown−Out pin (represented LBO pin) as receives a portion of the input voltage (Vin). As Vin is a rectified sinusoid, a capacitor must integrate the ac line ripple so that a voltage proportional to the average value of Vin is applied to the brown−out pin. The main function of the LBO block is to detect too low input voltage conditions. A 7 mA current source lowers the http://onsemi.com 22 NCP1910 Conversely, if VLBO goes below 1 V, VLBOcomp turns high and a 980 mV voltage source, VLBO(clamp), is connected to the LBO pin to maintain the pin level near 1 V. Then a 50 ms blanking delay, tLBO(blank), is activated during which no fault is detected. The main goal of the 50 ms lag is to help meet the hold−up requirements. In case of a short mains interruption, no fault is detected and hence, both PFC and LLC keep operating. In addition, LBO pin being kept at 980 mV, there is almost no extra delay between the line recovery and the occurrence of a proper voltage applied to LBO pin, that otherwise would exist because of the large capacitor typically placed between LBO pin and ground to filter the input voltage ripple. As a result, the NCP1910 effectively “blanks” any mains interruption that is shorter than 25 ms (minimum guaranteed value of the 50 ms timer). At the end of this blanking delay (tLBO(blank)), another timer is activated that sets a 50 ms window during which a fault can be detected. This is the role of the tLBO(window) in Figure 46: • If VLBOcomp is high during the second 50 ms delay (tLBO(window)), a line brown−out condition is confirmed and PFC_BO signal is asserted high. • If VLBOcomp remains low for the duration of the tLBO(window), no fault is detected. R LBOL V LBO + Ǹ2 V ac,rms @ R LBOU ) R LBOL R LBOU @ R LBOL * I LBOH R LBOU ) R LBOL If RLBOL << RLBOU, V LBO ] Ǹ2 V ac,rms (eq. 9) R LBOL R LBOU ) R LBOL * I LBOHR LBOL • After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the average voltage becomes <Vin> = (2/p) √2 Vac,rms, which decays 2/π of the peak value of rms input voltage. Hence, the average voltage applied to LBO pin is: <VLBO> = (2/p) √2 Vac,rms RLBOL/(RLBOU + RLBOL). And because of the ripple on the LBO pin, the minimum value of VLBO is around: V LBO + 2Ǹ 2 V ac,rms p R ǒ R LBOL LBOU ) R LBOL f LBO 1* (eq. 10) Ǔ 3f line Where: ♦ fLBO is the sensing network pole frequency. When the PFC_BO signal is high: • The PFC driver is disabled, and the VCTRL pin is grounded to recover operation with a soft−start when the fault has gone. • The VLBO(clamp) voltage source is removed from LBO pin. • The ILBOH current source (7 mA typically) is enabled that lowers the LBO pin voltage for hysteresis purpose. At startup, a pnp transistor ensures that the LBO pin voltage remains below when: VCC < UVLO or ON/OFF pin is released open or UVP or Thermal Shutdown. This is to guarantee that the circuit starts operation in the right state, which is “PFC_BO” high. When the NCP1910 is ready to work, the pnp transistor turns off and the circuit enables the ILBOH. Also, ILBOH is enabled whenever the part is in off mode, but at startup, ILBOH is disabled until VCC reaches VCC(on). f LBO + R LBOU ) R LBOL 2pR LBOUR LBOLC LBO ♦ fline is the line frequency. ♦ RLBOL is low side resistor of the dividing resistors between LBO pin and ground. ♦ RLBOU is upper side resistor of the dividing resistors between Vin and LBO pin. f LBO of Equation 10 enables to take into The term 1* 3f line account the LBO pin voltage ripple (first approximation). If as a rule of the thumb, we will assume that f line . f LBO + 10 Re−arranging the Equation 9 and 10, the network connected to LBO pin can be calculated with the following equations: ȡ 1 ȧ Ȣ1 * Line Brown−Out Network Calculation R LBOL + If the line brown−out network is connected to the voltage after bridge diode, the monitored voltage can be very different depending on the phase: • Before operation, the PFC stage is off and the input bridge acts as a peak detector. As a consequence, the input voltage is approximately flat and nearly equates the ac line amplitude: <Vin> = √2 Vac,rms, where Vac,rms is the rms voltage of the line. As depicted in previous section, the ILBOH turns on before PFC operates for the purpose of adjustable line brown−out hysteresis; hence, the average voltage applied to LBO pin is: f LBO 3f ^ ǒ http://onsemi.com 23 ȣ ȧ Ȥ V LBOT p V ac,on @ *1 @ 2 V ac,off I LBOH line (eq. 11) Ǔ V LBOT p V ac,on 1 @ @ *1 @ 0.967 2 V ac,off I LBOH R LBOU + Where: @ ǒ Ǹ2 @ V ac,on I LBOHR LBOL ) V LBOT Ǔ (eq. 12) * 1 R LBOL NCP1910 ♦ ♦ PFC Over−Power Limitation (OPL) Vac,on is the rms ac voltage to starts PFC operating. Vac,off the rms ac voltage for line brown−out detection. This is a second OCP with a threshold that is line dependent. Sense current ICS represents the inductor current IL and hence represents the input current approximately. Input voltage signal VLBO represents the rms input voltage. The product (ICS x VLBO) represents an approximated input power (IL x Vac). It is illustrated in Figure 48. PFC Current Sense IL RCS ICS CS + RSENSE IL Vin NCP1910 IL GND VCS − RSENSE Figure 47. PFC Current Sensing Configuration RCS The device senses the inductor current IL by the current sense scheme in Figure 47. The device maintains the voltage at CS pin to be zero voltage, i.e. VCS = 0 V, so that I CS + R SENSE R CS IL RLBOU R SENSE + R SENSE CLBO RLBOL Figure 48. PFC Over−Power Limitation Configuration When the product (ICS x VLBO) is greater than a permissible level 275 mVA, the device turns off the PFC driver so that the input power is limited. The OPL is automatically deactivated when the product (ICS x VLBO) is lower than the 275 mVA level. This 275 mVA level corresponds to the approximated input power (IL x Vac) to be smaller than the particular expression in Equation 15. I CSV LBO t 275 mVA PFC Over−Current Protection is reached when ICS is larger than IS(OCP) (200 mA typical). The offset voltage of the CS pin is typical 10 mV and it is neglected in the calculation. Hence, the maximum OCP inductor current threshold IL(OCP) is obtained in Equation 14. I LǒOCPǓ + OPL > 275 mVA? PFC Over−Current Protection (OCP) R CS Current mirror LBO (eq. 13) Where: ♦ RSENSE is the sense resistor to sense IL. ♦ RCS is the offset resistor between CS pin and RSENSE. This scheme has the advantage of the minimum number of components for current sensing. The sense current ICS represents the inductor current IL and will be used in the PFC duty modulation to generate the multiplier voltage VM, Over−Power Limitation (OPL), and Over−Current Protection. Equation 13 would insist in the fact that it provides the flexibility in the RSENSE choice and that it allows to detect in−rush currents. R CSI SǒOCPǓ CS ICS ǒ IL Ǔ ǒ R SENSE 2 Ǹ2 K LBO R CS p I L @ V ac t 200 mA (eq. 14) R CS @ p R SENSE @ K LBO @ V ac Ǔ (eq. 15) t 275 mVA @ 97 mVA Where When over−current protection threshold is reached, the PFC drive goes low. The device automatically resumes operation when the inductor current goes below the threshold. K LBO + http://onsemi.com 24 R LBOL R LBOU ) R LBOL NCP1910 PFC Reference Section V CTRL The internal reference voltage (VPREF) is trimmed to be ±2% accurate over the temperature range (the typical value is 2.5 V). VPREF is the reference used for the regulation of PFC section. V bulk R FBL @ G EAR Z R FBL ) R FBU 1 ) sR ZC Z @ (eq. 17) sR ZC Zǒ1 ) sR ZC PǓ PFC Power Analysis and Vin2 Feed−Forward From Equation 7 through 13, the input impedance Zin is re−formulated in Equation 18. PFC Feedback and Compensation Z in + Vbulk Vin + 2R MR SENSE @ K LBO 2 @ V ac 2 @ V bulkI L ǒ Ǔ p 2R CS @ V CTRL * V CTRLǒminǓ @ V PREFI L−50 (eq. 18) When IL is equal to IL−50, Equation 18 is re−formulated in Equation 19. RFBU Z in + FB VPREF OTA VCTRL RFBL RZ CP To Multiplier of VM pin Figure 49. VCTRL Type−2 Compensation The output voltage Vbulk of the PFC circuits is sensed at FB pin via the resistor divider (RFBL and RFBU) as shown in Figure 49. Vbulk is regulated as described in Equation 16. R FBU ) R FBL R FBL ǒ Ǔ p 2R CS @ V CTRL * V CTRLǒminǓ @ V PREF (eq. 19) The multiplier capacitor CM is the one to filter the high−frequency component of the multiplier voltage VM. The high−frequency component is basically coming from the inductor current IL. On the other hand, the input filter capacitor Cin similarly removes the high−frequency component of inductor current IL. If the capacitors CM and Cin match with each other in terms of filtering capability, IL becomes IL−50. Input impedance Zin is roughly constant over the bandwidth of 50 or 60 Hz and power factor is corrected. Input and output power (Pin and Pout) are derived in Equations 20 and 21 when the circuit efficiency η is obtained or assumed. The variable Vac stands for the rms input voltage. VCTRL(min) CZ V bulk + V PREF 2R MR SENSE @ K LBO 2 @ V ac 2 @ V bulk (eq. 16) P in + The feedback signal VFB represents the output voltage Vbulk and will be used in the output voltage regulation, Over−voltage protection (OVP), fast transient response, and under−voltage protection (UVP) The Operational Trans−conductance Amplifier (OTA) constructs a control voltage, VCTRL, depending on the output power and hence Vbulk. The operating range of VCTRL is from VCTRL(min) to VCTRL(max). The signal used for PFC duty modulation is after decreasing a offset voltage, VCTRL(min), i.e. VCTRL−VCTRL(min). This control voltage VCTRL is a roughly constant voltage that comes from the PFC output voltage Vbulk that is a slowly varying signal. The bandwidth of VCTRL can be additionally limited by inserting the external type−2 compensation components (that are RZ, CZ, and CP as shown in Figure 49). It is recommended to limit cross over frequency of open loop system below 20 Hz typically if the input ac voltage is 50 Hz to achieve power factor correction purpose. The transformer of Vbulk to VCTRL is as described in Equation 16 if CZ >> CP. GEA is the error amplifier gain. V ac 2 Z in ǒV T ǒ Ǔ p 2 @ R CS @ V CTRL * V CTRLǒminǓ @ V PREF + 2R MR SENSEK LBO 2 @ V bulk CTRL * V CTRLǒminǓ Ǔ (eq. 20) V bulk ǒ Ǔ p 2 @ R CS @ V CTRL * V CTRLǒminǓ @ V PREF P in + hP in + h ǒV T 2R MR SENSEK LBO 2 @ V bulk CTRL * V CTRLǒminǓ V bulk Ǔ (eq. 21) Because of the Vin2 feed−forward, the power delivery is independent from input voltage. Hence the transfer function of power stage is independent from input voltage, which easies the compensation loop design. http://onsemi.com 25 NCP1910 PFC Frequency Foldback is hence done by comparing (VCTRL − VCTRL(min)) with Vfold, the voltage on Fold pin. The simplified block diagram of PFC frequency foldback feature is depicted in Figure 50. NCP1910 implements frequency foldback feature on PFC section to improve the efficiency at light load. Thanks to Vin2 feed−forward feature, the output power is proportional to the (VCTRL − VCTRL(min)). The PFC frequency foldback PFCOSC Vref Vdd Ict(min) Ict − + Vfold Vfold(max) Ict(fold) “0” / ”1” VPREF / 10%VPREF Oscillator section Vctrl Grand Reset PFC BO Vctrl(min) S Q Q R PFC OK Figure 50. The PFC Frequency Foldback Block Where: ♦ ICt(min) limits the minimum operating frequency. ♦ ICt and ICt(min) provide the charging current for oscillator and hence control the nominal operating frequency. ♦ Vfold determines the power level at which the frequency foldback starts. ♦ ICt(fold) steals the ICt and hence reduces the operating frequency according to the error information between Vfold and (VCTRL − VCTRL(min)). The transient slope of frequency foldback vs. VCTRL is fixed inside. ♦ Vfold(max) is to limit the maximum power level of frequency foldback, which is around 2 V typically. The frequency foldback is disabled at startup, i.e. before the PFCok signal in Figure 50 is asserted high. The user can adjust the power level at which the frequency foldback starts by adjust the resistor divider between VREF pin and fold pin. Also, the frequency foldback can be disabled by grounding fold pin. The relationship between operating frequency and VCTRL is depicted in Figure 51. ♦ FREQUENCY Fsw The slope is fixed internally. The power level at which frequency starts reducing is adjustable by modifying Vfold. Fsw(fold) Vfold – 0.4 Vfold VCTRL−VCTRL(min) T Power Figure 51. The Relationship between Frequency and VCTRL http://onsemi.com 26 NCP1910 PFC Power Boost As depicted in previous section, thanks to the Vin2 feed-forward, the power delivery is independent from input voltage. It brings benefit of good power factor and a direct control on the frequency foldback. However, in some special case such as when the ac input voltage drops sharply from high line to low line, the power will be limited because the filter on LBO pin slows down the reaction speed to follow up the change on input voltage. In the end, the bulk voltage might drop too low and stop the LLC converter. Hence, NCP1910 builds a so-called PFC power boost function inside. The idea is to pull down LBO pin to 2 V typically, VLBO(PD), when • VLBO is above 2 V, VLBO(PD), i.e. the input is at high line, and • VCTRL is at maximum for more than timer defined by tPFCflag, and, • Vbulk is under 95% of nominal output, i.e. VLD is triggered. The maximum pulling-down duration is defined by tLBO(PDlimit), which is 5 ms typically. A blanking timer, tLBO(PDblank), is to avoid this power boost function reacting too soon, which is about 77 ms typically. The PFC power boost function is inhibited at start-up until bulk voltage is above 95% of nominal output. PFC Skip Mode In order to ensure a proper regulation in no load conditions, the circuit skips cycles when VCTRL is at its minimum level. VCTRL is maintained between about 0.6 V and 3.6 V due to the internal active clamps. A skip sequence occurs as long as the 0.6 V clamp circuitry is triggered and switching operations is recovered when the clamp is inactive. Fast Transient Response Given the low bandwidth of the regulation block, the output voltage of PFC stages may exhibit excessive over or under−shoots because of abrupt load or input voltage variations (such as start−up duration). As shown in Figure 52, if the output voltage is out of regulation, NCP1910 has 2 functions to maintain the output voltage regulation. Vbulk PFC_OK 105% VPREF Vdd IVLD 200 mA PFC_OVP + RFBU PFC_OPL − FB VLD 95% VPREF CFB RFBL $30 mA OTA VCTRL VPREF Figure 52. PFC OVP and VLD • Over−Voltage Protection (OVP): When VFB is higher than 105% of VPREF (i.e. Vbulk > 105% of nominal bulk voltage), the PFC driver output goes low for protection. The circuit automatically resumes operation when VFB becomes lower than 103.2% of VPREF, i.e. around 44 mV hysteresis in the OVP comparator. If the nominal Vbulk is set at 390 V, then the maximum bulk • voltage is 105% of 390 V = 410 V. Hence a cost and size effective bulk capacitor of lower voltage rating is suitable for this application, Voltage−Low Detection (VLD): NCP1910 drastically speeds up the regulation loop by its internal 200 mA enhanced current source when the bulk voltage is below 95% of its regulation level. Under normal condition, the http://onsemi.com 27 NCP1910 VCTRL pin current ( mA) maximum sink and source of output current capability of OTA is around 30 mA. Due to the “Vout Low Detect” block (VLD), when the VFB is below 95% VPREF, an extra 200 mA current source (IVLD in Figure 52) will raise VCTRL rapidly. Hence prevent the PFC output from dropping too low and improve the transient response performance. The relationship between current flowing in/out VCTRL pin and VFB is as shown in Figure 53. It is recommended to add a typical 100 pF capacitor CFB decoupling capacitor next to feedback pin to prevent from noise impact. 50 0 −50 2 2.2 2.4 2.6 2.8 3 −100 −150 No DRV when VFB is above 105% VPREF −200 −250 230 mA raises VCTRL rapidly when VFB is below 95% VPREF VFB Figure 53. VFB vs. Current Flowing in/out From VCTRL Pin PFCok Signal Refer to Figure 54. “PFCok” signal is low when • the PFC stage start−up, or • any latch off signal arrives, or • line brown−out activates. The PFC provides a “PFCok” signal to: • enable the dynamic response enhancer (IVLD) if Vbulk is below 95%, finish of the PFC soft−start, • enable the PFC frequency foldback, • enable the timer (tDEL1), which is to start the LLC−HB converter, • enable the timer (tDEL2), which is to stop LLC−HB converter once “PFCok” is asserted low or Vbulk is lower than PG level after LLC−HB has started. This “PFCok” signal is high when the PFC stage is in normal operation, i.e. its output is above 95% of normal output, and low otherwise. “PFCok” signal is high when • DRV starts operating and the PFC stage is above 95% • of target, i.e. the VLD comparator output is high, or the PFC stage is above 100% target, i.e. PFCREG comparator output is high. PFC_BO Latch Grand Reset R Q Q 95% VPREF + DRV S − VLD FB + VPREF − PFCREG Figure 54. PFCok Signal Block Diagram http://onsemi.com 28 PFC_OK NCP1910 PFC Soft−Start As shown in Figure 55, when VFB is less than 8% of VPREF, the device is shut down. The device automatically starts operation when the output voltage goes above 12% of VPREF. In normal situation of boost converter configuration, the bulk voltage Vbulk is always greater than the input voltage Vin and the feedback signal VFB has to be always greater than 8% and 12% of VPREF to enable NCP1910 to operate. The main purpose of this Under−Voltage Protection function is to protect the power stage from damage at feedback loop abnormal, such as VFB is grounded or the feedback resistor RFBU is open. Refer to Figure 52 and 54. The device provides no PFC driver output when the VCTRL is lower than VCTRL(min). VCTRL is pulled low by: • VCC Under−Voltage Lockout, or • Off signal from on/off pin, or • Thermal Shut−down (TSD), or • Line Brown−out, or • PFC Under−Voltage Protection At one of these situations, NCP1910 grounds the VCTRL pin and turns off the 200 mA current source in regulation block. When the IC turns on again: • VCTRL will be pulled low and PFC DRV output keeps off until VCTRL is below VCTRL(min) to make PFC starts with lowest duty cycle. • The 200 mA current source block keeps off. Only the Operating Transconductance Amplifier (OTA) raises the VCTRL slowly. This is to obtain a slow increasing duty cycle and hence reduce the voltage and current stress on the MOSFET. A soft−start operation is obtained. Redundant Over−Voltage Protection (OVP2 pin) Except the Over−Voltage Protection in FB pin, NCP1910 also reserve one dedicated pin, OVP2 pin, for the redundant over voltage protection on bulk voltage. The purpose of this feature is to protect the power components from damage in case of any drift on the feedback resistor. As shown in Figure 56, the OVP2 has 3 differences compared to the OVP in FB pin: • The protection mode provided by OVP2 pin is latch−off. When OVP2 is triggered, the NCP1910 stays at latch off mode, i.e. both PFC and LLC stop. • A 20 ms filter is built−in after the OVP2 comparator for better noise immunity. • The reference voltage for this OVP2 comparator is 107% of VPREF. The resistance value of ROVPU and ROVPL could be the same as RFBU and RFBL depending on the requirement of OVP2 level. In this case, the level of the OVP in FB pin would be 105% of normal bulk voltage and OVP2 will be 107% of normal bulk voltage. Or if one would need a higher level for the OVP2, then it is flexible to change the value. If someone doesn’t need this OVP2 feature, then OVP2 function could be disable by grounding the OVP2 pin. PFC Under−Voltage Protection (UVP) for Open Loop Protection ICC2 Operating Shutdown ICC7 8% VPREF 12% VPREF VFB Figure 55. PFC Under−Voltage Protection Vbulk ROVPU OVP2 20 ms filter PFC_OVP2 to SR-latch 107% VPREF COVP ROVPL Figure 56. PFC 2nd Over−Voltage Protection http://onsemi.com 29 NCP1910 PFC Abnormal However, as a D−flip−flop that creates division−by−two internally provides two outputs (A and B in Figure 57), the final effective signal on LLC driver outputs (ML and MU) switches between 25 kHz and 500 kHz. The CCO is configured in such a way that if the current that flows out from the Rt pin increases, the switching frequency also goes up. The PFC abnormal is detected by sensing VCTRL level. When VCTRL stays at VCTRL(max), or lower than VCTRL(min) – 0.1 V, for more than tPFCabnormal, PFC turns off first. After tDEL2, LLC shuts down. It is latches off protection. The main purpose of this feature is to avoid LLC from operating without correct operation of PFC stage. LLC Section Current Controlled Oscillator (CCO) The current controlled oscillator features a high−speed circuitry allowing operation from 50 kHz up to 1 MHz. VDD + VRt Rt RSS Q Q B for ML A VCtmax SS Feedback opto-coupler for MU R Ct Rmin S Clk - IDT Rmax D LLCenable Grand Reset CSS Grand Reset Latch LLC_BO CS/FF > VCS1 tDEL2 elapsed Q S S Q Q Q R Grand Reset Disable LLC ML and MU R Grand Reset LLC_PG + VSS_RST Figure 57. The Current Controlled Oscillator Architecture and Configuration For the resonant applications, it is necessary to adjust minimum operating frequency with high accuracy. The designer also needs to limit maximum operating and startup frequency. All these parameters can be adjusted by using external components connected to the Rt pin as shown in Figure 57. The following approximate relationships hold for the minimum, maximum and startup frequency respectively: The internal timing capacitor Ct is charged by current which is proportional to the current flowing out from the Rt pin. The discharging current iDT is applied when voltage on this capacitor reaches VCtmax. The output drivers are disabled during discharge period so the dead time length is given by the discharge current sink capability. Discharge sink is disabled when voltage on the timing capacitor reaches zero and charging cycle starts again. Ct is grounded to disable the oscillator when either of “turn−off LLC” signals arrives. http://onsemi.com 30 NCP1910 • The minimum switching frequency is given by the Rmin The definition of start−up, shut−off and these 2 delay timers (tDEL1 and tDEL2) will be depicted later in “combo management section”. There are the other 2 delay timers are built−in after the brown−out comparator: • tBOK is the delay timer after Vbulk is rising above the BO level. • tBONOTOK is the delay timer after Vbulk is falling down the BO level. NCP1910 gets the information of Vbulk from the PFC FB pin, which minimizes the losses of the high voltage sensing circuit. As depicted in Figure 22, 3 resistors (R1, R2, and R3) among VREF, PGadj, BOadj pin, and ground determine the levels of PGout signal and LLC brown−out as the following formulas: resistor value. This frequency is reached if there is no feedback action and soft start period has already elapsed. R min + 10 6V Rt 490 F min (eq. 22) • The maximum switching frequency excursion is limited by the Rmax selection. Note that the maximum frequency is influenced by the opto−coupler saturation voltage value. R max + 490 10 6V Rt F max * F min (eq. 23) • Resistor RSS together with capacitor CSS prepares the V PG + soft start period for the resonant converter. R SS + 490 10 6V Rt F SS * F min R2 ) R3 R1 ) R2 ) R3 (eq. 24) + V bulk,PG @ Where: ♦ VRt = 3.5 V ♦ Fmin is the minimal frequency ♦ Fmax is the maximal frequency ♦ FSS is the maximal soft start switching frequency V BO + (eq. 25) R FBL R FBU ) R FBL R3 R1 ) R2 ) R3 + V bulk,BO @ LLC Power Good Signal and Brown−out (PGadj, PGout and BOadj Pin) @ V REF + V bulk,PG @ V PREF V bulk,nom @ V REF (eq. 26) R FBL R FBU ) R FBL + V bulk,BO @ V PREF V bulk,nom Where: ♦ VPG is the voltage on PGadj pin ♦ VBO is the voltage on BOadj pin ♦ VREF is the reference voltage (5 V typically). ♦ VPREF is the internal reference voltage for PFC feedback OTA (2.5 V typically) ♦ Vbulk,PG is the bulk voltage when PGout pin is released open. ♦ Vbulk,BO is the bulk voltage when brown−out function of LLC activates. ♦ Vbulk,nom is the normal bulk voltage, e.g. 390 V. Divide Equation 25 by 26, we can get the relationship between R2 and R3 in Equation 27: As shown in Figure 22, the NCP1910 provides the Brown−Out circuitry (BO) that offer a way to protect the resonant converter from operating at too low Vbulk. In the mean time, NCP1910 provides a Power Good signal (PGout) to inform the isolated secondary side that the NCP1910 is in order of match. Once the PFC has started and raises Vbulk above 95% of its regulated voltage, an internal “PFC_OK” signal is asserted. 20 ms later (tDEL1), the PGout pin is brought low. The PGout signal can now disappear, which will release PGout pin open, in two cases: • Vbulk decreases to the level, programmed by a reference voltage imposed on PGadj pin. This level is usually above the LLC turn−off voltage, programmed by BOadj pin. Therefore, in a normal turn−off sequence, PG first drops and informs the secondary side that it must be prepared for shutdown. • The second event that can drop the PG signal is when the PFC experiences a fault: broken feedback path (PFC UVP), PFC abnormal, or input line brown−out. In either case, the internal PFCok signal will drop and then assert the PGout signal high, and starts a 5 ms timer (tDEL2). Once this timer is elapsed, the LLC converter can be safely halted. R2 R3 + V bulk,PG V bulk,BO *1 (eq. 27) Hence, by given Vbulk,PG and Vbulk,BO, and choose the value R3 as the 1st step, we can get the R2 by Equation 27 and R1 by Equation 26. For example, Vbulk,nom is 390 V, Vbulk,PG is 340 V, and Vbulk,BO is 330 V. Choose 10 kW resistor as R3. Then R2 is 303 W. Choose 300 W as it is the closet standard resistor. Then we can get the R1 is 13.3 kW. http://onsemi.com 31 NCP1910 VREF R3 BOadj + ”1” BONOTOK R1 R2 tBONOTOK PFC_FB LLCenable PFC_OK ”1” is ok ”0” notok ”1” PGNOTOK ”1” enables LLC ”0” LLC is locked − PGadj LLC_BO tBOK − + LLC_BO LLC_PG VCC SS is reset Grand Reset VSB R tDEL1 20 ms R tDEL2 PGout 5 ms ”1” after reset ”0” when PG out drops after 5 ms PGI for supervisory To close switch at SS pin Figure 58. The PG and BO Block Diagram for LLC LLC Fast Fault Input (CS/FF Pin) (ML and MU) is shifted up to keep the primary current under acceptable level. In case of heavy overload, like transformer short circuit, the primary current grows very fast and thus could reach danger level. The NCP1910 therefore features additional comparator VCS2 (1.5 V typically) at the CS/FF pin to permanently latch the device (both PFC and LLC) and protect against destruction. As shown in Figure 59, the NCP1910 offers a dedicated input (CS/FF pin) to detect the primary over−current conditions and protect the power stage from damage. Once the voltage on the CS/FF pin exceeds the threshold of VCS1 (1 V typically), the internal switch at SS pin will be closed to discharge CSS until VSS is below VSS_RST (150 mV typically). Hence the switching frequency of LLC http://onsemi.com 32 NCP1910 PFC_OVP2 CS/FF + − S Q Q VCS2 Latch ”1” to disable LLC and PFC driver, and pull down PFCok R + PFC_BO Grand Reset ”1” to set the SR−latch to pull low SS pin − VCS1 Figure 59. The Fast Fault Input at CS/FF pin LLC Soft−Start (SS Pin) Once the LLC part starts operation, the internal switch at SS pin is released open and the empty soft−start capacitor withdraws current from Rt pin through soft−start resistor, RSS. This current charges up and soft−start capacitor and increases the operating frequency of LLC. As the soft−start capacitor is charged, the LLC driver output frequency smoothly decreases down to Fmin. Of course, practically, the feedback loop is supposed to take over the CCO lead as soon as the output voltage has reached the target. In resonant converter, a soft−start is needed to avoid suddenly applying the full current into the resonating circuit. NCP1910 reserves SS pin to fully discharge soft−start capacitor before re−start and in case of fault conditions: • LLC brown−out actives, • tDEL2 is elapsed, where tDEL2 timer could be activated by line brown−out or power good comparator, • CS/FF pin is above VCS1, the fast fault input for LLC, • VCC UVLO, • PFC UVP, • Off signal from on/off pin, or • Thermal Shut−Down (TSD) When the switch inside SS pin is activated to discharge the soft−start capacitor, it keeps close until VSS is below VSS_RST (150 mV typically). It ensures the full discharge of soft−start capacitor before re−start, and hence the fresh soft−start is confirmed. LLC Skip (Skip Pin, B Version Only) To avoid any frequency runaway in light conditions but also to improve the standby power consumption, the NCP1910B welcomes a skip mode operation (Skip pin) which permanently observes the opto−coupler collector as depicted in Figure 60. If skip pin senses a low voltage, it cuts the LLC output pulses (ML and MU pins) until the collector goes up again. Rt Rmax RSS Rmin SS CSS Skip − VSkip + Feedback opto−coupler Disable ML and MU Figure 60. The LLC Skip Mode Configuration http://onsemi.com 33 NCP1910 LLC High−Voltage Driver another timer (tDEL2) starts. Once the tDEL2 is elapsed, LLC stops its drivers (ML and MU pins). Figure 61 depicts the start−up and stop delay of LLC and PGout. Once the PFC is ready (PFCok is asserted high), tDEL1 (20 ms typically) is started. Once this delay is elapsed: • PGout pin is asserted low • LLC drivers (ML and MU pins) can start to operate. The NCP1910 includes a high−voltage driver allowing a direct connection to the upper side MOSFET of LLC converter. This device also incorporates an upper UVLO circuitry that makes sure enough gate voltage is available for the upper side MOSFET. The bias of the floating driver section is provided by Cboot capacitor between Vboot pin and HB pin that is refilled by external booststrap diode. The floating portion can go up to 600 Vdc and makes the IC perfectly suitable for offline applications featuring a 400 V PFC front−end stage. As shutdown by unplug ac input, Vbulk decreases: • When it reaches the PG signal, which is adjusted by PGadj pin, PGout pin is released open. • If Vbulk reaches the LLC stop level (BO level adjusted by BOadj pin), the LLC stops; or if Vbulk drops slowly, e.g. light load, LLC drivers (ML and MU pins) will stop 5 ms after PGout pin is released (tDEL2). Combo Management Section Start−up and Stop Delay of LLC and Pgout signal (tDEL1 and tDEL2) To ensure the proper operation of LLC, LLC cannot start if the PFC is not ready. As depicted in the “PFCok signal” section, the internal PFCok signal is asserted high when Vbulk is above 95% of normal bulk voltage. After PFCok signal is high, a timer (tDEL1) starts to ensure PFC stage is fully stable before LLC starts. When tDEL1 is elapsed, PGout pin is grounded and LLC starts its driver outputs (ML and MU pins). In case of shutdown by unplugging ac input or line brown out situation, PGout signal is released open. And then As shutdown by line brown−out situation, PFCok signal will be pulled down: • PGout pin is released open once this internal PFCok signal is low. • LLC drivers (ML and MU pins) will stop 5 ms after PGout pin is released open (tDEL2). Vbulk 95% PG level BO level tDEL1 20 ms PGout tDEL2 LLC works off 5 ms off Figure 61. The Timing for tDEL1 and tDEL2 time • When the on/off pin is above 3 V, the device stops both Remote on/off (on/off pin) NCP1910 reserves one dedicated pin for remote control feature at on/off pin: • When the on/off pin is pulled below 1 V, the PFC starts operation. 20 ms after Vbulk is above 95% of target level, LLC starts. PFC and LLC immediately and keeps low consumption. Figure 62 depicts the relationship between the operation mode and on/off pin. http://onsemi.com 34 NCP1910 State ON OFF On/off pin TBD ICC < 600 mA Voff Von On/off pin Figure 62. Remote on/off (on/off Pin) VCC Under−Voltage LockOut (UVLO) some hysteresis (VCC(Hys)) to prevent erratic operation as the VCC crosses the threshold. When VCC goes below the UVLO comparator lower threshold (VCC(min)), the circuit turns off. It is illustrated in Figure 63. After startup, the operating range is between 9 V and 20 V. The device incorporates an Under−Voltage Lockout block to prevent the circuit from operating when VCC is too low in order to ensure a proper operation. An UVLO comparator monitors VCC pin voltage to allow the NCP1910 to operate when VCC exceeds VCC(on). The comparator incorporates State ON OFF TBD ICC VCC < 100mA VCC(on) VCC(min) VCC Figure 63. VCC Under−Voltage LockOut (UVLO) Bias the Controller temperature exceeds TSD level. The output stage is then enabled once the temperature drops below typically 110°C (i.e. TSD − TSDhyste). The thermal shutdown is provided to prevent possible device failures that could result from an accidental over−heating. It is recommended to add a typical 1 nF to 100 nF decoupling capacitor next to the VCC pin for proper operation. The hysteresis between VCC(on) and VCC(min) is small because the NCP1910 is supposed to be biased by external power source. Therefore it is recommended to make a low−voltage source to bias NCP1910, e.g. the standby power supply. 5 V Reference The VREF pin provides an accurate (±2% typically) 5 V reference voltage. The Power−Good and Brown−Out of LLC converter, and the frequency foldback level (fold pin) of PFC can hence can get an accurate reference voltage by resistor dividers. Thermal Shutdown An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction http://onsemi.com 35 NCP1910 • Recycle VCC so that VCC is below VCC(min) and back Latched Protections and Reset As depicated in the above sections, there are 3 fault modes that latch off both PFC and LLC: • PFC abnormal • PFC OVP2 • LLC CS/FF pin is above VCS2 To release from the latch−off mode, NCP1910 offers 3 ways: • • to above VCC(on) again. Recycle the remote on/off function, which toggles on/off pin high and low again. Recycle the line brown−out function, which could be done by unplug and re−plug the ac input. ORDERING INFORMATION Device Version Marking Package Shipping† NCP1910A65DWR2G 65 kHz − A NCP1910A65 SOIC 24WB Less Pin 21 (Pb−Free) 1000 / Tape & Reel NCP1910B65DWR2G 65 kHz − B NCP1910B65 SOIC 24WB Less Pin 21 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 36 NCP1910 PACKAGE DIMENSIONS SOIC−24 WB LESS PIN 21 CASE 752AB−01 ISSUE O 0.20 C A-B 2X D D A H NOTE 7 24 E 2X 13 E1 1 NOTES 5 & 6 L2 12 0.33 C 0.10 C D B PIN 1 INDICATOR 0.25 TOP VIEW C DETAIL A 2X 24X b NOTE 7 L C A-B D M NOTES 3 & 4 NOTE 9 h x 45 _ 0.10 C 0.10 C A e A1 NOTE 8 C c SEATING PLANE DETAIL A END VIEW SIDE VIEW M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF ’b’ AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD AND ARE MEASURED BETWEEN 0.10 AND 0.25 FROM THE LEAD TIP. 5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 6. DIMENSIONS D AND E1 ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, PROTRUSIONS, TIE BAR BURRS, OR GATE BURRS BUT INCLUSIVE OF ANY MOLD MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM H. 8. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. 9. THIS CHAMFER IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 IDENTIFIER MUST BE LOCATED IN THE INDICATED AREA. RECOMMENDED SOLDERING FOOTPRINT* 23X 23X 1.62 0.52 DIM A A1 b J D E E1 e h L L2 M MILLIMETERS MIN MAX 2.35 2.65 0.10 0.29 0.31 0.51 0.20 0.33 15.40 BSC 10.30 BSC 7.50 BSC 1.27 BSC 0.25 0.75 0.40 1.27 0.25 BSC 0_ 8 _ 11.00 1 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 37 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP1910/D