DG3001, DG3002, DG3003 Vishay Siliconix Low-Voltage Sub- SPST/SPDT MICRO FOOT® Analog Switch DESCRIPTION FEATURES The DG3001, DG3002, DG3003 are monolithic CMOS analog switches designed for high performance switching of analog signals. The DG3001 and DG3002 are configured as SPST switches, and the DG3003 is an SPDT switch. Combining low power, high speed (tON: 47 ns, tOFF: 40 ns), low on-resistance (rDS(on): 0.4 ) and small physical size (MICRO FOOT, 6-bump), the DG3001, DG3002, DG3003 are ideal for portable and battery powered applications requiring high performance and efficient use of board space. • MICRO FOOT chip scale package (1.0 mm x 1.5 mm) • Low voltage operation (1.8 V to 5.5 V) • Low on-resistance - RDS(on): 0.4 • Fast switching - tON : 47 ns, tOFF: 40 ns • Low power consumption • TTL/CMOS compatible The DG3001, DG3002, DG3003 are built on Vishay Siliconix’s low voltage JI2 process. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to the power supply level when off. As a committed partner to the community and the environment, Vishay Siliconix manufactures this product with the lead (Pb)-free device terminations. For MICRO FOOT analog switching products manufactured with tin/ silver/copper (Sn/Ag/Cu) device terminations, the lead (Pb)-free “-E1” suffix is being used as a designator. BENEFITS • • • • Reduced power consumption Simple logic interface High accuracy Reduce board space APPLICATIONS • • • • • • Cellular phones Communication systems Portable test equipment Battery operated systems PCM cards PDA FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION MICRO FOOT (6-Bump) MICRO FOOT (6-Bump) DG3002DB DG3001DB DG3003DB V+ B1 A1 NC (Source1) V+ B1 A1 NO (Source1) B2 A2 COM IN B2 A2 COM B3 A3 GND B3 A3 COM V+ B1 A1 NO (Source1) IN B2 A2 COM IN B3 A3 COM GND GND MICRO FOOT (6-Bump) Device Marking: 3001 xxx = Date/Lot Traceability Code A1 Locator Device Marking: 3002 xxx = Date/Lot Traceability Code XXX 3003 XXX 3002 XXX 3001 A1 Locator NC (Source2) Top View Top View Top View A1 Locator Device Marking: 3003 xxx = Date/Lot Traceability Code TRUTH TABLE Logic NC NO 0 ON OFF 1 OFF ON * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 www.vishay.com 1 DG3001, DG3002, DG3003 Vishay Siliconix ORDERING INFORMATION Temp. Range Package Part Number DG3001DB-T1 DG3002DB-T1 DG3003DB-T1 DG3001DB-T1-E1 DG3002DB-T1-E1 DG3003DB-T1-E1 MICRO FOOT: 6/-Bump 3 x 2, 0.5-mm pitch, 165 µm nom. bump height (Eutectic, SnPb) - 40 °C to 85 °C MICRO FOOT: 6-Bump 3 x 2, 0.5-mm pitch, 238 µm nom. bump height (Lead (Pb)-free, Sn/Ag/Cu) ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Limit Reference V+ to GND IN, COM, NC, NOa - 0.3 to (V+ + 0.3 V) Continuous Current (NO, NC, COM) ± 250 Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 400 Storage Temperature (D Suffix) b Package Reflow Conditions IR/Convection Unit - 0.3 to + 6 V mA - 65 to 150 VPR (Eutectic) 215 (Eutectic) 220 (Lead (Pb)-free) 250 °C 250 mW 6-Bump, 2 x 3 MICRO FOOTd Power Dissipation (Packages)c Notes: a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. Refer to IPC/JEDEC (J-STD-020A) c. All bumps soldered to PC board. d. Derate 3.1 mW/°C above 70 °C. www.vishay.com 2 Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 DG3001, DG3002, DG3003 Vishay Siliconix SPECIFICATIONS (V+ = 3.0 V) Test Conditions Otherwise Unless Specified Parameter Analog Switch Symbol VNO, VNC, VCOM Analog Signal Ranged On-Resistanced RON RON Flatness RON Flatnessd RON RON Matchd Switch Off Leakage Current V+ = 3 V, ± 10 %,VIN = 0.4 V or 2.0 Ve f INO(off) INC(off) ICOM(off) Channel-On Leakage Currentf ICOM(on) Limits - 40 °C to 85 °C Temp.a Min.b Full 0 V+ = 2.7 V, VCOM = 0 to V+ INO, INC = 10 mA Room 0.1 0.2 Room 0.01 0.05 V+ = 3.3 V, VNO, VNC = 0.3 V/3 V, VCOM = 3 V/0.3 V V+ = 3.3 V, VNO, VNC = VCOM = 0.3 V/3 V Room Full -1 - 10 1 10 Room Full Room Full -1 - 10 -1 - 10 1 10 1 10 2 Full Full Input Capacitanced Cin tON Turn-Off Timed tOFF Break-Before-Make Timed Charge Injection d Off-Isolationd OIRR Crosstalkd XTALK NO, NC Off Capacitanced Channel-On Capacitanced Power Supply Positive Supply Range Negative Supply Current CNO(off) CNC(off) Full 5 Full VNO or VNC = 2.0 V, RL = 300 , CL = 35 pF figure 1 and 2 Room Full Room Full CL = 1 nF, VGEN = 0 V, RGEN = 0 figure 3 Room 64 Room - 70 Room - 70 Room 100 Room 340 Room RL = 50, CL = 5 pF, f = 100 kHz VIN = 0 or V+, f = 1 MHz CON V+ I+ 0.4 VIN = 0 or V+ td QINJ V 0.7 0.8 VINL Turn-On Timed V+ 0.4 VINH IINL or IINH Unit Room Full Input Low Voltage Input Current Dynamic Characteristics Max.b V+ = 2.7 V, VCOM = 1.5 V INO, INC = 10 mA Digital Control Input High Voltage d Typ.c -1 1 nA V pF 1 47 71 40 59 µA ns 6 2.7 VIN = 0 or V+ pC dB pF 3.3 0.1 1.0 V µA Notes: a. Room = 25 °C, Full = as determined by the operating suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for design aid only, not guaranteed nor subject to production testing. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 www.vishay.com 3 DG3001, DG3002, DG3003 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2.00 1.00 R ON - On-Resistance (Ω) 1.75 R ON - On-Resistance () V+ = 3 V IS = 10 mA T = 25 °C IS = 10 mA 1.50 1.25 V+ = 1.8 V 1.00 V+ = 2 V 0.75 V+ = 2.7 V V+ = 3 V 0.50 V+ = 5 V 0.80 85 °C 0.60 25 °C 0.40 - 40 °C 0.20 0.25 V+ = 3.3 V 0.00 0 1 2 3 4 0.00 0.0 5 0.5 1.0 VCOM - Analog Voltage (V) 2.0 2.5 3.0 VCOM - Analog Voltage (V) RON vs. VCOM and Supply Voltage RON vs. Analog Voltage and Temperature 10 000 100 mA 10 mA I+ - Supply Current (A) 1000 I+ - Supply Current (nA) 1.5 V+ = 5 V VIN = 0 V 100 10 V+ = 5 V 1 mA 100 µA 10 µA 1 µA 100 nA 10 nA 1 - 60 1 nA - 40 - 20 0 20 40 60 80 100 10 100 Temperature (°C) 1K 10 K 100 K 1M 10 M Input Switching Frequency (Hz) Supply Current vs. Temperature Supply Current vs. Input Switching Frequency 1000 250 V+ = 5 V 200 ICOM(on) V+ = 5 V Leakage Current (pA) Leakage Current (pA) 150 100 ICOM(off) INO(off), INC(off) ICOM(off) 100 50 ICOM(on) 0 INO(off), INC(off) - 50 - 100 - 150 - 200 10 - 60 - 40 - 20 0 20 40 60 80 Temperature (°C) Leakage Current vs. Temperature www.vishay.com 4 100 - 250 0 1 2 3 4 5 VCOM, V NO, V NC - Analog Voltage (V) Leakage vs. Analog Voltage Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 DG3001, DG3002, DG3003 Vishay Siliconix 100 10 90 0 LOSS 80 - 10 tON V+ = 2 V Loss, OIRR, XTALK (dB) t ON, t OFF - Switching Time (ns) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 70 tOFF V+ = 2 V 60 tON V+ = 3 V 50 40 tOFF V+ = 3 V 30 - 20 OIRR - 40 - 50 - 70 10 - 80 - 40 - 20 0 20 40 60 80 V+ = 3 V RL = 50 - 60 20 0 - 60 XTALK - 30 - 90 100 K 100 1M Temperature (°C) 10 M 100 M 1G Frequency (Hz) Switching Time vs. Temperature and Supply Voltage Insertion Loss, Off-Isolation, Crosstalk vs. Frequency 3.0 250 Q - Charge Injection (pC) V T - Switching Threshold (V) 200 2.5 2.0 1.5 1.0 150 V+ = 5 V 100 50 0 - 50 V+ = 3 V V+ = 2 V - 100 - 150 0.5 - 200 0.0 - 250 0 1 2 3 4 5 6 7 0 1 2 3 4 V+ - Supply Voltage (V) VCOM - Analog Voltage (V) Switching Threshold vs. Supply Voltage Charge Injection vs. Analog Voltage Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 5 www.vishay.com 5 DG3001, DG3002, DG3003 Vishay Siliconix TEST CIRCUITS V+ VINH Logic Input 50 % VINL V+ NO or NC Switch Input tr < 5 ns tf < 5 ns Switch Output COM VOUT 0.9 x VOUT Switch Output IN Logic Input RL 300 GND CL 35 pF 0V tOFF tON Logic "1" = Switch On Logic input waveforms inverted for switches that have the opposite logic sense. CL (includes fixture and stray capacitance) = VCOM V OUT RL R L + R ON Figure 1. Switching Time V+ Logic Input V+ tr < 5 ns tf < 5 ns VINL COM NO VNO VINH VO NC VNC RL 300 IN CL 35 pF GND VNC = VNO VO Switch Output 90 % 0V tD tD CL (includes fixture and stray capacitance) Figure 2. Break-Before-Make Interval V+ Rgen VOUT V+ COM NC or NO VOUT VOUT + Vgen IN CL = 1 nF IN On Off On GND Q = VOUT x CL VIN = 0 – V+ IN depends on switch configuration: input polarity determined by sense of switch. Figure 3. Charge Injection www.vishay.com 6 Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 DG3001, DG3002, DG3003 Vishay Siliconix TEST CIRCUITS V+ 10 nF V+ NC or NO IN 0 V, 2.4 V COM VCOM Off Isolation = 20 log RL GND VNO/ NC Analyzer Figure 4. Off-Isolation V+ 10 nF V+ COM Meter IN 0 V, 2.4 V NC or NO GND HP4192A Impedance Analyzer or Equivalent f = 1 MHz Figure 5. Channel Off/On Capacitance Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 www.vishay.com 7 DG3001, DG3002, DG3003 Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 6-BUMP (3 x 2, 0.5 mm PITCH, 165 µm BUMP HEIGHT) 6 x Ø 0.150 0.229 Note b Solder Mask Ø Pad Dia. + 0.1 0.5 Silicon 0.5 A2 A A1 Recommended Land Pattern Bump Note a Index-Bump A1 Note c 3 2 1 b Diameter A XXX 3003 E e B S S Top Side (Die Back) e D Notes (Unless Otherwise Specified): a. Bump is Eutectic 63/57 Sn/Pb or Lead (Pb)-free Sn/Ag/Cu. b. Non-solder mask defined copper landing pad. c. Laser Mark on silicon die back; no coating. Shown is not actual marking; sample only. EUTECTIC (Sn/Pb) LEAD (Pb)-FREE (Sn/Ag/Cu) Inches Millimetersa Inches Millimetersa Dim. Min. Max. Min. Max. Dim. Min. Max. Min. Max. A 0.610 0.685 0.0240 0.0270 A 0.688 0.753 0.0271 0.0296 A1 0.140 0.190 0.0055 0.0075 A1 0.218 0.258 0.0086 0.0102 A2 0.470 0.495 0.0185 0.0195 A2 0.470 0.495 0.0185 0.0195 b 0.180 0.250 0.0071 0.0098 b 0.306 0.346 0.0120 0.0136 D 1.490 1.515 0.0587 0.0596 D 1.490 1.515 0.0587 0.0596 E 0.990 1.015 0.0390 0.0400 E 0.990 1.015 0.0390 0.0400 e S 0.5 BASIC 0.245 0.258 0.0197 BASIC 0.0096 Notes: a. Use millimeters as the primary measurement. 0.0101 e S 0.5 BASIC 0.245 0.258 0.0197 BASIC 0.0096 0.0102 Notes: a. Use millimeters as the primary measurement. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72505. www.vishay.com 8 Document Number: 72505 S11-0303-Rev. D, 28-Feb-11 AN824 Vishay Siliconix PCB Design and Assembly Guidelines For MICRO FOOTr Products Johnson Zhao INTRODUCTION Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. For example, the 6−bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same performance as TSSOP−8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A MICRO FOOT analog switch, the 6−bump DG3000DB, offers low charge injection and 1.4 W on−resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). Vishay Siliconix MICRO FOOT products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable performance without underfill. The advantage of the device’s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, PDAs, cellular phones, and notebook computers. This application note discusses the mechanical design and reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework process. FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and Si8900EDB 3 2 1 0.18 ~ 0.25 A 1.08 0.5 B 0.285 0.285 0.5 1.58 FIGURE 2. Outline of MICRO FOOT CSP & Analog Switch DG3000DB Document Number: 71990 06-Jan-03 www.vishay.com 1 AN824 Vishay Siliconix TABLE 1 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Main Parameters of Solder Bumps in MICRO FOOT Designs MICRO FOOT CSP Bump Material MICRO FOOT CSP MOSFET Eutectic Solder: 63Sm/37Pb MICRO FOOT CSP Analog Switch MICRO FOOT UCSP Analog Switch Bump Pitch* Bump Diameter* Bump Height* 0.8 0.37-0.41 0.26-0.29 0.5 0.18-0.25 0.14-0.19 0.5 0.32-0.34 0.21-0.24 * All measurements in millimeters MICRO FOOT’S DESIGN AND RELIABILITY BOARD LAYOUT GUIDELINES As a mechanical, electrical, and thermal connection between the device and PCB, the solder bumps of MICRO FOOT products are mounted on the top active surface of the die. Table 1 shows the main parameters for solder bumps used in MICRO FOOT products. A silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. A green laser is used to mark the backside of the die without damaging it. Reliability results for MICRO FOOT products mounted on a FR-4 board without underfill are shown in Table 2. Board materials. Vishay Siliconix MICRO FOOT products are designed to be reliable on most board types, including organic boards such as FR-4 or polyamide boards. The package qualification information is based on the test on 0.5-oz. FR-4 and polyamide boards with NSMD pad design. TABLE 2 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ MICRO FOOT Reliability Results Test Condition C: −65_ to 150_C >500 Cycles Test condition B: −40_ to 125_C >1000 Cycles 121_C @ 15PSI 100% Humidity Test 96 Hours The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results shown in Table 2 demonstrate that a high level of reliability can be achieved with proper board design and assembly techniques. Land patterns. Two types of land patterns are used for surface-mount packages. Solder mask defined (SMD) pads have a solder mask opening smaller than the metal pad (Figure 3), whereas on-solder mask defined (NSMD) pads have a metal pad smaller than the solder-mask opening (Figure 4). NSMD is recommended for copper etch processes, since it provides a higher level of control compared to SMD etch processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the PCB. By contrast, SMD pad definition introduces a stress concentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. Copper pads should be finished with an organic solderability preservative (OSP) coating. For electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 mm to avoid solder joint embrittlement. Solder Mask Copper Copper FIGURE 3. SMD www.vishay.com 2 Solder Mask FIGURE 4. NSMD Document Number: 71990 06-Jan-03 AN824 Vishay Siliconix TABLE 3 Dimensions of Copper Pad and Solder Mask Opening in PCB and Stencil Aperture ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Pitch Copper Pad Solder Mask Opening Stencil Aperture 0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm 0.33 " 0.01 mm in ciircle aperture 0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm 0.30 " 0.01 mm in square aperture ASSEMBLY PROCESS MICRO FOOT products’ surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (Figure 5). Chip pick-and-placement. MICRO FOOT products can be picked and placed with standard pick-and-place equipment. The recommended pick-and-place force is 150 g. Though the part will self-center during solder reflow, the maximum placement offset is 0.02 mm. Reflow Process. MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other package, the thermal profile at specific board locations must be determined. Nitrogen purge is recommended during reflow operation. Figure 6 shows a typical reflow profile. Thermal Profile 250 200 Temperature (_C) Board pad design. The landing-pad size for MICRO FOOT products is determined by the bump pitch as shown in Table 3. The pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. 150 100 50 Stencil Design IIncoming Tape and Reel Inspection 0 0 Solder Paste Printing 100 200 300 400 Time (Seconds Chip Placement FIGURE 6. Reflow Profile Reflow Solder Joint Inspection Pack and Ship FIGURE 5. SMT Assembly Process Flow PCB REWORK To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 1. Stencil design. Stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). The stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. Remove the MICRO FOOT device using a convection nozzle to create localized heating similar to the original reflow profile. Preheat from the bottom. 2. Once the nozzle temperature is +190_C, use tweezers to remove the part to be replaced. 3. In MICRO FOOT products, the stencil is 0.125-mm (5-mils) thick. The recommended apertures are shown in Table 3 and are fabricated by laser cut. Resurface the pads using a temperature-controlled soldering iron. 4. Apply gel flux to the pad. 5. Use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. 6. Reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile. Solder-paste printing. The solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. In MICRO FOOT products, the solder paste used is UP78 No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. Document Number: 71990 06-Jan-03 www.vishay.com 3 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1