TI1 ADS1000A0QDBVRQ1 Low-power 12-bit analog-to-digital converter Datasheet

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ADS1000-Q1
SBAS480B – SEPTEMBER 2009 – REVISED OCTOBER 2015
ADS1000-Q1 Low-Power 12-Bit Analog-to-Digital Converter With I2C™ Interface
1 Features
3 Description
•
•
The ADS1000-Q1 is an I2C-compatible serial
interface analog-to-digital (A/D) converter with
differential inputs and 12 bits of resolution in a tiny
SOT23-6 package. Conversions are performed
ratiometrically, using the power supply as the
reference voltage. The ADS1000-Q1 operates from a
single power supply ranging from 2.7 V to 5.5 V.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
Complete 12-Bit Data Acquisition System in a Tiny
SOT-23 Package
Low Current Consumption: Only 90 μA
Integral Nonlinearity: 1 LSB Max
Single-Cycle Conversion
Programmable Gain Amplifier
Gain = 1, 2, 4, or 8
128-SPS Data Rate
I2C Interface with Two Available Addresses
Power Supply: 2.7 V to 5.5 V
The ADS1000-Q1 performs conversions at a rate of
128 samples per second (SPS). The onboard
programmable gain amplifier (PGA), which offers
gains of up to 8, allows smaller signals to be
measured with high resolution. In single-conversion
mode, the ADS1000-Q1 automatically powers down
after a conversion, greatly reducing current
consumption during idle periods.
2 Applications
•
•
•
•
•
•
•
•
•
The ADS1000-Q1 is designed for applications where
space and power consumption are major
considerations. Typical applications include head
units, battery management systems, on-board
chargers, and emissions and gas sensors.
Automotive Head Units
Automotive Battery Management Systems
Automotive On-Board Chargers
HEV/EV Inverters
NOx Sensors
Soot and Particulate Matter (PM) Sensors
Oxygen (O2, Lambda, A/F) Sensors
Ammonia (NH3) Sensors
Other Emissions and Gas Sensors
Device Information(1)
PART NUMBER
ADS1000-Q1
PACKAGE
SOT-23 (6)
BODY SIZE (NOM)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Internal Block Diagram
VDD
A = 1, 2, 4, or 8
VIN+
PGA
VIN-
A/D
Converter
2
IC
Interface
SCL
SDA
Clock
Oscillator
ADS1000-Q1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS1000-Q1
SBAS480B – SEPTEMBER 2009 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 8
7.5 Programming............................................................. 9
7.6 Register Maps ......................................................... 10
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Applications ................................................ 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
Changes from Revision A (August 2010) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
VIN- VDD SDA
6
5
VIN- VDD SDA
4
6
BSKQ
1
2
4
BTMQ
3
1
2
3
VIN+ GND SCL
VIN+ GND SCL
I C address: 1001000
I C address: 1001001
2
Note:
5
2
Marking text direction indicates pin 1.
Marking text depends on I2C address; see Mechanical, Packaging, and Orderable Information.
Pin Functions
PIN
NAME
NO.
I/O
—
DESCRIPTION
GND
2
Ground
SCL
3
I
Serial Clock Line
SDA
4
I/O
Serial Data Line
VDD
5
I
Power Supply
VIN–
6
I
Negative Differential Input
VIN+
1
I
Positive Differential Input
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). (1)
MIN
MAX
UNIT
–0.3
6
V
Input current (momentary)
100
mA
Input current (continuous)
10
mA
0.3
V
VDD to GND
Voltage to GND, VIN+, VIN–
–0.3 to VDD
Voltage to GND, SDA, SCL
–0.5
Maximum junction temperature, TJ
6
V
150
°C
Operating temperature
–40
125
°C
Storage temperature
–60
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC-Q100-002
Electrostatic
discharge
V(ESD)
(1)
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification
AEC-Q100-011
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
VDD
2.7
5.5
V
VDD + 0.2
V
ANALOG INPUT
Analog input voltage
VIN+, VIN– to GND
Full-scale input voltage
(VIN+) – (VIN–)
(1)
GND – 0.2
±VDD/PGA (1)
V
Each input, VIN+ and VIN–, must meet the absolute input voltage specifications.
6.4 Thermal Information
ALD1000-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
6 PINS
RθJA
Junction-to-ambient thermal resistance
182.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
126.5
°C/W
RθJB
Junction-to-board thermal resistance
34.1
°C/W
ψJT
Junction-to-top characterization parameter
20.7
°C/W
ψJB
Junction-to-board characterization parameter
33.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
All specifications at –40°C to 125°C, VDD = 5 V, GND = 0 V, and all PGAs (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Differential input impedance
Common-mode input impedance
2.4/PGA
MΩ
8
MΩ
SYSTEM PERFORMANCE
Resolution
No missing codes
12
Data rate
104
Integral nonlinearity (INL)
Offset error
Gain error
Bits
128
184
SPS
±0.1
1
LSB
1
±2
LSB
0.01%
0.1%
DIGITAL INPUT/OUTPUT
Logic level
VIH
0.7 VDD
6
V
VIL
GND – 0.5
0.3 VDD
V
GND
0.4
V
10
μA
VOL
IOL = 3 mA
Input leakage
IIH
VIH = 5.5 V
IIL
VIL = GND
–10
Power-supply voltage
VDD
2.7
Supply current
Power-down
μA
POWER-SUPPLY REQUIREMENTS
5.5
V
0.05
2
μA
90
150
μA
VDD = 5 V
450
750
μW
VDD = 3 V
210
Active
μA
Power dissipation
μW
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6.6 Timing Requirements
FAST MODE
PARAMETER
MIN
HIGH-SPEED MODE
MAX
MIN
f(SCLK)
Bus free time between STOP and START
conditions
t(BUF)
600
160
ns
Hold time after repeated START condition
After this period, the first clock is generated.
t(HDSTA)
600
160
ns
Repeated START condition setup time
t(SUSTA)
600
160
ns
STOP condition setup time
t(SUSTO)
600
160
ns
Data hold time
t(HDDAT)
0
0
ns
Data setup time
t(SUDAT)
100
10
ns
SCLK clock low period
t(LOW)
1300
160
ns
SCLK clock high period
t(HIGH)
600
60
Clock/data fall time
tF
300
160
ns
Clock/data rise time
tR
300
160
ns
tR
3.4
UNIT
SCLK operating frequency
t(LOW)
0.4
MAX
MHz
ns
t(HDSTA)
tF
SCL
t(HDSTA)
t(HIGH)
t(HDDAT)
t(SUSTO)
t(SUSTA)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 1. I2C Timing Diagram
6
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6.7 Typical Characteristics
At TA = 25°C and VDD = 5 V, unless otherwise indicated.
Figure 3. Supply Current vs I2C Bus Frequency
Figure 2. Supply Current vs Temperature
0.04
2.0
0.03
PGA = 8
PGA = 4
PGA = 2
PGA = 1
0.0
-1.0
Gain Error (%)
Offset Error (mV)
PGA = 8
0.02
1.0
PGA = 4
PGA = 1
0.01
0.00
-0.01
-0.02
PGA = 2
-0.03
-2.0
-60
-40
-20
0
20
40
60
80
100 120 140
-0.04
-60 -40
Temperature (°C)
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Figure 4. Offset Error vs Temperature
Figure 5. Gain Error vs Temperature
Figure 6. Data Rate vs Temperature
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7 Detailed Description
7.1 Overview
The ADS1000-Q1 is a fully differential, 12-bit A/D converter. The ADS1000-Q1 allows users to obtain precise
measurements with a minimum of effort, and the device is easy to design with and configure.
The ADS1000-Q1 consists of an A/D converter core with adjustable gain, a clock generator, and an I2C interface.
Each of these blocks are described in detail in the following sections.
7.2 Functional Block Diagram
VDD
A = 1, 2, 4, or 8
VIN+
PGA
VIN-
A/D
Converter
2
IC
Interface
SCL
SDA
Clock
Oscillator
ADS1000-Q1
GND
7.3 Feature Description
7.3.1 Analog-to-Digital Converter
The ADS1000-Q1 uses a switched-capacitor input stage. To external circuitry, it looks roughly like a resistance.
The resistance value depends on the capacitor values and the rate at which they are switched. The switching
clock is generated by the onboard clock generator, so its frequency, nominally 275 kHz, is dependent on supply
voltage and temperature. The capacitor values depend on the PGA setting.
The common-mode and differential input impedances are different. For a gain setting of PGA, the differential
input impedance is typically 2.4 MΩ/PGA. The common-mode impedance is typically 8 MΩ.
7.3.2 Clock Generator
The ADS1000-Q1 features an onboard clock generator. The Typical Characteristics show variations in data rate
over supply voltage and temperature. It is not possible to operate the ADS1000-Q1 with an external clock.
7.4 Device Functional Modes
7.4.1 Operating Modes
The ADS1000-Q1 operates in one of two modes: continuous conversion and single conversion.
In continuous conversion mode, the ADS1000-Q1 continuously performs conversions. Once a conversion has
been completed, the ADS1000-Q1 places the result in the output register, and immediately begins another
conversion. When the ADS1000-Q1 is in continuous conversion mode, the ST/BSY bit in the configuration
register always reads 1.
In single conversion mode, the ADS1000-Q1 waits until the ST/BSY bit in the conversion register is set to 1.
When this happens, the ADS1000-Q1 powers up and performs a single conversion. After the conversion
completes, the ADS1000-Q1 places the result in the output register, resets the ST/BSY bit to 0 and powers
down. Writing a 1 to ST/BSY while a conversion is in progress has no effect.
When switching from continuous conversion mode to single conversion mode, the ADS1000-Q1 will complete the
current conversion, reset the ST/BSY bit to 0 and power down the device.
8
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Device Functional Modes (continued)
7.4.2 Reset and Power Up
When the ADS1000-Q1 powers up, it automatically performs a reset. As part of the reset, the ADS1000-Q1 sets
all of the bits in the configuration register to their respective default settings.
The ADS1000-Q1 responds to the I2C General Call Reset command. When the ADS1000-Q1 receives a General
Call Reset, it performs an internal reset, exactly as though it had just been powered on.
7.5 Programming
7.5.1 I2C Interface
The ADS1000-Q1 communicates through an I2C (Inter-Integrated Circuit) interface. The I2C interface is a twowire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only
drive the bus lines low, by connecting them to ground; they never drive the bus lines high. Instead, the bus wires
are pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two
devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I2C devices can act as masters or slaves, but the ADS1000-Q1 can only act as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the bit level
while SCL is low (a Low on SDA indicates the bit is 0; a High indicates the bit is 1). Once the SDA line has
settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift
register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The
master always drives the clock line. The ADS1000-Q1 never drives SCL, because it cannot act as a master. On
the ADS1000-Q1, SCL is an input only.
Most of the time the bus is idle, no communication takes place, and both lines are high. When communication
takes place, the bus is active. Only master devices can start a communication. They do this by causing a start
condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data
line changes state while the clock line is high, it is either a start condition or its counterpart, a stop condition. A
start condition is when the clock line is high and the data line goes from high to low. A stop condition is when the
clock line is high and the data line goes from low to high.
After the master issues a start condition, it sends a byte that indicates with which slave device it wants to
communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device.
Every byte transmitted on the I2C bus, whether it be address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte, eight data bits, to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a
clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA low
to acknowledge to the slave that it has finished reading the byte. It then sends a clock pulse to clock the bit.
(Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not-acknowledge because no device is
present at that address to pull the line low.
When a master has finished communicating with a slave, it may issue a stop condition. When a stop condition is
issued, the bus becomes idle again. A master may also issue another start condition. When a start condition is
issued while the bus is active, it is called a repeated start condition.
A timing diagram for an ADS1000-Q1 I2C transaction is shown in Figure 1. Timing Requirements gives the
parameters for this diagram.
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Programming (continued)
7.5.2 Output Code Calculation
The ADS1000-Q1 outputs codes in binary two’s complement format. The output code is confined to the range of
numbers: –2048 to 2047, and is given by:
æ V - VIN- ö
Output Code = 2048(PGA) ç IN+
÷
VDD
è
ø
(1)
7.5.3 ADS1000-Q1 I2C Addresses
The ADS1000-Q1 I2C address is either 1001000 or 1001001, set at the factory. The address is identified with an
A0 or an A1 within the orderable name.
The two different I2C variants are also marked differently. Devices with an I2C address of 1001000 have
packages marked BD0, while devices with an I2C address of 1001001 are marked with BD1.
7.5.4 I2C General Call
The ADS1000-Q1 responds to General Call Reset, which is an address byte of 00h followed by a data byte of
06h. The ADS1000-Q1 acknowledges both bytes.
On receiving a General Call Reset, the ADS1000-Q1 performs a full internal reset, just as though it had been
powered off and then on. If a conversion is in process, it is interrupted; the output register is set to zero, and the
configuration register returns to its default setting.
The ADS1000-Q1 always acknowledges the General Call address byte of 00h, but it does not acknowledge any
General Call data bytes other than 04h or 06h.
7.5.5 I2C Data Rates
The I2C bus operates in one of three speed modes: Standard, which allows a clock frequency of up to 100 kHz;
Fast, which allows a clock frequency of up to 400 kHz; and High-speed mode (also called Hs mode), which
allows a clock frequency of up to 3.4 MHz. The ADS1000-Q1 is fully compatible with all three modes.
No special action needs to be taken to use the ADS1000-Q1 in Standard or Fast modes, but High-speed mode
must be activated. To activate High-speed mode, send a special address byte of 00001XXX following the start
condition, where the XXX bits are unique to the Hs-capable master. This byte is called the Hs master code. (This
is different from normal address bytes; the low bit does not indicate read/write status.) The ADS1000-Q1 will not
acknowledge this byte; the I2C specification prohibits acknowledgment of the Hs master code. On receiving a
master code, the ADS1000-Q1 will switch on its High-speed mode filters, and will communicate at up to 3.4 MHz.
The ADS1000-Q1 switches out of Hs mode with the next stop condition.
For more information on High-speed mode, consult the I2C specification.
7.6 Register Maps
The ADS1000-Q1 has two registers that are accessible through its I2C port. The output register contains the
result of the last conversion; the configuration register allows users to change the ADS1000-Q1 operating mode
and query the status of the device.
10
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Register Maps (continued)
7.6.1 Output Register
The 16-bit output register contains the result of the last conversion in binary two’s complement format. Because
the port yields 12 bits of data, the ADS1000-Q1 outputs right-justified and sign-extended codes. This format
makes it possible to perform averaging using a 16-bit accumulator. The output register format is shown in
Figure 7.
Following reset or power up, the output register is set to 0; it remains zero until the first conversion is completed.
Therefore, if a user reads the ADS1000-Q1 just after reset or power up, the output register will read 0.
Figure 7. Output Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15 (1)
D14 (1)
D13 (1)
D12 (1)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
D15–D12 are sign extensions of 12-bit data.
7.6.2 Configuration Register
A user controls the ADS1000-Q1 operating mode and PGA settings through the 8-bit configuration register. The
configuration register format is shown in Figure 8. The default setting is 80H.
Figure 8. Configuration Register
7
6
ST/BSY
5
4
Reserved
3
SC
2
Reserved
1
0
PGA1
PGA0
Table 1. Configuration Register Field Descriptions
BIT
7
FIELD
TYPE
RESET
DESCRIPTION
ST/BSY
RW
1
The meaning of the ST/BSY bit depends on whether it is being
written to or read from.
In single conversion mode, writing a 1 to the ST/BSY bit causes
a conversion to start, and writing a 0 has no effect. In continuous
conversion mode, the ADS1000-Q1 ignores the value written to
ST/BSY.
When read in single conversion mode, ST/BSY indicates
whether the A/D converter is busy taking a conversion. If
ST/BSY is read as 1, the A/D converter is busy, and a
conversion is taking place; if 0, no conversion is taking place,
and the result of the last conversion is available in the output
register.
In continuous mode, ST/BSY is always read as 1.
6-5
4
3-2
Reserved
R
SC
00
0
Reserved
R
SC controls whether the ADS1000-Q1 is in continuous
conversion or single conversion mode. When SC is 1, the
ADS1000-Q1 is in single conversion mode; when SC is 0, the
ADS1000-Q1 is in continuous conversion mode.
00
1
PGA1
0
Bits 1 and 0 control the ADS1000-Q1 gain setting; see Table 2.
0
PGA0
0
Bits 1 and 0 control the ADS1000-Q1 gain setting; see Table 2.
Table 2. PGA Bits
PGA1
PGA0
GAIN
0(1)
0(1)
1(1)
0
1
2
1
0
4
1
1
8
(1) Default setting
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7.6.3 Reading From the ADS1000-Q1
A user can read the output register and the contents of the configuration register from the ADS1000-Q1. To do
this, address the ADS1000-Q1 for reading, and read three bytes from the device. The first two bytes are the
output register contents; the third byte is the configuration register contents.
A user does not always have to read three bytes from the ADS1000-Q1. If only the contents of the output
register are needed, read only two bytes.
Reading more than three bytes from the ADS1000-Q1 has no effect. All of the bytes beginning with the fourth
byte will be FFh. See Figure 9 for a timing diagram of an ADS1000-Q1 read operation.
7.6.4 Writing to the ADS1000-Q1
A user can write new contents into the configuration register (the contents of the output register cannot change).
To do this, address the ADS1000-Q1 for writing, and write one byte to it. This byte is written into the
configuration register.
Writing more than one byte to the ADS1000-Q1 has no effect. The ADS1000-Q1 ignores any bytes sent to it after
the first one, and will only acknowledge the first byte. See Figure 10 for a timing diagram of an ADS1000-Q1
write operation.
9
1
9
1
···
SCL
SDA
1
0
0
1
A2
A1
R/W
A0
Start By
Master
D15
D14
ACK By
ADS1000
2
SDA
(Continued)
···
9
D7
D6
D5
D4
D3
D2
D11 D10
D9
···
D8
ACK By
Master
Frame 2: Output Register Upper Byte
1
···
D12
From
ADS1000
Frame 1: I C Slave Address Byte
SCL
(Continued)
D13
D1
1
ST/
BSY
D0
From
ADS1000
9
0
0
SC
ACK By
Master
0
0
PGA1 PGA0
ACK By
Master
From
ADS1000
Frame 3: Output Register Lower Byte
Stop By
Master
Frame 4: Configuration Register
(Optional)
Figure 9. Timing Diagram for Reading from the ADS1000-Q1
1
9
1
9
SCL
1
SDA
0
0
1
A2
A1
A0
Start By
Master
R/W
ST/
BSY
0
0
SC
0
0
PGA1 PGA0
ACK By
ADS1000
2
Frame 1: I C Slave Address Byte
ACK By
ADS1000
Stop By
Master
Frame 2: Configuration Register
Figure 10. Timing Diagram for Writing to the ADS1000-Q1
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The following sections give example circuits and suggestions for using the ADS1000-Q1 in various situations.
8.1.1 Basic Connections
For many applications, connecting the ADS1000-Q1 is extremely simple. A basic connection diagram for the
ADS1000-Q1 is shown in Figure 11.
The fully differential voltage input of the ADS1000-Q1 is ideal for connection to differential sources with
moderately low source impedance, such as bridge sensors and thermistors. Although the ADS1000-Q1 can read
bipolar differential signals, it cannot accept negative voltages on either input. It may be helpful to think of the
ADS1000-Q1 positive voltage input as noninverting, and of the negative input as inverting.
When the ADS1000-Q1 is converting, it draws current in short spikes. The 0.1-μF bypass capacitor supplies the
momentary bursts of extra current needed from the supply.
The ADS1000-Q1 interfaces directly to standard mode, fast mode, and high-speed mode I2C controllers. Any
microcontroller I2C peripheral, including master-only and non-multiple-master I2C peripherals, will work with the
ADS1000-Q1. The ADS1000-Q1 does not perform clock-stretching (that is, it never pulls the clock line low), so it
is not necessary to provide for this unless other devices are on the same I2C bus.
Pullup resistors are necessary on both the SDA and SCL lines because I2C bus drivers are open-drain. The size
of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
consume less power, but increase the transition times on the bus, limiting the bus speed. Lower-value resistors
allow higher speed at the expense of higher power consumption. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. The resistors should not be too small; if they are, the bus drivers
may not be able to pull the bus lines low.
Positive Input
(0V to 5V)
Negative Input
(0V to 5V)
2
I C Pull-Up Resistors
1kW to 10kW (typ.)
VDD
ADS1000-Q1
Microcontroller or
Microprocessor
VDD
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
2
with I C Port
SCL
4.7µF (typ.)
SDA
Figure 11. Typical Connections of the ADS1000-Q1
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Application Information (continued)
8.1.1.1 Connecting Multiple Devices
Connecting two ADS1000-Q1 devices to a single bus is almost trivial. An example showing two ADS1000-Q1
devices and one ADS1100 connected on a single bus is shown in Figure 12. Multiple devices can be connected
to a single bus (provided that their addresses are different).
Only one set of pullup resistors is needed per bus. A user might find that he or she needs to lower the pullup
resistor values slightly to compensate for the additional bus capacitance presented by multiple devices and
increased line length.
2
I C Pull-Up Resistors
1kW to 10kW (typ.)
VDD
ADS1000A0
Microcontroller or
Microprocessor
1
VIN+
VIN-
6
with I C Port
2
GND
VDD
5
SCL
3
SCL
SDA
4
2
SDA
ADS1000A1
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
ADS1100A2
NOTE: ADS1000 power
and input connections
omitted for clarity.
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
Figure 12. Connecting Multiple ADS1000-Q1 Devices
8.1.1.2 Using GPIO Ports For I2C
Most microcontrollers have programmable input and output pins that can be set in software to act as inputs or
outputs. If an I2C controller is not available, the ADS1000-Q1 can be connected to GPIO pins, and the I2C bus
protocol simulated, or bit-banged, in software. An example of this for a single ADS1000-Q1 is shown in
Figure 13.
VDD
ADS1000-Q1
Microcontroller or
Microprocessor
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
2
with I C Port
SCL
SDA
NOTE: ADS1000-Q1 power
and input connections
omitted for clarity.
Figure 13. Using GPIO With a Single ADS1000-Q1
14
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Application Information (continued)
Bit-banging I2C with GPIO pins can be done by setting the GPIO line to zero and toggling it between input and
output modes to apply the proper bus states. To drive the line low, the pin is set to output a 0; to let the line go
high, the pin is set to input. When the pin is set to input, the state of the pin can be read; if another device is
pulling the line low, this device will read as a 0 in the port input register.
No pullup resistor is shown on the SCL line. In this simple case, the resistor is not needed; the microcontroller
can simply leave the line on output, and set it to 1 or 0 as appropriate. It can do this because the ADS1000-Q1
never drives its clock line low. This technique can also be used with multiple devices, and has the advantage of
lower current consumption resulting from the absence of a resistive pullup.
If there are any devices on the bus that may drive their clock lines low, the above method should not be used;
the SCL line should be high-Z or zero and a pullup resistor provided as usual. Note also that this cannot be done
on the SDA line in any case, because the ADS1000-Q1 does drive the SDA line low from time to time, as all I2C
devices do.
Some microcontrollers have selectable strong pullup circuits built into the GPIO ports. In some cases, these can
be switched on and used in place of an external pullup resistor. Weak pullup resistors are also provided on some
microcontrollers, but usually these are too weak for I2C communication. If there is any doubt about the matter,
test the circuit before committing it to production.
8.1.1.3 Single-Ended Inputs
Although the ADS1000-Q1 has a fully differential input, it can easily measure single-ended signals. A simple
single-ended connection scheme is shown in Figure 14. The ADS1000-Q1 is configured for single-ended
measurement by grounding either of its input pins, usually VIN–, and applying the input signal to VIN+. The singleended signal can range from –0.2 V to VDD + 0.3 V. The ADS1000-Q1 loses no linearity anywhere in its input
range. Negative voltages cannot be applied to this circuit because the ADS1000-Q1 inputs can only accept
positive voltages.
VDD
0V - VDD
Single-Ended
Filter Capacitor
33pF to 100pF
(typ.)
ADS1000-Q1
1
VIN+
VIN-
6
2
GND
VDD
5
3
SCL
SDA
4
Output
Codes
0 - 2048
Figure 14. Measuring Single-Ended Inputs
The ADS1000-Q1 input range is bipolar differential with respect to the reference, that is, ±VDD. The single-ended
circuit shown in Figure 14 covers only half the ADS1000-Q1 input scale because it does not produce differentially
negative inputs; therefore, one bit of resolution is lost. The DRV134 balanced line driver can be employed to
regain this bit for single-ended signals.
Negative input voltages must be level-shifted. A good candidate for this function is the THS4130 differential
amplifier, which can output fully differential signals. This device can also help recover the lost bit noted previously
for single-ended positive signals. Level-shifting can also be performed using the DRV134.
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8.2 Typical Applications
8.2.1 ADS1000-Q1 with Current Shunt Monitor
3.3 V
Shunt
Resistor
Load
4.7 µF
3.3 V
INA213-Q1
REF
IN+
VIN-
I2C
ADS1000-Q1
+
OUT
VIN+
IN-
Figure 15. Current Shunt Monitor Application
8.2.1.1 Design Requirements
For this design example, the ADS1000-Q1 is paired with a current shunt monitor. Bidirectional current monitoring
is required when there is both charging and discharging. The requirements for this example are:
• Voltage across current shunt varies from –15 mV to 15 mV
• 3.3-V supply
• 1-V rail available as reference
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Part Selection
The INA213A-Q1 is chosen because of its low offset and zero drift. The ADS1000-Q1 has a low noise floor, so it
can support more of the gain. For this reason, the lowest gain option was chosen from the INA21x-Q1 family.
The INA213A-Q1 has a gain of 50.
8.2.1.2.1.1 Gain Settings
First, determine what the full-scale differential range will be into the ADS1000-Q1 device.
Vfs = VINdiff × GINA213
Vfs = ±15 mV × 50
Vfs = ±0.75 V
(2)
(3)
(4)
By looking at the recommended full-scale input voltage, it can be determined that a gain of 4 will satisfy the
conditions.
Vfs ≤ ±VDD / PGA
Vfs ≤ ±3.3 V / 4
Vfs ≤ ±0.825 V
16
(5)
(6)
(7)
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Typical Applications (continued)
8.2.1.2.1.2 Circuit Implementation
Because the ADS1000-Q1 has a differential input, it is helpful to connect the reference voltage of the INA213AQ1 to the negative input terminal of the ADS1000-Q1. Because bidirectional current sensing is required in this
application, VREF must be chosen so that:
VREF > Vfs / 2
VREF < Vsupply – Vfs / 2
(8)
where
•
Vfs = 1.5 V
(9)
A 1-V reference works for this example. Because the ADS1000-Q1 is a differential input ADC, a resistive divider
could be used to generate the reference voltage because impedance effects on the INA213-Q1 will be canceled
out by the ADS1000-Q1. When using a single-ended ADC with the INA213A-Q1, TI does not recommend using a
voltage divider to generate the reference voltage.
8.2.1.3 Application Curve
2500
2000
ADC Output Code
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
-0.02 -0.015 -0.01 -0.005
0
0.005 0.01 0.015
Differential Input Voltage to INA213-Q1 (V)
0.02
D001
Figure 16. Input Voltage vs ADC Code in Bidirectional Current Sensing Application
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Typical Applications (continued)
8.2.2 Low-Side Current Measurement
11.5 kW
5V
V
5V
FS = 0.63 V
Load
OPA333-Q1
(1)
RS
(2)
R3
ADS1000-Q1
49.9 k W
1 kW
G = 12.5
-5 V
2
IC
(PGA Gain = 8)
5 V FS
Figure 17. Low-Side Current Measurement Schematic
8.2.2.1 Design Requirements
Figure 17 shows a circuit for a low-side shunt-type current monitor. The circuit reads the voltage across a shunt
resistor, which is sized as small as possible while still giving a readable output voltage. This voltage is amplified
by an OPA333-Q1 low-drift operational amplifier, and the result is read by the ADS1000-Q1. The maximum
voltage across the current shunt is 50mV. This design uses a 5-V power supply.
8.2.2.2 Detailed Design Procedure
TI recommends that the ADS1000-Q1 be operated at a gain of 8. The gain of the OPA333-Q1 can then be set
lower. For a gain of 8, the operational amplifier should be configured to give a maximum output voltage of no
greater than 0.75 V. If the shunt resistor is sized to provide a maximum voltage drop of 50 mV at full-scale
current, the full-scale input to the ADS1000-Q1 is 0.63 V.
18
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9 Power Supply Recommendations
The ADS1000-Q1 is fabricated in a small-geometry low-voltage process. The analog inputs feature protection
diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS1000-Q1
can be permanently damaged by analog input voltages that remain more than approximately 300-mV beyond the
rails for extended periods. One way to protect against overvoltage is to place current-limiting resistors on the
input lines. The ADS1000-Q1 analog inputs can withstand momentary currents of as large as 10 mA.
The previous paragraph does not apply to the I2C ports, which can both be driven to 6 V regardless of the
supply.
If the ADS1000-Q1 is driven by an operational amplifier with high voltage supplies, such as ±12 V, protection
should be provided, even if the operational amplifier is configured so that it will not output out-of-range voltages.
Many operational amplifiers seek to one of the supply rails immediately when power is applied, usually before the
input has stabilized; this momentary spike can damage the ADS1000-Q1. Sometimes this damage is incremental
and results in slow, long-term failure—which can be disastrous for permanently installed, low-maintenance
systems.
If using an operational amplifier or other front-end circuitry with the ADS1000-Q1, be sure to take the
performance characteristics of this circuitry into account; a chain is only as strong as its weakest link.
Any data converter is only as good as its reference. For the ADS1000-Q1, the reference is the power supply, and
the power supply must be clean enough to achieve the desired performance. If a power-supply filter capacitor is
used, it should be placed close to the VDD pin, with no vias placed between the capacitor and the pin. The trace
leading to the pin should be as wide as possible, even if it must be necked down at the device.
10 Layout
10.1 Layout Guidelines
An optimum layout for the ADS1000-Q1 helps to reduce noise and improve performance. The decoupling
capacitor on VDD should be placed as close to the VDD pin as possible. Also, the analog input pins (VIN+ and
VIN-) should be routed carefully to reduce noise.
10.2 Layout Example
Place power
supply capacitor as
close as possible
to VDD pin
To VDD
supply
Via to
ground plane
VIN+
VIN-
GND
VDD
SCL
SDA
Via to
ground plane
Copper trace/pour
Figure 18. ADS1000-Q1 Layout Recommendation
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors, Inc.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS1000A0QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BSKQ
ADS1000A1QDBVRQ1
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BTMQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1000-Q1 :
• Catalog: ADS1000
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
ADS1000A0QDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
ADS1000A1QDBVRQ1
SOT-23
DBV
6
3000
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
3.1
1.39
4.0
8.0
Q3
3.2
3.1
1.39
4.0
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS1000A0QDBVRQ1
SOT-23
DBV
6
3000
210.0
185.0
35.0
ADS1000A1QDBVRQ1
SOT-23
DBV
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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