ON MC74ACT161D Synchronous presettable binary counter Datasheet

MC74AC161, MC74ACT161,
MC74AC163, MC74ACT163
Synchronous Presettable
Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are
high−speed synchronous modulo−16 binary counters. They are
synchronously presettable for application in programmable dividers
and have two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multistage counters.
The MC74AC161/74ACT161 has an asynchronous Master Reset
input that overrides all other inputs and forces the outputs LOW. The
MC74AC163/74ACT163 has a Synchronous Reset input that
overrides counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
•
•
•
•
•
w
Synchronous Counting and Loading
High−Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
′ACT161 and ′ACT163 Have TTL Compatible Inputs
TC
Q0
Q1
Q2
Q3
CET
PE
16
15
14
13
12
11
10
9
DIP−16
N SUFFIX
CASE 648
16
1
16
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
VCC
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16
1
1
SO−16
D SUFFIX
CASE 751B
EIAJ−16
M SUFFIX
CASE 966
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
1
2
3
4
5
6
7
8
DEVICE MARKING INFORMATION
*R
CP
P0
P1
P2
P3
CEP
GND
See general marking information in the device marking
section on page 11 of this data sheet.
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
FUNCTION
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
(′161) Asynchronous Master Reset Input
SR
(′163) Synchronous Reset Input
P0−P3
Parallel Data Inputs
PE
Parallel Enable Input
Q0 −Q3
Flip−Flop Outputs
TC
Terminal Count Output
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 7
1
Publication Order Number:
MC74AC161/D
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
operation, as shown in the Mode Select Table. A LOW
signal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on SR overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (Pn) inputs to be loaded into the flip−flops on the next
rising edge of CP. With PE and MR (′161) or SR (′163)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
The MC74AC161/ACT161 and MC74AC163/ACT163 use
D−type edge−triggered flip−flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the MC74AC568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or
asynchronous reset for flip−flops, counters or registers.
Logic Equations:
Count Enable = CEP•CET•PE
TC = Q0•Q1•Q2•Q3•CET
PE P0 P1 P2 P3
CEP
CET
TC
CP
*R Q0 Q1 Q2 Q3
*MR for ′161
*SR for ′163
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
The MC74AC161/ACT161 and MC74AC163/ACT163
count modulo−16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip−flops are driven in parallel through a clock buffer. Thus
all changes of the Q outputs (except due to Master Reset of
the ′161) occur as a result of, and synchronous with, the
LOW−to−HIGH transition of the CP input signal. The
circuits have four fundamental modes of operation, in order
of precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count−up and hold. Five control inputs
− Master Reset (MR, ′161), Synchronous Reset (SR, ′163),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) − determine the mode of
MODE SELECT TABLE
0
*SR
PE
CET
CEP
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Action on the Rising
Clock Edge ( )
Reset (Clear)
Load (Pn → Qn)
Count (Increment)
No Change (Hold)
No Change (Hold)
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
*For ′163 only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Figure 3. State Diagram
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2
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
P0
P1
P2
P3
PE
′163
′161
CEP
CET
′163
ONLY
TC
CP
CP
′161
ONLY
CP
D
CD
CP
Q
Q0
D
Q
Q0
DETAIL A
DETAIL A
DETAIL A
Q1
Q2
Q3
DETAIL A
MR ′161
SR ′163
Q0
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 4. Logic Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
−0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC VCC or GND Current per Output Pin
±50
mA
Tstg
Storage Temperature
−65 to +150
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Supply Voltage
VIN, VOUT
DC Input Voltage, Output Voltage (Ref. to GND)
tr, tf
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
Min
Typ
Max
Unit
′AC
2.0
5.0
6.0
′ACT
4.5
5.0
5.5
0
−
VCC
VCC @ 3.0 V
−
150
−
VCC @ 4.5 V
−
40
−
VCC @ 5.5 V
−
25
−
VCC @ 4.5 V
−
10
−
VCC @ 5.5 V
−
8.0
−
−
−
140
°C
−40
25
85
°C
V
V
ns/V
tr, tf
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
TJ
Junction Temperature (PDIP)
TA
Operating Ambient Temperature Range
IOH
Output Current − High
−
−
−24
mA
IOL
Output Current − Low
−
−
24
mA
ns/V
1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74AC
74AC
TA = +25°C
TA =
−40°C to
+85°C
Typ
Unit
Conditions
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
5.5
−
±0.1
5.5
−
5.5
5.5
VOL
Maximum Low Level
Output Voltage
IIN
Maximum Input
Leakage Current
IOLD
†Minimum Dynamic
Output Current
IOHD
ICC
Maximum Quiescent
Supply Current
V
*VIN = VIL or VIH
−12 mA
IOH
−24 mA
−24 mA
IOUT = 50 mA
V
*VIN = VIL or VIH
12 mA
IOL
24 mA
24 mA
±1.0
mA
VI = VCC, GND
−
75
mA
VOLD = 1.65 V Max
−
−
−75
mA
VOHD = 3.85 V Min
−
8.0
80
mA
VIN = VCC or GND
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.
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V
IOUT = −50 mA
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC161
74AC161
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Count
Frequency
3.3
5.0
70
110
111
167
−
−
60
95
−
−
MHz
3−3
tPLH
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
3.3
5.0
2.0
1.5
7.0
5.0
12.0
9.0
1.5
1.0
13.5
9.5
ns
3−6
tPHL
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
3.3
5.0
1.5
1.5
7.0
5.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
3−6
tPLH
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.0
6.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
3−6
tPHL
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
8.5
6.5
14.0
11.0
2.5
2.0
15.5
11.5
ns
3−6
tPLH
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
5.5
3.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
3−6
tPHL
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
6.5
5.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
3−6
tPHL
Propagation Delay
MR to Qn
3.3
5.0
2.0
1.5
6.0
5.5
12.0
9.5
1.5
1.5
13.5
10.0
ns
3−6
tPHL
Propagation Delay
MR to TC
3.3
5.0
3.5
2.5
10.0
8.5
15.0
13.0
3.0
2.5
17.5
13.5
ns
3−6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74AC163
74AC163
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Count
Frequency
3.3
5.0
70
110
95
140
−
−
60
95
−
−
MHz
3−3
tPLH
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
3.3
5.0
2.0
1.5
7.5
5.5
12.5
9.0
1.5
1.0
13.5
9.5
ns
3−6
tPHL
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
3.3
5.0
1.5
1.5
8.5
6.0
12.0
9.5
1.5
1.5
13.0
10.0
ns
3−6
tPLH
Propagation Delay
CP to TC
3.3
5.0
3.0
2.0
9.5
7.0
15.0
10.5
2.5
1.5
16.5
11.5
ns
3−6
tPHL
Propagation Delay
CP to TC
3.3
5.0
3.5
2.0
11.0
8.0
14.0
11.0
2.5
2.0
15.5
11.5
ns
3−6
tPLH
Propagation Delay
CET to TC
3.3
5.0
2.0
1.5
7.5
5.5
9.5
6.5
1.5
1.0
11.0
7.5
ns
3−6
tPHL
Propagation Delay
CET to TC
3.3
5.0
2.5
2.0
8.5
6.0
11.0
8.5
2.0
1.5
12.5
9.5
ns
3−6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74AC161
74AC161
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
3.3
5.0
6.0
3.5
13.5
8.5
16.0
10.5
ns
3−9
th
Hold Time, HIGH or LOW
Pn to CP
3.3
5.0
−7.0
−4.0
−1.0
0
−0.5
0
ns
3−9
ts
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
6.5
4.0
11.5
7.5
14.0
8.5
ns
3−9
th
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
−6.0
−3.5
0
0.5
0
1.0
ns
3−9
ts
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.0
2.0
6.0
4.5
7.0
5.0
ns
3−9
th
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
−3.5
−2.0
0
0
0
0.5
ns
3−9
tw
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
2.0
2.0
3.5
2.5
4.0
3.0
ns
3−6
tw
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
2.0
2.0
4.0
3.0
4.5
3.5
ns
3−6
tw
MR Pulse Width, LOW
3.3
5.0
3.0
2.5
5.5
4.5
7.5
6.0
ns
3−6
trec
Recovery TIme
MR to CP
3.3
5.0
−2.0
−1.0
−0.5
0
0
0.5
ns
3−9
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
Typ
74AC163
74AC163
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
3.3
5.0
5.5
4.0
13.5
8.5
16.0
10.5
ns
3−9
th
Hold Time, HIGH or LOW
Pn to CP
3.3
5.0
−7.0
−5.0
−1.0
0
−0.5
0
ns
3−9
ts
Setup Time, HIGH or LOW
SR to CP
3.3
5.0
5.5
4.0
14
9.5
16.5
11.0
ns
3−9
th
Hold Time, HIGH or LOW
SR to CP
3.3
5.0
−7.5
−5.5
−1.0
−0.5
−0.5
0
ns
3−9
ts
Setup Time, HIGH or LOW
PE to CP
3.3
5.0
5.5
4.0
11.5
7.5
14.0
8.5
ns
3−9
th
Hold Time, HIGH or LOW
PE to CP
3.3
5.0
−7.5
−5.0
−1.0
−0.5
−0.5
0
ns
3−9
ts
Setup Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
3.5
2.5
6.0
4.5
7.0
5.0
ns
3−9
th
Hold Time, HIGH or LOW
CEP or CET to CP
3.3
5.0
−4.5
−3.0
0
0
0
0.5
ns
3−9
tw
Clock Pulse Width (Load)
HIGH or LOW
3.3
5.0
3.0
2.0
3.5
2.5
4.0
3.0
ns
3−6
tw
Clock Pulse Width (Count)
HIGH or LOW
3.3
5.0
3.0
2.0
4.0
3.0
4.5
3.5
ns
3−6
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
DC CHARACTERISTICS
Symbol
Parameter
VCC
(V)
74ACT
74ACT
TA = +25°C
TA =
−40°C to
+85°C
Typ
Guaranteed Limits
Unit
Conditions
VIH
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
VOUT = 0.1 V
or VCC − 0.1 V
VIL
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
VOUT = 0.1 V
or VCC − 0.1 V
VOH
Minimum High Level
Output Voltage
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
V
4.5
5.5
−
−
3.86
4.86
3.76
4.76
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
4.5
5.5
−
−
0.36
0.36
0.44
0.44
V
*VIN = VIL or VIH
24 mA
IOL
24 mA
VOL
Maximum Low Level
Output Voltage
V
V
IOUT = −50 mA
*VIN = VIL or VIH
−24 mA
IOH
−24 mA
IOUT = 50 mA
IIN
Maximum Input
Leakage Current
5.5
−
±0.1
±1.0
mA
VI = VCC, GND
DICCT
Additional Max. ICC/Input
5.5
0.6
−
1.5
mA
VI = VCC − 2.1 V
IOLD
†Minimum Dynamic
Output Current
5.5
−
−
75
mA
VOLD = 1.65 V Max
5.5
−
−
−75
mA
VOHD = 3.85 V Min
5.5
−
8.0
80
mA
VIN = VCC or GND
IOHD
ICC
Maximum Quiescent
Supply Current
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74ACT161
74ACT161
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Count
Frequency
5.0
115
125
−
100
−
MHz
3−3
tPLH
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
5.0
1.5
8.0
9.5
1.5
10.5
ns
3−6
tPHL
Propagation Delay
CP or Qn (PE Input HIGH or LOW)
5.0
1.5
8.0
10.5
1.5
11.5
ns
3−6
tPLH
Propagation Delay
CP to TC
5.0
2.0
11.0
11.0
1.5
12.5
ns
3−6
tPHL
Propagation Delay
CP to TC
5.0
1.5
11.0
12.5
1.5
13.5
ns
3−6
tPLH
Propagation Delay
CET to TC
5.0
1.5
7.5
8.5
1.5
10.0
ns
3−6
tPHL
Propagation Delay
CET to TC
5.0
1.5
8.0
9.5
1.5
10.5
ns
3−6
tPHL
Propagation Delay
MR to Qn
5.0
1.5
8.0
10.0
1.5
11.0
ns
3−6
tPHL
Propagation Delay
MR to TC
5.0
2.5
10.0
13.5
2.0
14.5
ns
3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
VCC*
(V)
Parameter
74ACT163
74ACT163
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Min
Typ
Max
Min
Max
Unit
Fig.
No.
fmax
Maximum Count
Frequency
5.0
120
140
−
105
−
MHz
3−3
tPLH
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
5.0
1.5
5.5
10.0
1.5
11.0
ns
3−6
tPHL
Propagation Delay
CP to Qn (PE Input HIGH or LOW)
5.0
1.5
6.0
11.0
1.5
12.0
ns
3−6
tPLH
Propagation Delay
CP to TC
5.0
2.5
7.0
11.5
2.0
13.5
ns
3−6
tPHL
Propagation Delay
CP to TC
5.0
3.0
8.0
13.5
2.0
15.0
ns
3−6
tPLH
Propagation Delay
CET to TC
5.0
2.0
5.5
9.0
1.5
10.5
ns
3−6
tPHL
Propagation Delay
CET to TC
5.0
2.0
6.0
10.0
2.0
11.0
ns
3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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9
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
Symbol
Parameter
VCC*
(V)
Typ
74ACT161
74ACT161
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
5.0
7.0
9.5
11.5
ns
3−9
th
Hold Time, HIGH or LOW
Pn to CP
5.0
−3.0
0
0
ns
3−9
ts
Setup Time, HIGH or LOW
PE to CP
5.0
6.0
8.5
9.5
ns
3−9
th
Hold Time, HIGH or LOW
PE to CP
5.0
−3.5
− 0.5
− 0.5
ns
3−9
ts
Setup Time, HIGH or LOW
CEP or CET to CP
5.0
4.0
5.5
6.5
ns
3−9
th
Hold Time, HIGH or LOW
CEP or CET to CP
5.0
−2.0
0
0
ns
3−9
tw
Clock Pulse Width (Load)
HIGH or LOW
5.0
2.0
3.0
3.5
ns
3−6
tw
Clock Pulse Width (Count)
HIGH or LOW
5.0
2.0
3.0
3.5
ns
3−6
tw
MR Pulse Width, LOW
5.0
3.0
3.0
7.5
ns
3−6
trec
Recovery Time
MR to CP
5.0
0
0
0.5
ns
3−9
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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10
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC OPERATING REQUIREMENTS
Symbol
VCC*
(V)
Parameter
74ACT163
74ACT163
TA = +25°C
CL = 50 pF
TA = −40°C
to +85°C
CL = 50 pF
Typ
Unit
Fig.
No.
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
5.0
4.0
10.0
12.0
ns
3−9
th
Hold Time, HIGH or LOW
Pn to CP
5.0
−5.0
0.5
0.5
ns
3−9
ts
Setup Time, HIGH or LOW
SR to CP
5.0
4.0
10.0
11.5
ns
3−9
th
Hold Time, HIGH or LOW
SR to CP
5.0
−5.5
−0.5
−0.5
ns
3−9
ts
Setup Time, HIGH or LOW
PE to CP
5.0
4.0
8.5
10.5
ns
3−9
th
Hold Time, HIGH or LOW
PE to CP
5.0
−5.5
−0.5
0
ns
3−9
ts
Setup Time, HIGH or LOW
CEP or CET to CP
5.0
2.5
5.5
6.5
ns
3−9
th
Hold Time, HIGH or LOW
CEP or CET to CP
5.0
−3.0
0
0.5
ns
3−9
tw
Clock Pulse Width
HIGH or LOW
5.0
2.0
3.5
3.5
ns
3−6
tw
Clock Pulse Width (Count)
HIGH or LOW
5.0
2.0
3.5
3.5
ns
3−6
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Parameter
Value
Typ
Unit
Test Conditions
CIN
Input Capacitance
4.5
pF
VCC = 5.0 V
CPD
Power Dissipation Capacitance
45
pF
VCC = 5.0 V
MARKING DIAGRAMS
DIP−16
SO−16
EIAJ−16
MC74AC16xN
AWLYYWW
AC16x
AWLYWW
74AC16x
ALYW
MC74ACT16xN
AWLYYWW
ACT16x
AWLYWW
74ACT16x
ALYW
x
A
WL, L
YY, Y
WW, W
= 1 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
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11
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
ORDERING INFORMATION
Device
Package
Shipping
MC74AC161N
PDIP−16
25 Units/Rail
MC74ACT161N
PDIP−16
25 Units/Rail
MC74AC161D
SOIC−16
48 Units/Rail
MC74AC161DR2
SOIC−16
2500 Tape & Reel
MC74ACT161D
SOIC−16
48 Units/Rail
MC74ACT161DR2
SOIC−16
2500 Tape & Reel
MC74AC161M
EIAJ−16
50 Units/Rail
MC74ACT161MEL
EIAJ−16
2000 Tape & Reel
MC74AC163N
PDIP−16
25 Units/Rail
MC74ACT163N
PDIP−16
25 Units/Rail
MC74AC163D
SOIC−16
48 Units/Rail
MC74AC163DR2
SOIC−16
2500 Tape & Reel
MC74ACT163D
SOIC−16
48 Units/Rail
MC74ACT163DR2
SOIC−16
2500 Tape & Reel
MC74AC163MEL
EIAJ−16
2000 Tape & Reel
MC74ACT163MEL
EIAJ−16
2000 Tape & Reel
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12
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
16 PIN PLASTIC DIP PACKAGE
CASE 648−08
ISSUE R
−A−
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
SEATING
PLANE
−T−
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO−16
D SUFFIX
16 PIN PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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13
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
PACKAGE DIMENSIONS
EIAJ−16
M SUFFIX
16 PIN PLASTIC EIAJ PACKAGE
CASE966−01
ISSUE O
16
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−−
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−−
0.031
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
Notes
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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MC74AC161/D
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