M52036SP SYNC SIGNAL PROCESSOR REJ03F0086-0100Z Rev.1.0 Sep.22.2003 Description The M52036SP is a semiconductor integrated circuit for the automatic selection and rectification of sync waveforms. The IC operates with synchronizing signals in three forms, that is, separate sync(positive or negative polarity, 1 to 5 Vp-p), composite sync (positive or negative polarity, 1 to 5 Vp-p), and synchronous video (negative sync). This IC is optimal for processing sync signals for multi-scan-type displays. Features • Indicates the presence or absence of synchronizing-signal input and the polarities of the signals • Pulse-output circuit is for open-collector output • Clamp-pulse output and Clamp-pulse trigger is generated at the front edge for separate sync and composite sync input, and at the rear edge for sync on video input. • 20-pin shrink-DIP Application • Display Monitor Recommended Operating Condition • Supply voltage range: 11 to 13 V • Rated supply voltage: 12 V Block Diagram Rev.1.0, Sep.22.2003, page 1 of 13 M52036SP Pin Functions Absolute Maximum Rating Item Symbol Rated values Units Supply voltage Vcc 14.0 V Power dissipation Operating ambient temperature Storing temperature Pd Topr Tstg 1000 –20 to 85 –40 to 150 mW °C °C Rev.1.0, Sep.22.2003, page 2 of 13 M52036SP Electrical Characteristics (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 3 of 13 M52036SP Electrical Characteristics (cont.) (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 4 of 13 M52036SP Electrical Characteristics (cont.) (Ta = 25°C Vcc = 12 V, VDD = Open) Rev.1.0, Sep.22.2003, page 5 of 13 M52036SP Test Circuit Rev.1.0, Sep.22.2003, page 6 of 13 M52036SP Logic Table Table.1 Decoder Logic Output Input to pin 6 HD.COMP HD. COMP. (POS) HD. COMP. (POS) HD. COMP. (POS) HD. COMP. (NEG) HD. COMP. (NEG) HD. COMP. (NEG) NON NON NON Input to pin 8 VD NON VD (POS) VD (NEG) NON VD (POS) VD (NEG) NON VD (POS) VD (NEG) Output pins 1 2 18 19 H H H H H H L L L L H H L H H L H H L L L H H H L L L L L H L L H L L H Table.2 Allowable Amplitude of Input Voltage Amplitude of input to pin 4 Amplitude of input to pin 6 Amplitude of input to pin 8 Table.3 Output Priority Input signals (pin) 4 pin 6 pin 8 pin Ο Ο Ο Ο × × × × × × Ο Ο × × Ο Ο × Ο × Ο × Ο × Ο Rev.1.0, Sep.22.2003, page 7 of 13 Output signals (pin) 13 pin 14 pin 15 pin 4 11 6 11 4 8 6 8 × × 6 11 × 8 6 8 17 pin 4 6 4 6 × 6 × 6 M52036SP Table.4 Pulse Duty Ratio for Allowable Maximum Input Signal Input Pulse to Pin 6 (HD.COMP.) FH = 16 kHz Maximum voltage amplitude (VP-P) 1.0 3.3 4.0 5.0 POS. % 15.0 13.8 11.2 9.0 NEG. Time (µs) % Time (µs) 9.38 15.0 9.38 8.63 13.0 8.13 7.00 10.5 6.56 8.63 8.8 5.50 Maximum voltage amplitude (VP-P) 1.0 3.3 4.0 5.0 POS. % 14.1 12.1 9.8 7.7 NEG. Time (ms) % 2.35 14.8 2.02 11.3 1.63 9.2 1.28 7.5 Time (ms) 2.47 1.88 1.53 1.25 Input Pulse to Pin 8 (VD) Fv = 60 Hz Precautions for Application 1. Input 1) Green (Sync on Video) input (pins [3] and [4]) The input signals must be in sync negative polarity. For sync separation, a method is used in which the sync tip is clamped by a capacitor attached externally to pin [4] and by the C and R attached to pin [3]. Then sync tip of pin [4] shows approximately 4 V. Rev.1.0, Sep.22.2003, page 8 of 13 M52036SP 2) Comp Sync/H sync, V sync input Connect the composite sync input to pin [6]. For the separate sync input, connect H and V to pins[6] and [8] respectively. The bias and impedance at pins [6] and [8] are 6 V and 10 kΩ, respectively. Waveform shaping and polarity detection are performed by a double threshold converter installed inside. The internal circuit is as shown in Fig.B. The average DC voltage is set to approximately 0.7 V higher and lower than V2. Thus, as shown in Fig. A, this processor is energized by an input signal 0.7 Vp-p or over when the duty ratio is small. On the other hand, approximately 1.4 Vp-p is suitable when the duty ratio is large. Fig. C indicates an allowable standard value for the input duty. Rev.1.0, Sep.22.2003, page 9 of 13 M52036SP Fig. D shows an example of the measures for improving the allowable duty ratio in a range of 1.4 Vp-p or over of the input signal. For use in a range outside the specified value, confirm that the waveform complies with Fig. E when measured it after removing the filters in pins [7] and [9]. 3) Polarity detection and empty input detection (pins [7] and [9]) A capacitor is required to be installed external as a filter for polarity detection and empty input detection. The large the capacitance, the smaller the ripple and reduces malfunction. However, the detecting time is lengthened. For an input of 15 kHz, a capacitor of 0.05 µF or larger is recommended. For 60 Hz, a 10 µF or larger is sufficient. If it is necessary to use a capacitor of smaller capacitance, measure the waveform at the filter terminal under the condition of the lowest frequency of the input sync signal to be used and the smallest duty ratio. And make sure that the signal shows 7.5 V (actually 6.6 V) or over for positive polarity input or 4.5 V (actually 5.5 V) or lower for a negative polarity input. 4) VERT S/S IN (pins [11]) For V sync separation, signals are generated by externally integrating composite sync signals, and are then input. The composite sync signals that are input to pin [6] (H + V) ore output to pin [14] HD+. For V sync separation, pin [14] HD+ output is externally integrated, and input to pin [11]. Check pin [11] waveform to see if the H element is adequately low. In the IC, the sync separation threshold level is set to approximately 1 V when no external adjustment is provided. Rev.1.0, Sep.22.2003, page 10 of 13 M52036SP 5) VERT S/S ADJ (pins [10]) The threshold voltage is approximately 1 V when no external adjustment is provided. The threshold voltage is dependent on IC internal resistance. Pin [10] may be open; however, if noise may give adverse effect, ground the pin with capacitor. When the H element cannot be lowered sufficiently, connect resistance between pin [10] and Vcc to change the threshold level. (Provide resistance such that when VDD (Digital Vcc) is 12 V, the threshold voltage will be 8 V or less; and when VDD 1s 5 V, the threshold voltage will be 4 V or less.) When there are serration pulses or other pulses during the V period, provide resistance such that the threshold voltage will be half as high as VDD. 2. CP-Width Timing terminal (pins [20]) The time constant depends on the current flowing out through pin [20] and the capacitance of the timing terminal. The current flowing out through pin [20] is usually determined by the terminal voltage and the resistance of externally attached resistor. A pulse width of 0.7 µ sec is obtained by an 18 kΩ (or 200 µA) resistor and a 100 pF capacitor both installed externally. 3. Output stage 1) Logic output (pins [1], [2], [18] and [19]) This output system is illustrated in the figure shown below. The internal load resistance of this IC is 20 kΩ. 2) Pulse output (pins [13], [14], [15] and [17]) This output system is of open collector type as illustrated in the figure shown below. Approximately 6 mA can be charged in. 3) Power supply Supply 12 V to pin [16]. For the pulse output power, supply a digital Vcc of 5 to 12 V as illustrated below. Rev.1.0, Sep.22.2003, page 11 of 13 M52036SP 4. Other Differences between M52036SP and M52346SP The clamp pulse trigger is different between M52036SP and M52346SP when “S on G” and “H/H + V” are input simultaneously, or when only “H/H + V” is input. M52036SP: Generated at the first edge of “H/H + V” input. M52346SP: Generated at the latter edge of “H/H + V” input. M52346SP clamp pulses are generated at the latter edge of signals that have been given priority. The M52036SP pin configuration is the same as that of M52346SP. Rev.1.0, Sep.22.2003, page 12 of 13 SEATING PLANE EIAJ Package Code SDIP20-P-300-1.78 e b D b1 10 1 Lead Material Alloy 42/Cu Alloy 11 Weight(g) 1.0 20 JEDEC Code — A A1 A2 b b1 c D E e e1 L Symbol Plastic 20pin 300mil SDIP Dimension in Millimeters Min Nom Max — — 4.5 0.51 — — — 3.3 — 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 18.8 19.0 19.2 6.15 6.3 6.45 — 1.778 — — 7.62 — 3.0 — — 0° 15° — c MMP A L E A2 Rev.1.0, Sep.22.2003, page 13 of 13 A1 e1 20P4B M52036SP Package Dimensions Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0