Burr-Brown OPA129P Ultra-low bias current difet operational amplifier Datasheet

®
OPA129
Ultra-Low Bias Current Difet®
OPERATIONAL AMPLIFIER
FEATURES
APPLICATIONS
● ULTRA-LOW BIAS CURRENT: 100fA max
● PHOTODETECTOR PREAMP
●
●
●
●
●
●
●
●
●
●
LOW OFFSET: 2mV max
LOW DRIFT: 10µV/°C max
HIGH OPEN-LOOP GAIN: 94dB min
LOW NOISE: 15nV/√Hz at 10kHz
PLASTIC DIP and SOIC PACKAGE
CHROMATOGRAPHY
ELECTROMETER AMPLIFIERS
MASS SPECTROMETER
pH PROBE AMPLIFIER
ION GAGE MEASUREMENT
DESCRIPTION
The OPA129 is an ultra-low bias current monolithic operational amplifier offered in an 8-pin PDIP
and SO-8 package. Using advanced geometry
dielectrically-isolated FET (Difet®) inputs, this monolithic amplifier achieves a high performance level.
Difet fabrication eliminates isolation-junction leakage
current—the main contributor to input bias current
with conventional monolithic FETs. This reduces
input bias current by a factor of 10 to 100. Very low
input bias current can be achieved without resorting to
small-geometry FETs or CMOS designs which can
suffer from much larger offset voltage, voltage noise,
drift, and poor power supply rejection.
The OPA129's special pinout eliminates leakage current that occurs with other op amps. Pins 1 and 4 have
no internal connection, allowing circuit board guard
traces—even with the surface-mount package version.
Substrate
8
7
V+
–In
2
3
+In
Noise-Free
Cascode
6
Output
30kΩ
30kΩ
OPA129 is available in 8-pin DIP and SO-8 packages,
specified for operation from –40°C to +85°C.
5
V–
Simplified Circuit
Difet® Burr-Brown Corp.
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
©
1994 Burr-Brown Corporation
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
PDS-1195A
Printed in U.S.A. July, 1994
SPECIFICATIONS
ELECTRICAL
At VS = ±15V and TA = +25°C unless otherwise noted. Pin 8 connected to ground.
OPA129PB, UB
PARAMETER
CONDITION
MIN
TYP
OPA129P, U
MAX
MIN
±30
±100
Doubles every 10°C
TYP
MAX
UNITS
*
*
±250
fA
INPUT BIAS CURRENT(1)
vs Temperature
VCM = 0V
INPUT OFFSET CURRENT
VCM = 0V
±30
VCM = 0V
VS = ±5V to ±18V
±0.5
±3
±3
f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
fB = 0.1Hz to 10Hz
f = 10kHz
85
28
17
15
4
0.1
*
*
*
*
*
*
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVp-p
fA/√Hz
1013 || 1
1015 || 2
*
*
Ω || pF
Ω || pF
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
Supply Rejection
NOISE
Voltage
Current
INPUT IMPEDANCE
Differential
Common-Mode
VOLTAGE RANGE
Common-Mode Input Range
Common-Mode Rejection
OPEN-LOOP GAIN, DC
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Unity Gain, Small Signal
Full Power Response
Slew Rate
Settling Time:
0.1%
0.01%
Overload Recovery, 50% Overdrive(2)
RATED OUTPUT
Voltage Output
Current Output
Load Capacitance Stability
Short-Circuit Current
POWER SUPPLY
Rated Voltage
Voltage Range, Derated Performance
Current, Quiescent
TEMPERATURE
Specification
Operating
Storage
Thermal Resistance
PDIP—"P"
SOIC—"U"
*
±2
±10
±100
±1
±5
*
fA
±5
*
mV
µV/°C
µV/V
VIN = ±10V
±10
80
±12
118
*
*
*
*
V
dB
RL ≥ 2kΩ
94
120
*
*
dB
1
1
47
2.5
*
*
*
*
MHz
kHz
V/µs
*
*
*
µs
µs
µs
*
*
*
*
*
V
mA
pF
mA
*
*
V
V
mA
*
*
*
°C
°C
°C
20Vp-p, RL = 2kΩ
VO = ±10V, RL = 2kΩ
G = –1, RL = 2kΩ, 10V Step
5
10
5
G = –1
RL = 2kΩ
VO = ±12V
Gain = +1
±12
±6
±5
IO = 0mA
Ambient Temperature
Ambient Temperature
±13
±10
1000
±35
±15
1.2
–40
–40
–40
*
*
±55
*
±18
1.8
*
+85
+125
+125
*
*
*
*
θJA, Junction-to-Ambient
90
100
*
*
°C/W
°C/W
NOTES: (1) High-speed automated test. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the
removal of a 50% input overdrive.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
OPA129
2
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Power Supply Voltage ...................................................................... ±18V
Differential Input Voltage ............................................................ V– to V+
Input Voltage Range .................................................................... V– to V+
Storage Temperature Range ......................................... –40°C to +125°C
Operating Temperature Range ..................................... –40°C to +125°C
Lead Temperature (soldering, 10s; SOIC 3s) ............................... +300°C
Output Short Circuit Duration(1) .................................................................. Continuous
Junction Temperature (TJ) ............................................................. +150°C
PACKAGE
PACKAGE DRAWING
NUMBER(1)
8-pin Plastic DIP
8-pin Plastic DIP
8-pin SOIC
8-pin SOIC
006
006
182
182
MODEL
OPA129P
OPA129PB
OPA129U
OPA129UB
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
NOTE: (1) Short circuit may be to power supply common at +25°C ambient.
CONNECTION DIAGRAM
ELECTROSTATIC
DISCHARGE SENSITIVITY
Top View
DIP/SOIC
NC
1
8
Substrate
–In
2
7
V+
+In
3
6
Output
NC
4
5
V–
OPA
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NC: No internal connection.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
TYPICAL PERFORMANCE CURVES
TA = +25°C, +15VDC, unless otherwise noted.
OPEN-LOOP FREQUENCY RESPONSE
POWER SUPPLY REJECTION vs FREQUENCY
140
140
100
θ
80
Phase
Margin
≈90°
60
40
90
135
Power Supply Rejection (dB)
45
Gain
Pulse Shift (degrees)
Voltage Gain (dB)
120
20
0
180
1
10
100
1k
10k
100k
1M
120
100
80
+PSRR
60
–PSRR
40
20
0
10M
1
Frequency (Hz)
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
®
3
OPA129
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, +15VDC, unless otherwise noted.
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
COMMON-MODE REJECTION vs FREQUENCY
140
Common-Mode Rejection (dB)
Common-Mode Rejection (dB)
120
110
100
90
80
120
100
80
60
40
20
0
70
15
5
10
0
5
10
15
1
1k
10k
100k
1M
BIAS AND OFFSET CURRENT vs TEMPERATURE
BIAS AND OFFSET CURRENT
vs INPUT COMMON-MODE VOLTAGE
10M
10
Normalized Bias and Offset Current
Bias and Offset Current (fA)
100
Frequency (Hz)
100pA
10pA
1pA
IB and IOS
100
10
1
0.1
0.01
1
–50
–25
0
25
50
75
100
15
125
Ambient Temperature (°C)
–10
–5
5
0
10
15
Common-Mode Voltage (V)
FULL-POWER OUTPUT vs FREQUENCY
INPUT VOLTAGE NOISE SPECTRAL DENSITY
30
Output Voltage (Vp-p)
1k
Voltage Density (nV/√Hz)
10
Common-Mode Voltage (V)
100
20
10
0
10
1
10
100
1k
10k
1k
100k
®
OPA129
10k
100k
Frequency (Hz)
Frequency (Hz)
4
1M
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, +15VDC, unless otherwise noted.
4
3
3
2
2
1
1
0
0
–75
–50
–25
0
25
50
75
100
3
6
2
4
+Slew
–Slew
1
0
0
125
0
5
10
Ambient Temperature (°C)
15
20
Supply Voltage (±VCC)
SUPPLY CURRENT vs TEMPERATURE
OPEN-LOOP GAIN, PSR AND CMR vs TEMPERATURE
2
130
PSR, CMR, Voltage Gain (dB)
Supply Current (mA)
2
GBW
Slew Rate (v/µs)
4
Gain Bandwidth (MHz)
GAIN BANDWIDTH AND SLEW RATE
vs SUPPLY VOLTAGE
Slew Rate (V/µs)
Gain Bandwidth (MHz)
GAIN BANDWIDTH AND SLEW RATE
vs TEMPERATURE
1.5
1
0.5
0
120
A OL
CMR
110
100
PSR
90
–75
–50
–25
0
25
50
75
100
125
–75
–50
Ambient Temperature (°C)
–25
0
25
50
75
100
125
Ambient Temperature (°C)
LARGE SIGNAL TRANSIENT RESPONSE
SMALL SIGNAL TRANSIENT RESPONSE
10
Output Voltage (mV)
Output Voltage (V)
80
0
–10
40
0
–40
–80
0
25
50
0
Time (µs)
2
4
6
8
10
Time (µs)
®
5
OPA129
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, +15VDC, unless otherwise noted.
COMMON-MODE INPUT RANGE vs SUPPLY VOLTAGE
BIAS CURRENT vs ADDITIONAL POWER DISSIPATION
100pA
10pA
Bias Current (fA)
Common-Mode Voltage (+V)
15
10
5
1pA
100
10
0
1
0
5
10
15
20
0
APPLICATIONS INFORMATION
V+
VIN
3
7
OPA129
6
VOUT
5
V+
V–
470kΩ
220Ω
470kΩ
0.1µF
V–
FIGURE 1. Offset Adjust Circuit.
OFFSET VOLTAGE TRIM
The OPA129 has no conventional offset trim connections.
Pin 1, next to the critical inverting input, has no internal
connection. This eliminates a source of leakage current and
allows guarding of the input terminals. Pin 1 and pin 4, next
to the two input pins, have no internal connection. This
allows an optimized circuit board layout with guarding—see
“circuit board layout.”
®
OPA129
150
200
250
300
350
GUARDING AND SHIELDING
Ultra-low input bias current op amps require precautions to
achieve best performance. Leakage current on the surface of
circuit board can exceed the input bias current of the amplifier. For example, a circuit board resistance of 1012Ω from
a power supply pin to an input pin produces a current of
15pA—more than one-hundred times the input bias current
of the op amp.
To minimize surface leakage, a guard trace should completely surround the input terminals and other circuitry
connecting to the inputs of the op amp. The DIP package
should have a guard trace on both sides of the circuit board.
The guard ring should be driven by a circuit node equal in
potential to the op amp inputs—see Figure 2. The substrate,
pin 8, should also be connected to the circuit board guard to
assure that the amplifier is fully surrounded by the guard
potential. This minimizes leakage current and noise pick-up.
Careful shielding is required to reduce noise pickup. Shielding near feedback components may also help reduce noise
pick-up.
Triboelectric effects (friction-generated charge) can be a
troublesome source of errors. Vibration of the circuit board,
input connectors and input cables can cause noise and drift.
Make the assembly as rigid as possible. Attach cables to
avoid motion and vibration. Special low noise or low leakage cables may help reduce noise and leakage current. Keep
all input connections as short possible. Surface-mount components may reduce circuit board size and allow a more rigid
assembly.
RF
2
100
Due to its laser-trimmed input stage, most applications do
not require external offset voltage trimming. If trimming is
required, the circuit shown in Figure 1 can be used. Power
supply voltages are divided down, filtered and applied to the
non-inverting input. The circuit shown is sensitive to variation in the supply voltages. Regulation can be added, if
needed.
NON-STANDARD PINOUT
The OPA129 uses a non-standard pinout to achieve lowest
possible input bias current. The negative power supply is
connected to pin 5—see Figure 1. This is done to reduce the
leakage current from the V- supply (pin 4 on conventional
op amps) to the op amp input terminals. With this new
pinout, sensitive inputs are separated from both power
supply pins.
RIN
50
Additional Power Dissipation (mW)
Supply Voltage (±VCC)
6
CIRCUIT BOARD LAYOUT
The OPA129 uses a new pinout for ultra low input bias
current. Pin 1 and pin 4 have no internal connection. This
allows ample circuit board space for a guard ring surrounding the op amp input pins—even with the tiny SO-8 surfacemount package. Figure 3 shows suggested circuit board
layouts. The guard ring should be connected to pin 8 (substrate) as shown. It should be driven by a circuit node equal
in potential to the input terminals of the op amp—see Figure
2 for common circuit configurations.
1000MΩ
RF
2
Current
Input
3
7
Output
500Ω
6 Out
8
2
7
6
OPA129
3
1VDC
Output
5
V–
pH Probe
RS ≈ 500MΩ
50mV Out
CF 10pF
1011Ω
RF
8
3
In
V+
Guard
FIGURE 5. High Impedance (1015Ω) Amplifier.
6
3
VO = –IIN • RF
VO = –1V/nA
9.5kΩ
(B) Buffer
2
5
FIGURE 4. Current-to-Voltage Converter.
6. Load power dissipation,
7. Mechanical stress,
8. Electrostatic and electromagnetic interference.
8
6
V–
2. Unclean package,
3. Humidity or dew point condensations,
4. Circuit contamination from fingerprints or anti-static
treatment chemicals,
5. Test ambient temperature,
2
18kΩ
OPA129
8
TESTING
Accurately testing the OPA129 is extremely difficult due to
its high performance. Ordinary test equipment may not be
able to resolve the amplifier’s extremely low bias current.
Inaccurate bias current measurements can be due to:
1. Test socket leakage,
(A) Non-Inverting
2kΩ
V+
IIN
V+
Out
In
8
2
(C) Inverting
∆Q
3
7
OPA129
Output
6
VOUT
5
In
Low frequency cutoff =
V– 1/(2πR C ) = 0.16Hz
F F
2
6 Out
3
VOUT = –∆Q/CF
8
FIGURE 6. Piezoelectric Transducer Charge Amplifier.
Guard top and bottom of board.
~1pF to prevent gain peaking
FIGURE 2. Connection of Input Guard.
1
8
V+
V0
1010 Ω
Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
Pin photodiode
HP 5082-4204
V–
4
5
2
(A) DIP package
1
8
V0
5
8
0.1µF
7
V+
4
+15V
Guard
3
Connect to proper circuit
node, depending on circuit
configuration (see Figure 2).
OPA129
6
5 0.1µF
V–
Output
5 x 109V/W
–15V
(B) SOIC package
Circuit must be well shielded.
FIGURE 7. Sensitive Photodiode Amplifier.
FIGURE 3. Suggested Board Layout for Input Guard.
®
7
OPA129
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