Linear LTM8023 Dual sepic or inverting module dc dc converter Datasheet

LTM8049
Dual SEPIC or Inverting
µModule DC/DC Converter
FEATURES
DESCRIPTION
Two Complete Switch Mode Power Supplies
nn SEPIC or Inverting Topology
nn Wide Input Voltage Range: 2.6V to 20V
nn 2.5V to 24V or –2.5V to –24V Output Voltage
nn 1A at 5V
OUT from 12VIN
nn Selectable Switching Frequency: 200kHz to 2.5MHz
nn Power Good Outputs for Event Based Sequencing
nn User Configurable Undervoltage Lockout
nn (e4) RoHS Compliant Package with Gold Pad Finish
nn Low Profile 15mm × 9mm × 2.42mm Surface Mount
BGA Package
The LTM®8049 is a Dual SEPIC/Inverting µModule® (power
module) DC/DC Converter. Each of the two outputs can
be easily configured as a SEPIC or Inverting converter by
simply grounding the appropriate output rail. The LTM8049
includes power devices, inductors, control circuitry and
passive components. All that is needed to complete the
design are input and output caps, and small resistors to
set the output voltages and switching frequency. Other
components may be used to control the soft-start and
undervoltage lockout.
nn
APPLICATIONS
Battery Powered Regulator
Local Negative Voltage Regulator
nn Low Noise Amplifier Power
nn
nn
The LTM8049 is packaged in a thermally enhanced, compact (15mm × 9mm) over-molded Ball Grid Array (BGA)
package suitable for automated assembly by standard surface mount equipment. The LTM8049 is RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
±12VOUT from 2.7VIN to 20VIN
Maximum Load Current vs VIN
1.5
VIN1
4.7µF
×2
80.6k
1MHz
80.6k
1MHz
VOUT1P
FBX1
RUN1
VOUT1N
RT1
VOUT1
12V
130k
22µF
CLKOUT1
SYNC2
RT2
VIN2
RUN2
SYNC1
LTM8049
VOUT2P
FBX2
VOUT2N
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2
47µF
143k
VOUT2
–12V
8049 TA01a
LOAD CURRENT (A)
VIN
2.7V TO 20V
1.0
0.5
0
0
5
10
VIN (V)
15
20
8049 TA01
8049f
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1
LTM8049
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
VINn, RUNn, PGn........................................................20V
SYNCn, FBXn...............................................................5V
SSn...........................................................................2.5V
SHAREn.......................................................................2V
VOUTP (VOUTN = 0V)...................................................25V
VOUTN (VOUTP = 0V).................................................–25V
Maximum Internal Temperature............................. 125°C
Maximum Solder Temperature............................... 260°C
Storage Temperature.............................. –55°C to 125°C
A
BANK 2
VIN1
B
RUN1
FBX1
C
SS1
BANK 6
VOUT1N
D
SYNC1
E
RT1
BANK 4
VOUT1P
BANK 1
GND
PG1
CLKOUT1
SHARE2
F
BANK 7
VOUT2N
G
RT2
H
SYNC2
FBX2
J
SS2
BANK 5
VOUT2P
K
RUN2
L
BANK 3
VIN2
1
2
3
4
5
6
SHARE1
CLKOUT2
PG2
7
BGA PACKAGE
77-LEAD (15mm × 9mm × 2.42mm)
TJMAX = 125°C, θJA = 16.2°C/W, θJB = 3.8°C/W, θJCtop = 8.8°C/W,
θJCbottom = 3.8°C/W, θJCboard = 4.6°C/W, WEIGHT = 0.8g,
θ VALUES DETERMINED PER JEDEC 51-9, 51-12
ORDER INFORMATION
(http://www.linear.com/product/LTM8049#orderinfo)
PART MARKING*
PART NUMBER
LTM8049EY#PBF
LTM8049IY#PBF
PAD OR BALL FINISH
DEVICE
FINISH CODE
PACKAGE
TYPE
MSL
RATING
SAC305 (RoHS)
LTM8049Y
e1
BGA
3
TEMPERATURE RANGE
(SEE NOTE 2)
–40°C to 125°C
–40°C to 125°C
* Device temperature grade is indicated by a label on the shipping container. • Recommended BGA PCB Assembly and Manufacturing Procedures:
www.linear.com/BGA-assy
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• This product is not recommended for second side reflow. For more
information, go to www.linear.com/BGA-assy
2
• BGA Package and Tray Drawings: www.linear.com/packaging
• This product is moisture sensitive. For more information, go to:
www.linear.com/BGA-assy
8049f
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LTM8049
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
temperature range (Notes 2, 3), otherwise specifications are at TA = 25°C. RUN = 2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
Minimum Input Operating Voltage
l
TYP
MAX
UNITS
2.6
V
Positive Output DC Voltage
IOUT = 50mA, RFB = 15.4k, VOUTN Grounded
IOUT = 50mA, RFB = 274k, VOUTN Grounded
2.5
24
V
V
Negative Output DC Voltage
IOUT = 50mA, RFB = 30.1k, VOUTP Grounded
IOUT = 50mA, RFB = 287k, VOUTP Grounded
–2.5
–24
V
V
Maximum Continuous Output DC Current
VIN = 12V, VOUT = 5V or –5V
VIN = 12V, VOUT = 24 or –24V
VIN Quiescent Current
VRUN = 0V
VRUN = 2V, No Load
0
10
Line Regulation
4 ≤ VIN ≤ 20V, IOUT = 0.6A
0.1
%
Load Regulation
0 ≤ IOUT ≤ 1A
0.3
%
Switching Frequency
RT = 31.6k
RT = 412k
l
l
2100
160
2500
200
2900
240
kHz
kHz
Voltage at FBX Pin
Positive Output
Negative Output
l
l
1.185
2
1.204
7
1.22
16
V
mV
Current into FBX Pin
Positive Output
Negative Output
l
l
81
81
83.3
83.3
85.6
85.6
µA
µA
RUN pin Threshold Voltage
RUN Pin Rising
RUN Pin Falling
1.21
1.31
1.27
1.4
V
V
RUN Pin Current
VRUN = 3V
VRUN = 1.3V
VRUN = 0V
10.1
45
12.1
0
65
14.1
0.1
µA
µA
µA
SS Sourcing Current
SS = 0V
5.7
8.8
Synchronization Frequency Range
1
0.25
A
A
200
SYNC Input Low Threshold
µA
mA
11.7
µA
2500
kHz
0.4
SYNC Input High Threshold
CLKOUT1 Duty Cycle
2
V
1.3
(Note 5)
CLKOUT Output Voltage (Low)
2k Pull-Up to 2V
CLKOUT Output Voltage (High)
2k Pull-Down to GND
1.9
PG Threshold for Positive Feedback Voltage
FBX Rising
1.09
20
PG Threshold for Negative Feedback Voltage
FBX Falling
PG Output Voltage Low
100µA into PG, FBX = 1V
PG Leakage Current
PG = 20V, Run = 0V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM8049E is guaranteed to meet performance specifications
from 0°C to 125°C. Specifications over the –40°C to 125°C internal
temperature range are assured by design, characterization and correlation
with statistical process controls. LTM8049I is guaranteed to meet
specifications over the full –40°C to 125°C internal operating temperature
range. Note that the maximum internal temperature is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal resistance and other environmental factors.
V
50
%
0.2
V
V
1.2
V
120
mV
150
mV
1
µA
Note 3: This μModule regulator includes overtemperature protection that
is intended to protect the device during momentary overload conditions.
Internal temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum internal
operating junction temperature may impair device reliability.
Note 4: CLKOUTn is intended to drive other circuitry. Do not apply a
positive or negative voltage or current source to CLKOUT, otherwise
permanent damage may occur.
Note 5: The duty cycle of CLKOUT2 is dependent upon the internal
temperature. See the Applications Information section for more details.
8049f
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3
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
75
65
55
Efficiency, VOUT ±3.3V
65
55
5VIN
8VIN
45
0
0.5
1
1.5
LOAD CURRENT (A)
45
2
0
0.5
1
1.5
LOAD CURRENT (A)
50
2
0
0.5
1
1.5
LOAD CURRENT (A)
85
75
65
Efficiency, VOUT ±15V
75
65
5VIN
12VIN
16VIN
0.5
1
LOAD CURRENT (A)
55
1.5
0
0.50
1
LOAD CURRENT (A)
8049 G04
55
1.50
5VIN
12VIN
16VIN
0
0.25
0.50
0.75
LOAD CURRENT (A)
8049 G05
Efficiency, VOUT ±18V
85
2
8049 G03
Efficiency, VOUT ±12V
5VIN
12VIN
16VIN
85
60
5VIN
12VIN
15VIN
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
85
65
0
70
8049 G02
Efficiency, VOUT ±8V
75
55
Efficiency, VOUT ±5V
5VIN
12VIN
8049 G01
85
80
EFFICIENCY (%)
Efficiency, VOUT ±2.5V
EFFICIENCY (%)
EFFICIENCY (%)
75
1
8049 G06
Efficiency, VOUT ±24V
2.5
Input vs Load Current, VOUT ±2.5V
65
INPUT CURRENT (A)
75
EFFICIENCY (%)
EFFICIENCY (%)
2.0
75
65
5VIN
12VIN
16VIN
55
0
0.20
0.40
0.60
LOAD CURRENT (A)
0.80
8049 G07
4
55
0.2
0.4
LOAD CURRENT (A)
1.0
0.5
5VIN
12VIN
16VIN
0
1.5
0.6
8049 G08
0
5VIN
8VIN
0
0.5
1
1.5
LOAD CURRENT (A)
2
8049 G09
8049f
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LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
Input vs Load Current, VOUT ±3.3V
3.0
Input vs Load Current, VOUT ±5V
3.0
Input vs Load Current, VOUT ±8V
1.5
1.0
0.5
0
INPUT CURRENT (A)
INPUT CURRENT (A)
INPUT CURRENT (A)
2.0
2.0
1.0
5VIN
12VIN
15VIN
5VIN
12VIN
0
0.5
1
1.5
LOAD CURRENT (A)
0
2
0
0.5
1
1.5
LOAD CURRENT (A)
1.0
0
3.0
5VIN
12VIN
16VIN
0
0.50
1
LOAD CURRENT (A)
Input vs Load Current, VOUT ±24V
1.0
2.0
0
0.25
0.50
0.75
LOAD CURRENT (A)
0
0
0.2
0.4
LOAD CURRENT (A)
0.6
8049 G16
1.0
5VIN
12VIN
16VIN
0
0.2
2.0
PER CHANNEL
0.8
Maximum Load Current vs VIN
PER CHANNEL
1.5
1.0
0
0.4
0.6
LOAD CURRENT (A)
8049 G15
Maximum Load Current vs VIN
0.5
5VIN
12VIN
16VIN
Input vs Load Current, VOUT ±18V
2.0
0
1
LOAD CURRENT (A)
1.0
1.5
5VIN
12VIN
16VIN
1.5
2.0
0.5
1
LOAD CURRENT (A)
8049 G14
LOAD CURRENT (A)
INPUT CURRENT (A)
3.0
2.0
0
1.50
Input vs Load Current, VOUT ±15V
8049 G13
3.0
0
8049 G12
INPUT CURRENT (A)
Input vs Load Current, VOUT ±12V
2.0
5VIN
12VIN
16VIN
8049 G11
INPUT CURRENT (A)
INPUT CURRENT (A)
3.0
1.0
0
2
8049 G10
2.0
0.5
2.5VOUT
3.3VOUT
5VOUT
0
5
10
VIN (V)
1.0
15
8049 G17
0
8VOUT
12VOUT
15VOUT
0
5
10
VIN (V)
15
20
8049 G18
8049f
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5
LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Load Current vs VIN
2.00
PER CHANNEL
OUTPUT CURRENT (A)
LOAD CURRENT (A)
0.50
0.25
2.00
18VOUT
24VOUT
0
5
10
VIN (V)
15
1.00
0.50
0
20
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
5VIN
12VIN
16VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
1.00
0.50
0
125
5VIN
12VIN
16VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
5VIN
12VIN
16VIN
125
8049 G25
125
8049 G24
Derating Curve, VOUT ±18VOUT
0.75
Derating Curve, VOUT ±24VOUT
0 LFM
0.75
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Derating Curve, VOUT ±12VOUT
0 LFM
0.50
125
8049 G23
1.00
0.75
6
25
50
75
100
AMBIENT TEMPERATURE (°C)
0 LFM
0.50
0 LFM
25
50
75
100
AMBIENT TEMPERATURE (°C)
1.50
1.00
0
125
Derating Curve, VOUT ±15VOUT
0
0
8049 G21
Derating Curve, VOUT ±8VOUT
8049 G22
0
0
125
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
5VIN
12VIN
15VIN
0.25
0.50
0 LFM
1.00
1.00
1.00
8049 G20
1.50
25
50
75
100
AMBIENT TEMPERATURE (°C)
1.50
5VIN
12VIN
8049 G19
1.50
0
0 LFM
1.50
0 LFM
0
Derating Curve, VOUT ±3.3VOUT
5VIN
8VIN
Derating Curve, VOUT ±5VOUT
0.50
2.00
0LFM
0.75
0
Derating Curve, VOUT ±2.5VOUT
OUTPUT CURRENT (A)
1.00
0.50
0.25
0
5VIN
12VIN
16VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8049 G26
0.50
0.25
0
5VIN
12VIN
16VIN
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
125
8049 G27
8049f
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LTM8049
TYPICAL PERFORMANCE CHARACTERISTICS
Output Ripple, DC2244A Board
800mA Load, 12VIN
Measured Across C5, C6
CLKOUT2 Duty Cycle
vs Temperature
80
fSW = 1MHz
DUTY CYCLE (%)
12VOUT
50mV/DIV
60
–12VOUT
20mV/DIV
40
500ns/DIV
20
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
8049 G29
125
8049 G28
PIN FUNCTIONS
GND (Bank 1): Tie these GND pins to a local ground plane
below the LTM8049 and the circuit components. GND
MUST BE CONNECTED EITHER TO VOUTP OR VOUTN FOR
PROPER OPERATION. In most applications, the bulk of
the heat flow out of the LTM8049 is through these pads,
so the printed circuit design has a large impact on the
thermal performance of the part. See the PCB Layout and
Thermal Considerations sections for more details. Return
the feedback divider (RFB) to this net.
VIN1, VIN2 (Banks 2, 3): The VINn pins supply current to
the LTM8049’s internal regulator and to the internal power
switch. This pin must be locally bypassed with an external,
low ESR capacitor.
VOUT1P, VOUT2P (Banks 4, 5): VOUTnP is the positive output of the LTM8049. Apply an external capacitor between
VOUTnP and VOUTnN. Tie this net to GND to configure the
LMT8049 as a negative output Inverting regulator.
VOUT1N, VOUT2N (Banks 6, 7): VOUTnN is the negative output of the LTM8049. Apply an external capacitor between
VOUTnP and VOUTnN. Tie this net to GND to configure the
LTM8049 as a positive output SEPIC regulator.
RUN1, RUN2 (Pins B7, K7): These pins are used to enable/
disable the chip and restart the soft-start sequence. Drive
below 1.21V to stop the LTM8049 from switching. Drive
above 1.4V to activate the device and restart the soft-start
sequence. Do not float this pin.
RT1, RT2 (Pins E7, G7): The RTn pins are used to program
the switching frequency of the LTM8049 by connecting a
resistor from this pin to ground. The switching frequency
of the LTM8049 is determined by the equation RTn =
(81.6/fOSC)-1, where the fOSC is the switching frequency in
MHz. This pin must have a resistor to GND. Do not apply
a voltage to this pin.
SS1, SS2 (Pins C7, J7): Connect a soft-start capacitor
from this pin to GND. Upon start-up, the SSn pins will be
charged by an internal current source to about 2V.
SYNC1, SYNC2 (Pins D7, H7): To synchronize the switching frequency to an outside clock, simply drive this pin with
a clock signal. The high voltage level of the clock needs
to exceed 1.3V, and the low level must be less than 0.4V.
Drive this pin to less than 0.4V to revert to the internal
free running clock. Ground these pins if synchronization
is not required. See the Applications Information section
for more information.
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7
LTM8049
PIN FUNCTIONS
FBX1, FBX2 (Pins C1, J1): If configured as a SEPIC, the
LTM8049 regulates its FBX pin to 1.204V. Apply a resistor between FBX and VOUTP. Its value should be RFB =
[(VOUTP – 1.204)/0.0833]k. If the LTM8049 is configured
as an inverting converter, the LTM8049 regulates the FBX
pin to 7mV. Apply a resistor between FBX and VOUTN of
value RFB = [(|VOUTN| + 0.007)/0.0833]k. The LTM8049
features frequency foldback to protect the power switches
during a fault or output current overload. During start-up,
frequency foldback also limits the current the LTM8049
delivers to the load. The user must evaluate the start-up
behavior of the LTM8049 to ensure that it properly powers up the load.
CLKOUT1, CLKOUT2 (Pins E6, G6): Use these pins to
synchronize devices to either channel of the LTM8049.
These pins oscillate at the same frequency as the LTM8049
internal oscillator or, if active, the SYNC pin. The CLKOUT1
signal is about 180° out of phase with the oscillator of
channel 1 and duty cycle is about 50%. The CLKOUT2 signal
is in phase with the internal oscillator of channel 2 and its
duty cycle varies linearly with the internal temperature of
the LTM8049. Please refer to the Applications Information
section for detailed information on using CLKOUT2 as an
indication of the LTM8049 internal temperature. Do not
apply a voltage to this pin or use this pin to drive capacitive loads greater than 120pF.
PG1, PG2 (Pins D6, H6): These active high pins indicates
that the FBn pin voltage for the corresponding channel
is within 4% of its regulation voltage These open drain
outputs requires a pull-up resistor to indicate power good.
Also, the status of these pins is valid only when RUN >
1.4V and VIN > 2.6V.
SHARE1, 2 (pins F3, F4): Connect these pins together if
the two outputs of the LTM8049 are paralleled. Otherwise,
leave these pins floating.
BLOCK DIAGRAM
VIN1
4.7µH
2.2µF
VOUT1P
4.7µH
0.1µF
VOUT1N
RUN1
FBX1
RT1
SHARE1
CONTROLLER
PG1
CLKOUT1
SYNC1
GND
8049 BD
NOTE: CHANNEL 1. CHANNEL 2 IS FUNCTIONAL IDENTICAL, EXCEPT FOR THE CLKOUT2
VS TEMPERATURE BEHAVIOR. PLEASE SEE THE PIN DESCRIPTION AND APPLICATIONS
INFORMATION SECTIONS FOR DETAILS.
8
8049f
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LTM8049
OPERATION
The LTM8049 contains two stand-alone switching DC/
DC converters; either one may be configured as a SEPIC
(single-ended primary inductance converter) or inverting
power supply simply by tying VOUTN or VOUTP to GND,
respectively. It accepts an input voltage up to 20VDC. The
output is adjustable between 2.5V and 24V for the SEPIC,
and between –2.5V and –24V for the inverting configuration. The LTM8049 can provide 1.5A at VIN = 12V when
VOUT = 5V or –5V at ambient room temperature.
As shown in the Block Diagram, the LTM8049 contains a
current mode controller, power switching element, power
coupled inductor, power Schottky diode and a modest
amount of input and output capacitance. The LTM8049
is a fixed frequency PWM regulator.
The LTM8049 switching can free run by applying a resistor to
the RT pin or synchronize to an external source at a frequency
between 200kHz and 2.5MHz. To synchronize to an external
source, drive a valid signal source into the SYNC pin. See
Synchronization in the Applications Section for more details.
The LTM8049 also features RUN and SS pins to control
the start-up behavior of the device. The RUN pin may also
be used to implement an accurate undervoltage lockout
function by applying a resistor network to the RUN pin.
The LTM8049 features frequency foldback to protect the
power switches during a fault or output current overload.
During start-up, frequency foldback also limits the current
the LTM8049 delivers to the load. The user must evaluate
the start-up behavior of the LTM8049 to ensure that it
properly powers up the load.
The LTM8049 is equipped with a thermal shutdown to
protect the device during momentary overload conditions.
It is set above the 125°C absolute maximum internal temperature rating to avoid interfering with normal specified
operation, so internal device temperatures will exceed
the absolute maximum rating when the overtemperature
protection is active. Therefore, continuous or repeated
activation of the thermal shutdown may impair device
reliability.
APPLICATIONS INFORMATION
For most applications, the design process is straight
forward, summarized as follows:
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
optimal efficiency over the given input condition is given
in the fOPTIMAL column. Running the LTM8049 faster than
the recommended frequency may reduce the usable input
voltage range.
2. Apply the recommended CIN, COUT, RADJ and RT values.
Capacitor Selection Considerations
While these component combinations have been tested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that the
maximum output current is limited by junction temperature, the relationship between the input and output voltage
magnitude and polarity and other factors. Please refer to
the graphs in the Typical Performance Characteristics
section for guidance.
The CIN and COUT capacitor values in Table 1 are the
minimum recommended values for the associated operating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
Table 1 gives the recommended component values and
configuration for a single channel. Each channel may be
configured independently. The maximum frequency (and
attendant RT value) at which the LTM8049 should be allowed to switch is given in Table 1 in the fMAX column,
while the recommended frequency (and RT value) for
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and applied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application
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8049f
9
LTM8049
APPLICATIONS INFORMATION
Table 1. Recommended Component Values and Configuration (TA = 25°C)
VIN RANGE (V)
2.6V to 11.5V
2.6V to 9.5V
VOUT (V)
2.5V
–2.5V
CIN
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
2.6V to 18V
2.6V to 12V
3.3V
–3.3V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
2.7V to 20V
2.7V to 15V
5V
–5V
4.7µF 25V 0603 X5R
4.7µF 25V 0603 X5R
2.7V to 20V
8V
4.7µF 25V 0603 X5R
2.7 to 18.5V
–8V
4.7µF 25V 0603 X5R
2.7V to 20V
12V
4.7µF 25V 0603 X5R
2.7V to 20V
–12V
4.7µF 25V 0603 X5R
2.7V to 20V
15V
4.7µF 25V 0603 X5R
2.7V to 20V
–15V
4.7µF 25V 0603 X5R
3V to 20V
18V
4.7µF 25V 0603 X5R
3V to 20V
–18V
4.7µF 25V 0603 X5R
3.7V to 18V
24V
4.7µF 25V 0603 X5R
3.7V to 18V
–24V
4.7µF 25V 0603 X5R
Note: An input bulk capacitor is required.
COUT
100µF 4V 0805 X5R
100µF 4V 0805 X5R
+ 47µF 6.3V 0805 X5R
100µF 4V 0805 X5R
100µF 4V 0805 X5R
+ 47µF 6.3V 0805 X5R
47µF 6.3V 0805 X5R
100µF 6.3V 1206 X5R
+ 47µF 10V 1206 X5R
22µF 10V 1206 X5R
2x 47µF 10V 1206 X5R
22µF 16V 1210 X5R
47µF 16V 1210 X5R
22µF 16V 1210 X5R
47µF 16V 1210 X5R
22µF 16V 1210 X7R
22µF 16V 1210 X7R
22µF 25V 1206 X5R
22µF 25V 1206 X5R
circuit they may have only a small fraction of their nominal
capacitance resulting in much higher output voltage ripple
than expected.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8049. A
ceramic input capacitor combined with trace or cable
inductance forms a high Q (underdamped) tank circuit.
If the LTM8049 circuit is plugged into a live supply, the
input voltage can ring to twice its nominal value, possibly exceeding the device’s rating. This situation is easily
avoided; see the Hot-Plugging Safely section.
Programming Switching Frequency
The LTM8049 has an operational switching frequency range
between 200kHz and 2.5MHz. The free running frequency
is programmed with an external resistor from the RT pin
to ground. Do not leave this pin open under any condition.
When the SYNC pin is driven low (<0.4V), the frequency
of operation is set by a resistor from RT to ground. The
RT value is calculated by the following equation:
RT =
10
RFB (Ω)
15.4k
30.1k
fOPTIMAL
600kHz
600kHz
RTOPTIMAL (Ω)
137k
137k
fMAX
2MHz
2MHz
RTMIN (Ω)
38.3k
38.3k
25.5k
39.2k
650kHz
650kHz
124k
124k
2.3MHz
2.3MHz
33.2k
33.2k
45.3k
60.4k
750k
750k
107k
107k
2.5MHz
2.5MHz
31.6k
31.6k
82.5k
95.3k
130k
143k
165k
178k
200k
215k
274k
287k
1MHz
1MHz
1MHz
1MHz
1.1MHz
1.1MHz
1.5MHz
1.5MHz
1.5MHz
1.5MHz
80.6k
80.6k
80.6k
80.6k
73.2k
73.2k
53.6k
53.6k
53.6k
53.6k
2.5MHz
2.5MHz
2.5MHz
2.5MHz
1.9MHz
1.9MHz
1.8MHz
1.8MHz
1.8MHz
1.8MHz
31.6k
31.6k
31.6k
31.6k
41.2k
41.2k
45.3k
45.3k
45.3k
45.3k
Switching Frequency Trade-Offs
It is recommended that the user apply the optimal RT value
given in Table 1 for the corresponding input and output
operating condition. System level or other considerations,
however, may necessitate another operating frequency.
While the LTM8049 is flexible enough to accommodate
a wide range of operating frequencies, a haphazardly
chosen one may result in undesirable operation under
certain operating or fault conditions. A frequency that is
too high can reduce efficiency, reduce the usable input
voltage range, generate excessive heat or even damage
the LTM8049 in some fault conditions. A frequency that
is too low can result in a final design that has too much
output ripple or too large of an output capacitor. Note that
the Maximum Output Current vs Input Voltage curves
given in the Typical Characteristics section are for the
recommended operating conditions in Table 1. Using a
different operating frequency may result in a different
maximum output current.
81.6
– 1, where fOSC is in MHz and R T is in kΩ
fOSC
8049f
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
Soft-Start
The soft-start circuitry provides for a gradual ramp-up of
the switch current in each channel. When the channel is
enabled, the external SS capacitor is first discharged. This
resets the state of the logic circuits in the channel. Then
an integrated resistor pulls the channel’s SS pin to about
1.8V. The LTM8049 has a built-in soft-start characteristic,
but a slower ramp rate may be implemented by adding
capacitance to the SS pin. Typical values are between
0.1µF and 1µF.
The RUN pin has a voltage hysteresis with typical thresholds of 1.31V (rising) and 1.27V (falling). Resistor RUVLO2
is optional. RUVLO2 can be included to reduce the overall
UVLO voltage variation caused by variations in the RUN
pin current (see the Electrical Characteristics). A good
choice for RUVLO2 is ≤10k + 1%. After choosing a value
for RUVLO2, RUVLO1 can be determined from either of the
following:
RUVLO1 =
Configurable Undervoltage Lockout
Figure 1 shows how to configure an undervoltage lockout (UVLO) for the LTM8049. Typically, UVLO is used in
situations where the input supply is current-limited, has
a relatively high source resistance, or ramps up/down
slowly. A switching regulator draws constant power from
the source, so source current increases as source voltage
drops. This looks like a negative resistance load to the
source and can cause the source to current-limit or latch
low under low source voltage conditions. UVLO prevents
the regulator from operating at source voltages where
these problems might occur.
LTM8049
VIN
VIN
RUVLO1
1.31V
RUN
12.3µA
AT 1.31V
RUVLO2
(OPTIONAL)
ACTIVE/
LOCKOUT
8049 F01
Figure 1. The RUN Pin May Be Used to Implement
an Accurate UVLO
The RUN pin sinks 12.1µA at the 1.31V rising threshold
voltage and about 11.6µA at the 1.27V falling threshold.
This makes it easy to set up an input voltage UVLO threshold with just a single resistor. For a desired VIN threshold,
choose RUVLO1 using the equation:
VIN – 1.31V
12.1µA
RUVLO1 =
VIN(FALLING) – 1.27V
1.29V
+11.6µA
RUVLO2
where VIN(RISING) and VIN(FALLING) are the VIN threshold
voltages when rising or falling respectively.
For example, to disable the LTM8049 for VIN voltages
below 3.5V using the single resistor configuration, choose:
RUVLO1 =
3.5V – 1.27V
≅191k
1.29V
+11.6µA
∞
To activate the LTM8049 for VIN greater than 4.5V using
the two resistor configuration, choose RUVLO2 = 10k and:
RUVLO1 =
GND
RUVLO1 =
or
–
+
VIN(RISING) – 1.31V
1.32V
+12.1µA
RUVLO2
4.5V – 1.31V
≅ 22.1k
1.32V
+12.1µA
10k
Internal Undervoltage Lockout
The LTM8049 monitors the VIN supply voltage in case VIN
drops below a minimum operating level (typically about
2.3V). When VIN is detected low, the power switch is
deactivated, and while sufficient VIN voltage persists, the
soft-start capacitor is discharged. After VIN is sufficiently
high, the LTM8049 will reactivate and the soft-start capacitor will begin charging.
8049f
For more information www.linear.com/LTM8049
11
LTM8049
APPLICATIONS INFORMATION
Frequency Foldback
that internal temperatures will exceed the 125°C absolute
maximum rating when the overtemperature protection is
active, possibly impairing the device’s reliability.
The frequency foldback function reduces the switching
frequency for that channel when the output is about 15%
below the target regulation point. This feature lowers the
operating frequency, thus controlling the maximum output
current during start-up. When the FBX voltage is pulled
above the above mentioned range in a positive output voltage application, the switching frequency for that channel
runs that the rate set by the RT resistor value. Note that
the maximum output current at start-up is a function of
many variables including load profile, output capacitance,
target VOUT, VIN, switching frequency, so the user must
evaluate the performance of the LTM8049 to ensure that
it properly powers up its load.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8049. The LTM8049 is nevertheless a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 2
for a suggested layout. Ensure that the grounding and
heat-sinking are acceptable.
A few rules to keep in mind are:
Thermal Shutdown
1. Place the RFBX and RT resistors as close as possible to
their respective pins.
If the part is too hot, the LTM8049 engages its thermal
shutdown and terminates switching and discharges the
soft-start capacitor. When the part has cooled, the part automatically restarts. This thermal shutdown is set to engage at
temperatures above the 125°C absolute maximum internal
operating rating to ensure that it does not interfere with
functionality in the specified operating range. This means
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8049.
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8049.
GND
VIN1
RUN1 SS1 SYNC1 RT1
RT2 SYNC2 SS2 RUN2
VIN2
PG1 CLKOUT1 CLKOUT2 PG2
CIN1
GND
SHARE2
CIN2
GND
SHARE1
FBX1
FBX2
COUT1
VOUT1
(POSITIVE OUTPUT)
COUT2
GND
VOUT2
(NEGATIVE OUTPUT)
THERMAL/GND VIAS
GND
8049 F02
Figure 2. Layout Showing Suggested External Components, GND Plane and Thermal Vias
12
8049f
For more information www.linear.com/LTM8049
LTM8049
APPLICATIONS INFORMATION
4. Place the CIN and COUT capacitors such that their
ground current flow directly adjacent or underneath
the LTM8049.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8049.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 2. The LTM8049 can benefit from
the heat-sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8049. However, these capacitors
can cause problems if the LTM8049 is plugged into a live
input supply (see Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with
stray inductance in series with the power source forms an
underdamped tank circuit, and the voltage at the VIN pin
of the LTM8049 can ring to more than twice the nominal
input voltage, possibly exceeding the LTM8049’s rating and
damaging the part. If the input supply is poorly controlled
or the user will be plugging the LTM8049 into an energized
supply, the input network should be designed to prevent this
overshoot. This can be accomplished by installing a small
resistor in series to VIN, but the most popular method of
controlling input voltage overshoot is to add an electrolytic
bulk capacitor to the VIN net. This capacitor’s relatively high
equivalent series resistance damps the circuit and eliminates
the voltage overshoot. The extra capacitor improves low
frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is physically large.
Thermal Considerations
The LTM8049 output current may need to be derated if
it is required to operate in a high ambient temperature or
deliver a large amount of continuous power. The amount
of current derating is dependent upon the input voltage,
output power and ambient temperature. The temperature
rise curves given in the Typical Performance Characteristics section can be used as a guide. These curves were
generated by a LTM8049 mounted to a 58cm2 4-layer FR4
printed circuit board. Boards of other sizes and layer count
can exhibit different thermal behavior, so it is incumbent
upon the user to verify proper operation over the intended
system’s line, load and environmental operating conditions.
The thermal resistance numbers listed in Page 2 of the
data sheet are based on modeling the µModule package
mounted on a test board specified per JESD51-9 (Test
Boards for Area Array Surface Mount Package Thermal
Measurements). The thermal coefficients provided in this
page are based on JESD 51-12 (Guidelines for Reporting
and Using Electronic Package Thermal Information).
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, Page 2 of the data sheet typically gives four
thermal coefficients:
θJA: Thermal resistance from junction to ambient
θJCbottom: Thermal resistance from junction to the bottom
of the product case
θJCtop: Thermal resistance from junction to top of the
product case
θJB: Thermal resistance from junction to the printed circuit
board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
θJA is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
8049f
For more information www.linear.com/LTM8049
13
LTM8049
APPLICATIONS INFORMATION
still air although natural convection causes the air to move.
This value is determined with the part mounted to a JESD
51-9 defined test board, which does not reflect an actual
application or viable operating condition.
θJCbottom is the thermal resistance between the junction
and bottom of the package with all of the component power
dissipation flowing through the bottom of the package. In
the typical µModule converter, the bulk of the heat flows
out the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
θJCtop is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule converter are
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
θJB is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θJCbottom and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two sided,
two layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 3.
The blue resistances are contained within the µModule
converter, and the green are outside.
The die temperature of the LTM8049 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8049. The bulk of the heat flow out of the LTM8049
is through the bottom of the μModule converter and the
BGA pads into the printed circuit board. Consequently a
poor printed circuit board design can cause excessive
heating, resulting in impaired performance or reliability.
Please refer to the PCB Layout section for printed circuit
board design suggestions.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-CASE
CASE (BOTTOM)-TO-BOARD
(BOTTOM) RESISTANCE
RESISTANCE
AMBIENT
BOARD-TO-AMBIENT
RESISTANCE
8049 F03
µMODULE DEVICE
Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients
14
8049f
For more information www.linear.com/LTM8049
LTM8049
TYPICAL APPLICATIONS
±5V Converter
Maximum Load Current vs VIN
VIN1
4.7µF
×2
107k
750kHz
107k
750kHz
VOUT1P
FBX1
RUN1
RT1
SYNC2
RT2
45.3k
VOUT1N
CLKOUT1
47µF
LTM8049
VIN2
VOUT2P
FBX2
RUN2
SYNC1
2.0
VOUT1
5V
147µF
1.5
LOAD CURRENT (A)
VIN
2.7V TO 15V
1.0
0.5
60.4k
VOUT2
–5V
VOUT2N
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2, SHARE1, SHARE2
0
0
5
10
15
VIN (V)
8049 TA02a
8049 TA02b
Parallel 8V Outputs for Increased Current
VIN1
4.7µF
×2
80.6k
1MHz
Maximum Load Current vs VIN
VOUT1P
FBX1
RUN1
RT1
3.5
82.5k
VOUT1N
CLKOUT1
SYNC2
SHARE1
VOUT
8V
LTM8049
SHARE2
80.6k
1MHz
RT2
VIN2
RUN2
SYNC1
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2
VOUT2P
FBX2
VOUT2N
82.5k
47µF
LOAD CURRENT (A)
VIN
2.7V TO 20V
2.5
1.5
0.5
0
5
10
VIN (V)
15
20
8049 TA03b
8049 TA03a
8049f
For more information www.linear.com/LTM8049
15
LTM8049
PACKAGE DESCRIPTION
Pin Assignment Table
(Arranged by Pin Number)
PIN NAME
PIN NAME
A1 VOUT1P
B1 VOUT1P
C1 FBX1
D1 VOUT1N
E1
VOUT1N
F1
GND
A2 VOUT1P
B2 VOUT1P
B3 GND
C2 VOUT1N
C3 GND
D2 VOUT1N
D3 GND
E2
VOUT1N
F2
GND
E3
GND
F3
SHARE1
A3 GND
PIN NAME
PIN NAME
PIN NAME
PIN NAME
A4 GND
B4 GND
C4 GND
D4 GND
E4
GND
F4
SHARE2
A5 VIN1
B5 GND
C5 GND
D5 GND
E5
GND
F5
GND
A6 VIN1
B6 GND
C6 GND
D6 PG1
E6
CLKOUT1 F6
GND
A7 VIN1
B7 RUN1
C7 SS1
D7 SYNC1
E7
RT1
GND
PIN NAME
PIN NAME
F7
PIN NAME
PIN NAME
G1 VOUT2N
J1
FBX2
K1 VOUT2P
L1
VOUT2P
G2 VOUT2N
H1 VOUT2N
H2 VOUT2N
PIN NAME
J2
VOUT2N
K2 VOUT2P
L2
VOUT2P
G3 GND
H3 GND
J3
GND
K3 GND
L3
GND
G4 GND
H4 GND
J4
GND
K4 GND
L4
GND
G5 GND
H5 GND
J5
GND
K5 GND
L5
VIN2
G6 CLKOUT2 H6 PG2
J6
GND
K6 GND
L6
VIN2
G7 RT2
J7
SS2
K7 RUN2
L7
VIN2
H7 SYNC2
PACKAGE PHOTO
16
8049f
For more information www.linear.com/LTM8049
LTM8049
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM8049#packaging for the most recent package drawings.
BGA Package
77-Lead (15.00mm × 9.00mm × 2.42mm)
(Reference LTC DWG# 05-08-1964 Rev A)
A
aaa Z
E
Y
Z
X
SEE NOTES
DETAIL A
A2
7
G
SEE NOTES
PIN 1
3
A1
A
ccc Z
PIN “A1”
CORNER
B
4
C
b1
MOLD
CAP
b
D
E
SUBSTRATE
D
F
G
Z
H2
// bbb Z
F
H1
DETAIL B
H
J
e
Øb (77 PLACES)
K
ddd M Z X Y
eee M Z
L
aaa Z
7
PACKAGE TOP VIEW
3.810
2.540
DETAIL A
1.270
0.3175
0.3175
1.270
2.540
3.810
0.000
DETAIL B
PACKAGE SIDE VIEW
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
6.350
SUGGESTED PCB LAYOUT
TOP VIEW
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
2.22
0.50
1.72
0.60
0.60
0.27
1.45
5
4
3
2
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS
6.350
0.630 ±0.025 Ø 77x
6
PACKAGE BOTTOM VIEW
NOM
2.42
0.60
1.82
0.75
0.63
15.00
9.00
1.27
12.70
7.62
0.32
1.50
MAX
2.62
0.70
1.92
0.90
0.66
0.37
1.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 77
NOTES
3
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7
!
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
LTMXXXXXX
µModule
COMPONENT
PIN “A1”
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
BGA 77 0114 REV A
8049f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its information
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTM8049
17
LTM8049
TYPICAL APPLICATION
Parallel Outputs to Increase –5V Output Current
VIN1
4.7µF
×2
107k
750kHz
VOUT1P
FBX1
RUN1
RT1
Maximum Load Current vs VIN
100µF
×2
4
60.4k
VOUT1N
CLKOUT1
3
LOAD CURRENT (A)
VIN
2.7V TO 15V
SYNC2
SHARE1
LTM8049
SHARE2
107k
750kHz
RT2
VIN2
VOUT2P
RUN2
FBX2
SYNC1
1
60.4k
VOUT
–5V
VOUT2N
PINS NOT USED: SS1, SS2, PG1, PG2, CLKOUT2
2
0
8049 TA04a
0
5
10
VIN (V)
15
20
8049 TA04b
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENT
LTM8045
Single. Inverting or SEPIC µModule DC/DC Convertor
2.8 ≤ VIN ≤ 18V. ±2.5V ≤ VOUT ≤ ±15V. 6.25mm × 11.25mm × 4.92mm BGA
LTM8046
2kVAC, 2.75W Isolated DC/DC µModule Converter
3.1V ≤ VIN ≤ 31V, 1.8V ≤ VOUT ≤ 12V. 5V at 550mA from 24VIN,
9mm × 15mm × 4.92mm BGA
LTM8047
725kVDC, 1.5W Isolated DC/DC µModule Converter
3.1V ≤ VIN ≤ 32V, 2.5V ≤ VOUT ≤ 12V. 9mm × 11.25mm × 4.92mm BGA
LTM8048
725kVDC, 1.5W Isolated DC/DC µModule Converter with
Integrated LDO
3.1V ≤ VIN ≤ 32V, 1.2V ≤ LDO VOUT ≤ 12V. 9mm × 11.25mm × 4.92mm BGA
LTM8067
2kVAC, 2.25W Isolated DC/DC µModule Converter
2.8V ≤ VIN ≤ 40V, 2.5V ≤ VOUT ≤ 24V. 9mm × 11.25mm × 4.92mm BGA
LTM8068
2kVAC, 2.25W Isolated DC/DC µModule Converter with
Integrated LDO
2.8V ≤ VIN ≤ 40V, 1.2V ≤ LDO VOUT ≤ 18V. 9mm × 11.25mm × 4.92mm BGA
LTM8023
36VIN, 2A, Step-Down DC/DC µModule Converter. Can Be 3.6V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V. 9mm x 11.25mm x 2.82mm LGA.
Used for Inverting
9mm x 11.25mm x 3.52mm BGA
LTM8053
40VIN, 3.5A Step-Down DC/DC µModule Regulator. Can
be used for inverting.
18 Linear Technology Corporation
3.4V ≤ VIN ≤ 40V. 0.97V ≤ VOUT ≤ 15V. 6.25mm x 9mm x 3.32mm BGA.
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTM8049
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTM8049
8049f
LT 0816 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2016