DCR1570L65 Phase Control Thyristor Preliminary Information DS5812-1.4 June 2008 (LN26206) FEATURES KEY PARAMETERS Double Side Cooling High Surge Capability VDRM IT(AV) ITSM dV/dt* dI/dt APPLICATIONS 6500V 1568A 22000A 1500V/µs 300A/µs * Higher dV/dt selections available High Power Drives High Voltage Power Supplies Static Switches VOLTAGE RATINGS Part and Ordering Number DCR1570L65* DCR1570L60 DCR1570L55 DCR1570L50 Repetitive Peak Voltages VDRM and VRRM V 6500 6000 5500 5000 Conditions Tvj = -40°C to 125°C, IDRM = IRRM = 300mA, VDRM, VRRM tp = 10ms, VDSM & VRSM = VDRM & VRRM + 100V respectively Lower voltage grades available. 0 0 * 6200V @ -40 C, 6500V @ 0 C ORDERING INFORMATION When ordering, select the required part number shown in the Voltage Ratings selection table. Outline type code: L (See Package Details for further information) Fig. 1 Package outline For example: DCR1570L65 Note: Please use the complete part number when ordering and quote this number in any future correspondence relating to your order. 1/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR CURRENT RATINGS Tcase = 60°C unless stated otherwise Parameter Symbol Test Conditions Max. Units 1570 A Double Side Cooled IT(AV) Mean on-state current IT(RMS) RMS value - 2466 A Continuous (direct) on-state current - 2340 A IT Half wave resistive load SURGE RATINGS Parameter Symbol ITSM 2 It Surge (non-repetitive) on-state current Test Conditions Max. Units 10ms half sine, Tcase = 125°C 22.0 kA VR = 0 2.42 MA s Min. Max. Units 2 I t for fusing 2 THERMAL AND MECHANICAL RATINGS Symbol Rth(j-c) Rth(c-h) Tvj Parameter Thermal resistance – junction to case Thermal resistance – case to heatsink Virtual junction temperature Test Conditions Double side cooled DC - 0.0117 °C/W Single side cooled Anode DC - 0.0187 °C/W Cathode DC - 0.0329 °C/W Clamping force 37kN Double side - 0.0025 °C/W (with mounting compound) Single side - 0.005 °C/W On-state (conducting) - 135 °C Reverse (blocking) - 125 °C Tstg Storage temperature range -55 125 °C Fm Clamping force 33 41 kN 2/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR DYNAMIC CHARACTERISTICS Symbol IRRM/IDRM Parameter Test Conditions Min. Max. Units Peak reverse and off-state current At VRRM/VDRM, Tcase = 125°C - 300 mA dV/dt Max. linear rate of rise of off-state voltage To 67% VDRM, Tj = 125°C, gate open - 1500 V/µs dI/dt Rate of rise of on-state current From 67% VDRM to 2x IT(AV) Repetitive 50Hz - 150 A/µs Gate source 30V, 10, Non-repetitive - 300 A/µs tr < 0.5µs, Tj = 125°C VT(TO) rT tgd Threshold voltage – Low level 100A to 1500A at Tcase = 125°C - 1.0 V Threshold voltage – High level 1500A to 7200A at Tcase = 125°C - 1.2 V On-state slope resistance – Low level 100A to 1500A at Tcase = 125°C - 0.615 m On-state slope resistance – High level 1500A to 7200A at Tcase = 125°C - 0.5 m VD = 67% VDRM, gate source 30V, 10 - 3 µs - 1200 µs 2000 4500 µC Delay time tr = 0.5µs, Tj = 25°C tq Turn-off time Tj = 125°C, VR = 200V, dI/dt = 1A/µs, dVDR/dt = 20V/µs linear QS Stored charge IT = 2000A, Tj = 125°C, dI/dt – 1A/µs, IL Latching current Tj = 25°C, VD = 5V - 3 A IH Holding current Tj = 25°C, RG-K = , ITM = 500A, IT = 5A - 300 mA 3/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR GATE TRIGGER CHARACTERISTICS AND RATINGS Symbol Parameter Test Conditions Max. Units VGT Gate trigger voltage VDRM = 5V, Tcase = 25°C 1.5 V VGD Gate non-trigger voltage At 50% VDRM, Tcase = 125°C 0.4 V IGT Gate trigger current VDRM = 5V, Tcase = 25°C 250 mA IGD Gate non-trigger current At 50% VDRM, Tcase = 125°C 15 mA CURVES Instantaneous on-state current IT - (A) 7000 6000 5000 4000 3000 2000 min 125°C max 125°C min 25°C max 25°C 1000 0 1.0 2.0 3.0 4.0 5.0 Instantaneous on-state voltage VT - (V) Fig.2 Maximum & minimum on-state characteristics VTM EQUATION VTM = A + Bln (IT) + C.IT+D.IT Where A = 0.666848 B = 0.033446 C = 0.000418 D = 0.009666 these values are valid for Tj = 125°C for IT 100A to 7200A 4/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR 130 10 120 o Maximum case temperature, T case ( C ) 11 Mean power dissipation - (kW) 9 8 7 6 5 180 4 120 3 90 2 60 1 30 90 100 60 90 30 80 70 60 50 40 30 20 10 0 0 1000 2000 3000 0 500 1000 1500 2000 2500 Mean on-state current, IT(AV) - (A) Mean on-state current, IT(AV) - (A) Fig.3 On-state power dissipation – sine wave Fig.4 Maximum permissible case temperature, double side cooled – sine wave 130 180 120 110 100 120 12 90 11 Mean power dissipation - (kW) o 120 110 0 Maximum heatsink temperature, T Heatsink - ( C ) 180 60 90 30 80 70 60 50 40 30 20 10 10 9 8 7 6 d.c. 5 180 4 120 90 3 60 2 30 1 0 0 0 500 1000 1500 2000 2500 Mean on-state current, IT(AV) - (A) Fig.5 Maximum permissible heatsink temperature, double side cooled – sine wave 0 1000 2000 3000 4000 Mean on-state current, IT(AV) - (A) Fig.6 On-state power dissipation – rectangular wave 5/10 www.dynexsemi.com DCR1570L65 130 130 d.c. 120 Maximum heatsik temperature T heatsink - (oC) Maximum permissible case temperature , Tcase - (°C) SEMICONDUCTOR 180 110 120 100 90 90 60 80 30 70 60 50 40 30 20 10 0 d.c. 120 180 110 120 100 90 90 60 80 30 70 60 50 40 30 20 10 0 0 1000 2000 3000 4000 0 Mean on-state current, IT(AV) - (A) 1000 2000 Fig.7 Maximum permissible case temperature, double side cooled – rectangular wave Anode side cooled 35 Cathode side cooled 2 2.6074 3 4.2073 0.008639 0.0533503 0.3309504 1.612 0.9647 2.8312 4.9433 9.909 0.0096096 0.0627037 0.4198958 8.908 0.9285 2.9366 2.3581 26.683 0.0093033 0.0621535 0.3092235 5.835 Ri (°C/kW) Ti (s) Double Side Cooling Anode Side Cooling Cathode Sided Cooling 1 0.8342 Ri (°C/kW) Ti (s) Thermal Impedance, Zthj-c ( °C/kW) 4000 Fig.8 Maximum permissible heatsink temperature, double side cooled – rectangular wave Double side cooled 30 3000 Mean on-state current, IT(AV) - (A) Ri (°C/kW) Ti (s) 4 4.041 Zth = [Ri x ( 1-exp. (t/ti))] 25 Rth(j-c) Conduction 20 Tables show the increments of thermal resistance R th(j-c) when the device operates at conduction angles other than d.c. 15 Double side cooling Zth (z) 10 5 0 0.001 0.01 0.1 1 10 100 ° 180 120 90 60 30 15 sine. 1.45 1.68 1.93 2.16 2.34 2.42 rect. 0.98 1.40 1.64 1.90 2.19 2.34 Anode Side Cooling Zth (z) ° 180 120 90 60 30 15 sine. 1.43 1.66 1.90 2.12 2.30 2.37 rect. 0.97 1.39 1.62 1.88 2.15 2.30 Cathode Sided Cooling Zth (z) ° 180 120 90 60 30 15 sine. 1.44 1.66 1.91 2.14 2.31 2.39 rect. 0.97 1.39 1.63 1.89 2.17 2.31 Time ( s ) Fig.9 Maximum (limit) transient thermal impedance – junction to case (°C/kW) 6/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR 50 10 Conditions: Tcase= 125°C VR = 0 half-sine wave 40 ITSM 20 4 2 It 10 1 6 2 30 2 0 1 10 100 2 10 8 I t (MA s) Conditions: Tcase = 125°C VR =0 Pulse width = 10ms Surge current, ITSM - (kA) Surge current, ITSM- (kA) 100 0 1 10 100 Pulse width, tP - (ms) Number of cycles Fig.10 Multi-cycle surge current Fig.11 Single-cycle surge current 25000 700 Reverse recovery current, IRR - (A) Qs (Max) = 5265.1*(di/dt)0.4473 Stored Charge, Qs- (uC) 20000 15000 Qs(Min)=2592.3*(di/dt)0.5818 10000 Conditions: Tj = 125° C, VRpeak ~ 4500V VRM ~ 3000V snubber as appropriate to control reverse voltages 5000 5 10 15 20 25 30 Rate of change of on-state current, di/dt - (A/us) Fig.12 Reverse recovery charge 600 500 400 300 Irr (Min)= 37.17*(di/dt)0.8012 Conditions: Tj = 125° C, VRpeak ~ 4500V VRM ~ 3000V snubber as appropriate to control reverse voltages 200 100 0 0 Irr (Max) = 53.831*(di/dt)0.729 0 0 5 10 15 20 25 30 Rate of decay of on-state current, di/dt - (A/us) Fig.13 Reverse recovery current 7/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR 10 9 Pulse Width us 100 200 500 1000 10000 Gate trigger voltage, VGT - (V) 8 7 Pulse Power PGM (Watts) Frequency Hz 50 100 150 150 150 150 150 150 150 100 20 - 400 150 125 100 25 - Upper Limit 6 5 Preferred gate drive area 4 3 2 o 1 Tj = -40oC Tj = 25oC Lower Limit Tj = 125 C 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Gate trigger current IGT, - (A) Fig14 Gate Characteristics 30 Lower Limit Upper Limit 5W 10W 20W 50W 100W 150W -40C Gate trigger voltage, VGT - (V) 25 20 15 10 5 0 0 1 2 3 4 5 6 7 8 9 10 Gate trigger current, IGT - (A) Fig. 15 Gate characteristics 8/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR PACKAGE DETAILS For further package information, please contact Customer Services. All dimensions in mm, unless stated otherwise. DO NOT SCALE. 3rd ANGLE PROJECTION DO NOT SCALE IF IN DOUBT ASK HOLE Ø3.60 X 2.00 DEEP (IN BOTH ELECTRODES) 20° OFFSET (NOM.) TO GATE TUBE Device DCR1374SBA18 DCR1375SBA28 DCR1376SBA36 DCR2690L22 DCR2480L28 DCR2040L42 DCR1850L52 DCR1570L65 DCR1300L85 Maximum Minimum Thickness Thickness (mm) (mm) 34.515 33.965 34.59 34.04 34.82 34.27 34.515 33.965 34.59 34.04 34.82 34.27 34.94 34.39 35.2 34.65 35.56 35.01 Ø98.9 MAX. Ø62.85 NOM. Ø1.5 CATHODE GATE ANODE Ø62.85 NOM. FOR PACKAGE HEIGHT SEE TABLE Nominal weight: 1500g Clamping force: 37kN ±10% Lead length: 420mm Lead terminal connector: M4 ring Package outline type code: L Fig.16 Package outline 9/10 www.dynexsemi.com DCR1570L65 SEMICONDUCTOR POWER ASSEMBLY CAPABILITY The Power Assembly group was set up to provide a support service for those customers requiring more than the basic semiconductor, and has developed a flexible range of heatsink and clamping systems in line with advances in device voltages and current capability of our semiconductors. We offer an extensive range of air and liquid cooled assemblies covering the full range of circuit designs in general use today. The Assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our customers. Using the latest CAD methods our team of design and applications engineers aim to provide the Power Assembly Complete Solution (PACs). HEATSINKS The Power Assembly group has its own proprietary range of extruded aluminium heatsinks which have been designed to optimise the performance of Dynex semiconductors. Data with respect to air natural, forced air and liquid cooling (with flow rates) is available on request. For further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or Customer Services. Stresses above those listed in this data sheet may cause permanent damage to the device. In extreme conditions, as with all semiconductors, this may include potentially hazardous rupture of the package. Appropriate safety precautions should always be followed. http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln Lincolnshire, LN6 3LF. United Kingdom. Tel: +44(0)1522 500500 Fax: +44(0)1522 500550 CUSTOMER SERVICE Tel: +44(0)1522 502753 / 502901. Fax: +44(0)1522 500020 Dynex Semiconductor 2003 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRODUCED IN UNITED KINGDOM. This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company’s conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. 10/10 www.dynexsemi.com