Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 LMH6622 Dual Wideband, Low Noise, 160 MHz, Operational Amplifiers 1 Features 3 Description • The LMH6622 is a dual high speed voltage feedback operational amplifier specifically optimized for low noise. A voltage noise specification of 1.6nV/√Hz, a current noise specification 1.5pA/√Hz, a bandwidth of 160 MHz, and a harmonic distortion specification that exceeds 90 dBc combine to make the LMH6622 an ideal choice for the receive channel amplifier in ADSL, VDSL, or other xDSL designs. The LMH6622 operates from ±2.5 V to ±6 V in dual supply mode and from +5 V to +12 V in single supply configuration. The LMH6622 is stable for AV ≥ 2 or AV ≤ −1. The fabrication of the LMH6622 on TI's advanced VIP10 process enables excellent (160 MHz) bandwidth at a current consumption of only 4.3 mA/amplifier. Packages for this dual amplifier are the 8-lead SOIC and the 8-lead VSSOP. 1 • • • • • • • • • • VS = ±6 V, TA = 25°C, Typical Values Unless Specified Bandwidth (AV = +2) 160 MHz Supply Voltage Range ±2.5 V to ±6 V; + 5 V to +12 Slew Rate 85V/μs Supply Current 4.3 mA/amp Input Common Mode Voltage −4.75 V to +5.7 V Output Voltage Swing (RL = 100 Ω) ±4.6 V Input Voltage Noise 1.6 nV/√Hz Input Current Noise 1.5 pA/√Hz Linear Output Current 90 mA Excellent Harmonic Distortion 90 dBc Device Information(1) 2 Applications • • • • • PART NUMBER xDSL Receiver Low Noise Instrumentation Front End Ultrasound Preamp Active Filters Cellphone Basestation PACKAGE BODY SIZE (NOM) LMH6622 SOIC (8) 4.90 mm × 3.91 mm LMH6622 VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. XDSL Analog Front End RECEIVE PRE-AMP ADC ADC LMH6622 1:N HYBRID COUPLER LMH6643 TELEPHONE LINE LMH6672 DAC DAC BUFFER/FILTER LINE DRIVER 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 6 9 Absolute Maximum Ratings ...................................... Handling Ratings....................................................... Recommended Operating Conditions....................... Thermal Information .................................................. ±6 V Electrical Characteristics .................................. ±2.5 V Electrical Characteristics ............................... Typical Performance Characteristics ........................ 7 Parameter Measurement Information ................ 14 8 Detailed Description ............................................ 16 7.1 Test Circuits ............................................................ 14 8.1 Overview ................................................................. 16 8.2 Functional Block Diagram ....................................... 16 8.3 Feature Description................................................. 16 8.4 Device Functional Modes........................................ 16 9 Application and Implementation ........................ 17 9.1 9.2 9.3 9.4 DSL Receive Channel Applications ........................ Receive Channel Noise Calculation........................ Differential Analog-to-Digital Driver......................... Typical Application ................................................. 17 19 20 21 10 Power Supply Recommendations ..................... 22 10.1 Driving Capacitive Load ........................................ 22 11 Layout................................................................... 22 11.1 Layout Guidelines ................................................. 22 11.2 Layout Examples................................................... 23 12 Device and Documentation Support ................. 25 12.1 Trademarks ........................................................... 25 12.2 Electrostatic Discharge Caution ............................ 25 12.3 Glossary ................................................................ 25 13 Mechanical, Packaging, and Orderable Information ........................................................... 25 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E Page • Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information ........................................................................ 1 • Changed RG to RC. Changed AV from +10 to +9 for Figure 38 ............................................................................................ 20 • Changed RG to RC. Changed AV from +10 to +9 for Figure 39 ............................................................................................ 20 Changes from Revision C (March 2013) to Revision D • 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 5 Pin Configuration and Functions 8-Pin SOIC and VSSOP D and DGK Packages (Top View) Pin Functions PIN I/O DESCRIPTION NAME NO. OUT A 1 O ChA Output -IN A 2 I ChA Inverting Input +IN A 3 I ChA Non-inverting Input V- 4 I V- Supply Pin +IN B 5 I ChB Non-inverting Input -IN B 6 I ChB Inverting Input OUT B 7 I ChB Output V+ 8 I V+ Supply Pin Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 3 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) MAX UNIT VIN Differential MIN ±1.2 V Supply Voltage (V+ – V−) 13.2 V V+ +0.5, V− −0.5 V 235 °C 260 °C +150 °C Voltage at Input Pins SOLDERING INFORMATION Infrared or Convection (20 sec) Wave Soldering (10 sec) Junction Temperature (1) (2) (3) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board. 6.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) (3) Electrostatic discharge MIN MAX UNIT −65° +150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 (2) Charged device model (CDM), per JEDEC specification JESD22C101, all pins (3) 200 (2) V JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Human body model, 1.5 kΩ in series with 100 pF. Machine model, 0 Ω in series with 200 pF. JEDEC document JEP157 states that 200-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) MIN MAX Supply Voltage (V+– V−) ±2.25 ±6 V Temperature Range (2) (3) −40 +85 °C (1) (2) (3) UNIT Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board. 6.4 Thermal Information THERMAL METRIC (1) RθJA (1) (2) 4 Junction-to-ambient thermal resistance (2) LMH6622 LMH6622 Package D Package DGK 8 PINS 8 PINS 166° 211° UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/RθJA. All numbers apply for packages soldered directly onto a PC board. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 6.5 ±6 V Electrical Characteristics Unless otherwise specified, TJ = 25°C, V+ = 6 V, V− = −6 V, VCM = 0 V, AV = +2, RF = 500 Ω, RL = 100 Ω. Some limits apply at the temperature extremes as noted in the table. PARAMETER TEST CONDITIONS TEMPERATURE EXTREMES MIN (1) TYP (2) ROOM TEMPERATURE MAX (1) MIN (1) TYP (2) UNIT MAX (1) DYNAMIC PERFORMANCE −3dB BW VO = 200 mVPP 160 MHz BW0.1dB 0.1dB Gain Flatness VO = 20 0mVPP 30 MHz VO = 2 VPP 85 V/μs VO = 2 VPP to ±0.1% 40 VO = 2 VPP to ±1.0% 35 fCL (3) SR Slew Rate TS Settling Time ns Tr Rise Time VO = 0.2 V Step, 10% to 90% 2.3 ns Tf Fall Time VO = 0.2 V Step, 10% to 90% 2.3 ns DISTORTION and NOISE RESPONSE en Input Referred Voltage Noise f = 100 kHz in Input Referred Current Noise f = 100 kHz DG Differential Gain RL = 150 Ω, RF = 470 Ω, NTSC 0.03% DP Differential Phase RL = 150 Ω, RF = 470 Ω, NTSC 0.03 HD2 2nd Harmonic Distortion fc = 1 MHz, VO = 2 VPP, RL = 100 Ω −90 fc = 1 MHz, VO = 2 VPP, RL = 500 Ω −100 fc = 1 MHz, VO = 2 VPP, RL = 100 Ω −94 fc = 1 MHz, VO = 2 VPP, RL = 500 Ω −100 HD3 MTPR 3rd Harmonic Distortion Upstream Downstream nV/√Hz 1.6 pA/√Hz 1.5 deg dBc dBc VO = 0.6 VRMS, 26 kHz to 132 kHz (see Figure 33) −78 VO = 0.6 VRMS, 144 kHz to 1.1 MHz (see Figure 33) −70 dBc INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0 V VCM = 0 V IOS Input Offset Current VCM = 0V IB Input Bias Current VCM = 0V RIN Input Resistance Common Mode CIN Input Capacitance CMRR (1) (2) (3) (4) +2 −1.2 +0.2 −1.5 1.5 −1 −0.04 1 4.7 10 +1.2 −2.5 TC VOS Input Offset Average Drift CMVR −2 (4) 15 mV μV/°C μA μA 17 MΩ Differential Mode 12 kΩ Common Mode 0.9 pF Differential Mode 1.0 pF Input Common Mode Voltage Range CMRR ≥ 60dB −4.75 Common-Mode Rejection Ratio Input Referred, VCM = −4.2 V to +5.2 V 75 5.5 +5.7 80 100 −4.5 V dB All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 5 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com ±6 V Electrical Characteristics (continued) Unless otherwise specified, TJ = 25°C, V+ = 6 V, V− = −6 V, VCM = 0 V, AV = +2, RF = 500 Ω, RL = 100 Ω. Some limits apply at the temperature extremes as noted in the table. PARAMETER TEST CONDITIONS TEMPERATURE EXTREMES MIN (1) TYP (2) ROOM TEMPERATURE MAX (1) UNIT MIN (1) TYP (2) MAX (1) 74 83 dB −75 dB TRANSFER CHARACTERISTICS AVOL Large Signal Voltage Gain VO = 4 VPP Xt Crosstalk f = 1 MHz 70 OUTPUT CHARACTERISTICS VO Output Swing No Load, Positive Swing 4.6 4.8 −4.4 No Load, Negative Swing RL = 100 Ω, Positive Swing 3.8 4.0 RL = 100 Ω, Negative Swing 5.2 −5.0 −3.8 4.6 −4.6 RO Output Impedance f = 1 MHz ISC Output Short Circuit Current Sourcing to Ground ΔVIN = 200 mV (5), (6) 100 135 Sinking to Ground ΔVIN = −200 mV (5), (6) 100 130 IOUT Output Current −4.6 V −4 Ω 0.08 mA Sourcing, VO = +4.3 V Sinking, VO = −4.3 V mA 90 POWER SUPPLY +PSRR Positive Power Supply Rejection Ratio Input Referred, VS = +5 V to +6 V 74 80 95 −PSRR Negative Power Supply Rejection Ratio Input Referred, VS = −5 V to −6 V 69 75 90 IS Supply Current (per amplifier) No Load (5) (6) dB 6.5 4.3 6 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ ±2.5 V, at room temperature and below. For VS > ±2.5 V, allowable short circuit duration is 1.5ms. 6.6 ±2.5 V Electrical Characteristics Unless otherwise specified, TJ = 25°C, V+ = 2.5 V, V− = −2.5 V, VCM = 0 V, AV = +2, RF = 500 Ω, RL = 100 Ω. Some limits apply at the temperature extremes as noted in the table. PARAMETER TEST CONDITIONS TEMPERATURE EXTREMES MIN (1) TYP (2) MAX (1) ROOM TEMPERATURE MIN (1) TYP (2) UNIT MAX (1) DYNAMIC PERFORMANCE fCL −3 dB BW BW0.1dB 0.1dB Gain Flatness (3) SR Slew Rate TS Settling Time VO = 200 mVPP 150 MHz VO = 200 mVPP 20 MHz VO = 2 VPP 80 V/μs VO = 2 VPP to ±0.1% 45 VO = 2 VPP to ±1.0% 40 ns Tr Rise Time VO = 0.2 V Step, 10% to 90% 2.5 ns Tf Fall Time VO = 0.2 V Step, 10% to 90% 2.5 ns (1) (2) (3) 6 All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Slew rate is the slowest of the rising and falling slew rates. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 ±2.5 V Electrical Characteristics (continued) Unless otherwise specified, TJ = 25°C, V+ = 2.5 V, V− = −2.5 V, VCM = 0 V, AV = +2, RF = 500 Ω, RL = 100 Ω. Some limits apply at the temperature extremes as noted in the table. PARAMETER TEST CONDITIONS TEMPERATURE EXTREMES MIN (1) TYP (2) ROOM TEMPERATURE MAX (1) MIN (1) TYP (2) UNIT MAX (1) DISTORTION and NOISE RESPONSE en Input Referred Voltage Noise f = 100 kHz in Input Referred Current Noise f = 100 kHz HD2 2nd Harmonic Distortion fc = 1 MHz, VO = 2VPP, RL = 100 Ω −88 fc = 1 MHz, VO = 2VPP, RL = 500 Ω −98 fc = 1 MHz, VO = 2 VPP, RL = 100 Ω −92 fc = 1 MHz, VO = 2 VPP, RL = 500 Ω −100 HD3 MTPR 3rd Harmonic Distortion Upstream Downstream nV/√Hz 1.7 pA/√Hz 1.5 dBc dBc VO = 0.4VRMS, 26kHz to 132kHz (see Figure 33) −76 VO = 0.4 VRMS, 144 kHz to 1.1 MHz (see Figure 33) −68 dBc INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0 V −2.3 +2.3 −1.5 +0.3 −2.5 2.5 −1.5 +0.01 1.5 μA 4.6 10 μA (4) +1.5 −2.5 mV μV/°C TC VOS Input Offset Average Drift VCM = 0 V IOS Input Offset Current VCM = 0 V IB Input Bias Current VCM = 0 V RIN Input Resistance Common Mode 17 MΩ Differential Mode 12 kΩ Common Mode 0.9 pF 15 CIN Input Capacitance CMVR Input Common Mode Voltage Range CMRR ≥ 60dB Common Mode Rejection Ratio Input Referred, VCM = −0.7 V to +1.7 V Differential Mode CMRR 1.0 −1.25 75 pF −1 V 2 +2.2 80 100 74 82 dB −75 dB dB TRANSFER CHARACTERISTICS AVOL Large Signal Voltage Gain VO = 1 VPP Xt Crosstalk f = 1 MHz (4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 7 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com ±2.5 V Electrical Characteristics (continued) Unless otherwise specified, TJ = 25°C, V+ = 2.5 V, V− = −2.5 V, VCM = 0 V, AV = +2, RF = 500 Ω, RL = 100 Ω. Some limits apply at the temperature extremes as noted in the table. PARAMETER TEST CONDITIONS TEMPERATURE EXTREMES MIN (1) TYP (2) ROOM TEMPERATURE MAX (1) MIN (1) TYP (2) 1.4 1.7 UNIT MAX (1) OUTPUT CHARACTERISTICS VO Output Swing No Load, Positive Swing 1.2 −1 No Load, Negative Swing RL = 100 Ω, Positive Swing 1 RL = 100 Ω, Negative Swing −1.5 1.2 −0.9 −1.4 RO Output Impedance f = 1 MHz ISC Output Short Circuit Current Sourcing to Ground ΔVIN = 200 mV (5) (6) 100 137 Sinking to Ground ΔVIN = −20 0mV (5) (6) 100 134 IOUT Output Current −1.2 1.5 V −1.1 Ω 0.1 mA Sourcing, VO = +0.8 V Sinking, VO = −0.8 V mA 90 POWER SUPPLY +PSRR Positive Power Supply Rejection Ratio Input Referred, VS = +2.5 V to +3 V 72 78 93 −PSRR Negative Power Supply Rejection Ratio Input Referred, VS = −2.5 V to −3 V 70 75 88 IS Supply Current (per amplifier) No Load (5) (6) 8 6.4 4.1 dB dB 5.8 mA Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Short circuit test is a momentary test. Output short circuit duration is infinite for VS ≤ ±2.5 V, at room temperature and below. For VS > ±2.5 V, allowable short circuit duration is 1.5ms. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 6.7 Typical Performance Characteristics 100 100 100 VS = ±6V VOLTAGE 1 1 CURRENT 0.1 10 1 100 1k 10k 100k 1M 0.1 10M VOLTAGE NOISE (nV/ Hz) 10 10 CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) VS = ±2.5V 10 10 VOLTAGE 1 1 CURRENT 0.1 10 1 100 Figure 1. Current and Voltage Noise vs. Frequency NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 VIN = 700mVPP, BW = 33MHz -2 VIN = 450mVPP, BW = 50MHz VIN = 200mVPP, BW = 103MHz 10k 100k 1M AV = +2 +3 VIN = 14mVPP, BW = 190MHz +2 +1 0 -1 -2 VIN = 700mVPP, BW = 35MHz VIN = 450mVPP, BW = 55MHz -3 -4 VIN = 100mVPP, BW = 154MHz -5 1k VS = ±6V +4 +1 -4 VIN = 200mVPP, BW = 114MHz VIN = 100mVPP, BW = 164MHz 10M 100M -5 1k 500 M 10k FREQUENCY (Hz) 1M 100k 10M 100M FREQUENCY (Hz) 5 VSS = ±6V 5 VSS = ±6V 4 RF = 500: 4 RF = 500: 3 VIN = 3 VIN = 100mVPP 2 AV = -1, BW = 187MHz 0 -1 AV = -2, BW = 110MHz -2 AV = -5, BW = 45MHz -3 -4 -5 1 k AV = -10, BW = 30MHz 1 10 10M 100k M k FREQUENCY 500 M Figure 4. Frequency Response vs. Input Signal Level NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) Figure 3. Frequency Response vs. Input Signal Level 1 0.1 10M +5 VIN = 14mVPP, BW = 186MHz -3 1M Figure 2. Current and Voltage Noise vs. Frequency + 5 VS = ±2.5V +4 AV = +2 +3 -1 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) +2 1k CURRENT NOISE (pA/ Hz) 100 100mVPP 2 AV = +2, BW = 166MHz 1 0 -1 AV = +3, BW = 96MHz -2 AV = +5, BW = 45MHz -3 -4 -5 100M AV = +10, BW = 21MHz 1 k 10 k 1 10M 100k M FREQUENCY 100M (Hz) (Hz) Figure 5. Inverting Amplifier Frequency Response Figure 6. Non-Inverting Amplifier Frequency Response Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 9 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com Typical Performance Characteristics (continued) 90 270° 80 234° 70 198° GAIN -30°C PHASE 126° 90° 40 54° 30 -30°C PHASE (°) GAIN (dB) 50 CROSSTALK (dB) 162° 60 25°C 20 85°C 25°C 18° -18° 10 85°C -54° 0 -10 1k 10k 10 100k 1M FREQUENCYM (Hz) -90° 100M 500M 0 VS = ±6V, ±2.5V VS = ±2.5V 10 VIN = 200mVpp -20 AV = +2 VS = ±6V 30 -40 50 CHANNEL 1 OUTPUT VS = ±2.5V 60 70 VS = ±6V 80 -90 CHANNEL 2 OUTPUT 100 100 100 10M 1M M k FREQUENCY (Hz) Figure 8. Crosstalk vs. Frequency Figure 7. Open Loop Gain and Phase Response 0 -50 -10 -55 +PSRR -20 -60 -30 -65 VS = ±2.5V -50 -70 VS = ±6V VS = ±6V VS = ±2.5V -60 dB dB -40 -75 -80 -70 -85 -PSRR -80 -90 -90 -95 -100 10k -100 100k 1M 10M Figure 10. CMRR vs. Frequency Figure 9. PSRR vs. Frequency 2.5 2.5 VS = ±2.5V VOUT REFERENCED TO V (V) 2.1 - + VOUT REFERENCED TO V (V) 2.3 1.9 1.7 1.5 1.3 1.1 0. 9 0.7 0.5 0.01 2.3 2.1 1.9 1.7 1.5 VS = ±2.5V 1.3 1.1 0.9 0.7 VS = ±6V VS = ±6V 0.5 0.01 10 0.1 100 1 1000 OUTPUT SOURCING CURRENT (mA) Figure 11. Positive Output Swing vs. Source Current 10 1M 2M 100k 10k FREQUENCY (Hz) 1k 100M FREQUENCY (Hz) 0.1 1 10 100 1000 OUTPUT SINKING CURRENT (mA) Figure 12. Negative Output Swing vs. Sink Current Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 Typical Performance Characteristics (continued) 50mV/DIV 50mV/DIV 100nS 100nS INPUT INPUT 100mV/DIV 100mV/DIV OUTPUT OUTPUT Figure 13. Non-Inverting Small Signal Pulse Response VS = ±2.5 V, RL = 100 Ω, AV = +2, RF = 500 Ω 500mV/DIV Figure 14. Non-Inverting Small Signal Pulse Response VS = ±6 V, RL = 100 Ω, AV = +2, RF = 500 Ω 500mV/DIV 100nS 100nS INPUT INPUT 1V/DIV 1V/DIV OUTPUT OUTPUT Figure 15. Non-Inverting Large Signal Pulse Response VS = ±2.5 V, RL = 100 Ω, AV = +2, RF = 500 Ω 0 VS = ±2.5V f = 1MHz AV = +2 -20 HARMONIC DISTORTION -dBc HARMONIC DISTORTION -dBc 0 RL = 100: -40 Figure 16. Non-Inverting Large Signal Pulse Response VS = ±6 V, RL = 100 Ω, AV = +2, RF = 500 Ω -60 -80 HD2 -100 VS = ±6V f = 1MHz -20 AV = +2 RL = 100: -40 -60 HD2 -80 -100 HD3 HD3 -120 -120 0 200 400 600 800 1000 0 500 1000 1500 2000 VIN (mVPP) VIN (mVPP) Figure 17. Harmonic Distortion vs. Input Signal Level Figure 18. Harmonic Distortion vs. Input Signal Level Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 11 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com Typical Performance Characteristics (continued) 0 0 VS = ±6V VIN = 1VPP -20 HARMONIC DISTORTION -dBc HARMONIC DISTORTION -dBc VS = ±2.5V AV = +2 RL = 100: -40 -60 HD2 -80 -100 VIN = 1VPP -20 AV = +2 RL = 100: -40 -60 HD2 -80 -100 HD3 HD3 -120 -120 500 0 1500 1000 2000 0 500 FREQUENCY (kHz) Figure 19. Harmonic Distortion vs. Frequency Figure 20. Harmonic Distortion vs. Frequency 0 VS = ±2.5V f = 1MHz -20 HARMONIC DISTORTION -dBc HARMONIC DISTORTION -dBc 0 AV = +2 RL = 500: -40 -60 HD2 -80 -100 VS = ±6V f = 1MHz -20 AV = +2 RL = 500: -40 -60 HD2 -80 -100 HD3 HD3 -120 -120 0 400 200 800 600 1000 0 1000 500 2000 1500 VIN (mVPP) VIN (mVPP) Figure 21. Harmonic Distortion vs. Input Signal Level Figure 22. Harmonic Distortion vs. input Signal Level 0 0 VS = ±6V VIN = 1VPP -20 HARMONIC DISTORTION -dBc HARMONIC DISTORTION -dBc VS = ±2.5V AV = +2 RL = 500: -40 -60 -80 HD2 -100 -20 VIN = 1VPP AV = +2 -40 RL = 500: -60 HD2 -80 -100 HD3 HD3 -120 0 12 2000 1500 1000 FREQUENCY (kHz) 500 1000 1500 2000 -120 0 500 1000 1500 2000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 23. Harmonic Distortion vs. Input Frequency Figure 24. Harmonic Distortion vs. Input Frequency Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 Typical Performance Characteristics (continued) 0 0 VS = ±2.5V -10 VO = 0.407VRMS -20 RF = 500: VS = ±2.5V -10 MTPR (dBc) MTPR (dBc) RL = 437: -40 -50 RG = 174: RL = 437: -30 -40 -50 -60 -60 -70 -80 102.8 RF = 500: -20 RG = 174: -30 VO = 0.396VRMS 104.8 106.8 108.8 110.8 -70 551.3 112.8 553.3 FREQUENCY (kHz) 559.3 561.3 Figure 26. Full Rate ADSL (DMT) Downstream MTPR @ VS = ±2.5 V 0 0 VS = ±6V VS = ±6V -10 VO = 0.611VRMS -20 RF = 500: RL = 437: -40 -10 VO = 0.597VRMS -20 RF = 500: RG = 174: RG = 174: -30 MTPR (dBc) MTPR (dBc) 557.3 FREQUENCY (kHz) Figure 25. Full Rate ADSL (DMT) Upstream MTPR @ VS = ±2.5 V -50 -60 -30 RL = 437: -40 -50 -60 -70 -70 -80 -90 102.8 555.3 104.8 106.8 108.8 110.8 -80 551.3 112.8 553.3 555.3 557.3 559.3 561.3 FREQUENCY (kHz) FREQUENCY (kHz) Figure 27. Full Rate ADSL (DMT) Upstream MTPR @ VS = ±6 V Figure 28. Full Rate ADSL (DMT) Downstream MTPR @ VS = ±6 V Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 13 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com 7 Parameter Measurement Information 7.1 Test Circuits RG RF 50: + 50: Figure 29. Non-Inverting Amplifier 604: 604: - 50: 154: + 56.7: 154: Figure 30. CMRR RG 100: - PF + Figure 31. Voltage Noise RG = 1 Ω for f ≤ 100 kHz, RG = 20 Ω for f > 100 kHz 14 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 Test Circuits (continued) RG 100: - 1PF + 1k: Figure 32. Current Noise RG = 1 Ω for f ≤ 100 kHz, RG = 20 Ω for f > 100 kHz + + - VIN RF RG + RL RF VOUT - - + Figure 33. Multitone Power Ratio, RF = 500 Ω, RG = 174 Ω, RL = 437 Ω Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 15 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com 8 Detailed Description 8.1 Overview The LMH6622 is a dual high speed voltage operational amplifier specifically optimized for low noise. The LMH6622 operates from ±2.5 V to ±6 V in dual supply mode and from +5 V to +12 V in single supply configuration. 8.2 Functional Block Diagram RECEIVE PRE-AMP ADC ADC LMH6622 1:N HYBRID COUPLER LMH6643 TELEPHONE LINE LMH6672 DAC DAC BUFFER/FILTER LINE DRIVER Figure 34. xDSL Analog Front End 8.3 Feature Description • • • 4.5 V to 12 V supply range Large linear output current of 90 mA Excellent harmonic distortion of 90 dBc 8.4 Device Functional Modes • • 16 Single or dual supplies Traditional voltage feedback topology for maximum flexibility Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 9 Application and Implementation POWER SPECTRUM 9.1 DSL Receive Channel Applications UPSTREAM DOWNSTREAM POTS FREQUENCY 4.5kHz 30kHz 135kHz 160kHz 1.1MHz Figure 35. ADSL Signal Description The LMH6622 is a dual, wideband operational amplifier designed for use as a DSL line receiver. In the receive band of a Customer Premises Equipment (CPE) ADSL modem it is possible that as many as 255 Discrete MultiTone (DMT) QAM signals will be present, each with its own carrier frequency, modulation, and signal level. The ADSL standard requires a line referred noise power density of -140 dBm/Hz within the CPE receive band of 100 KHz to 1.1 MHz. The CPE driver output signal will leak into the receive path because of full duplex operation and the imperfections of the hybrid coupler circuit. The DSL analog front end must incorporate a receiver pre-amp which is both low noise and highly linear for ADSL-standard operation. The LMH6622 is designed for the twin performance parameters of low noise and high linearity. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 17 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com DSL Receive Channel Applications (continued) Applications ranging from +5 V to +12 V or ±2.5 V to ±6 V are fully supported by the LMH6622. In Figure 36, the LMH6622 is used as an inverting summing amplifier to provide both received pre-amp channel gain and driver output signal cancellation, that is, the function of a hybrid coupler. LMH6672 DAC + IN OUT +VA/2 V1 1/2RS + VT1 V2 -VA/2 IN OUT DAC - RF - 1:N 1/2RL + VTN - 1/2RS VS 1/2RL R1 R2 ADC + +VOUT + R+ LMH6622 R+ + -VOUT ADC - R1 RF R2 Figure 36. ADSL Receive Applications Circuit The two RS resistors are used to provide impedance matching through the 1:N transformer. RS = RL N 2 where • • RL is the impedance of the twisted pair line N is the turns ratio of the transformer (1) The resistors R2 and RF are used to set the receive gain of the pre-amp. The receive gain is selected to meet the ADC full-scale requirement of a DSL chipset. Resistor R1 and R2 along with RF are used to achieve cancellation of the output driver signal at the output of the receiver. Since the LMH6622 is configured as an inverting summing amplifier, VOUT is found to be, VOUT = -RF V1 R1 + V2 R2 (2) The expression for V1 and V2 can be found by using superposition principle. When VS = 0, V1 = 1 V 2 A and 1 V2 = - VA 4 (3) When VA = 0, 1 V1 = 0 and V2 = - 2 VT1 18 (4) Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 DSL Receive Channel Applications (continued) Therefore, 1 V1 = 2 VA 1 1 V2 = - VA - 2 VT1 4 and (5) And then, VOUT = -RF VA - 2R1 VA - 4R2 VT1 2R2 (6) Setting R1 = 2*R2 to cancel unwanted driver signal in the receive path, then we have VOUT = RF V 2R2 T1 (7) We can also find that, 1 VTN VS a n d VT1 2 1 N 1 VTN VS 2N (8) And then RF VOUT = 4NR VS 2 (9) In conclusion, the peak-to-peak voltage to the ADC would be, RF 2 VOUT = V 2NR2 S (10) 9.2 Receive Channel Noise Calculation The circuit of Figure 36 also has the characteristic that it cancels noise power from the drive channel. The noise gain of the receive pre-amp is found to be: An = 1 + RF R1 / R2 (11) Noise power at each of the output of LMH6622: 2 2 2 2 2 2 2 e o = A n [V n + i non-inv R+ + 4kT R+] + i inv R F + 4kT RF An where • • • • • • • Vn is the Input referred voltage noise in is the Input referred current noise inon-inv is the Input referred non-inverting current noise iinv is the Input referred inverting current noise k is the Boltzmann’s constant, K = 1.38 x 10−23 T is the Resistor temperature in k R+ is the source resistance at the non-inverting input to balance offset voltage, typically very small for this inverting summing applications (12) For a voltage feedback amplifier, iinv = inon-inv = in (13) Therefore, total output noise from the differential pre-amp is: 2 2 e TotalOutput = 2 e o (14) The factor '2 ' appears here because of differential output. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 19 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com 9.3 Differential Analog-to-Digital Driver LMH6622 + +VOUT/2 1:N x RC RIN RS RF 500: TO ADC 110: RF 500: -VOUT/2 VS + LMH6622 Figure 37. Circuit for Differential A/D Driver The LMH6622 is a low noise, low distortion high speed operational amplifier. The LMH6622 comes in either SOIC-8 or VSSOP-8 packages. Because two channels are available in each package the LMH6622 can be used as a high dynamic range differential amplifier for the purpose of driving a high speed analog-to-digital converter. Driving a 1 kΩ load, the differential amplifier of Figure 37 provides 20 dB gain, a flat frequency response up to 6 MHz, and harmonic distortion that is lower than 80 dBc. This circuit makes use of a transformer to convert a single-ended signal to a differential signal. The input resistor RIN is chosen by the following equation, RIN = 1 N 2 RS (15) The gain of this differential amplifier can be adjusted by RC and RF, AV = 2 RF RC (16) See Figure 38 and Figure 39 below for plots related to the discussion of Figure 37. 54n 22 52n VS = ±5.0V 50n AV = +9 48n RC = 110Ω 46n RF = 500Ω 44n RL = 1kΩ OUTPUT REFERED NOISE (V/ Hz) 24 20 18 GAIN (dB) 16 14 12 10 VS = ±5.0V 8.0 AV = +9 6.0 RC = 110Ω 4.0 RF = 500Ω 2.0 RL = 1kΩ 0.0 10k 100k 10M 1M FREQUENCY (Hz) 100 M 1G Figure 38. Frequency Response 20 42n 40n 38n 36n 34n 32n 30n 100 1k 1M 100k 10k FREQUENCY (Hz) 10M Figure 39. Total Output Referred Noise Density Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 9.4 Typical Application See Figure 40 for application circuit. LMH6672 DAC + IN OUT +VA/2 V1 1/2RS + VT1 V2 -VA/2 IN OUT DAC - RF - 1:N 1/2RL + VTN - 1/2RS VS 1/2RL R1 R2 ADC + +VOUT + R+ LMH6622 R+ + -VOUT ADC - R1 RF R2 Figure 40. ADSL Receive Applications Circuit 9.4.1 Design Requirements All normal precautions / considerations with Op Amps apply 9.4.2 Detailed Design Procedure • Use power supply decoupling capacitors close to supply pins • Beware of junction temperature rise at elevated ambient temperature and / or heavy output(s) load current especially at higher supply voltages • Ground plane near sensitive input pins can be removed to minimize parasitic capacitance 9.4.3 Application Curves See Figure 38 and Figure 39. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 21 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com 10 Power Supply Recommendations 10.1 Driving Capacitive Load Capacitive Loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed between the load and the output. In general, the bigger the isolation resistor, the more damped the pulse response becomes. For initial evaluation, a 50 Ω isolation resistor is recommended. 11 Layout 11.1 Layout Guidelines 11.1.1 Circuit Layout Considerations Texas Instruments suggests the copper patterns on the evaluation boards listed below as a guide for high frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case with all high-speed amplifiers, accepted-practice RF design technique on the PCB layout is mandatory. Generally, a good high frequency layout exhibits a separation of power supply and ground traces from the inverting input and output pins. Parasitic capacitances between these nodes and ground will cause frequency response peaking and possible circuit oscillations (see SNOA367, Application Note OA-15, for more information). High quality chip capacitors with values in the range of 1000 pF to 0.1 μF should be used for power supply bypassing. One terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a point that is as close as possible to each supply pin as allowed by the manufacturer's design rules. In addition, a tantalum capacitor with a value between 4.7 μF and 10 μF should be connected in parallel with the chip capacitor. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize inductance and microstrip line effect. Input and output termination resistors should be placed as close as possible to the input/output pins. Traces greater than 1 inch in length should be impedance matched to the corresponding load termination. Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained so as to minimize the imbalance of amplitude and phase of the differential signal. DEVICE PACKAGE EVALUATION BOARD P/N LMH6622MA SOIC-8 LMH730036 LMH6622MM VSSOP-8 LMH730123 Component value selection is another important parameter in working with high speed/high performance amplifiers. Choosing external resistors that are large in value compared to the value of other critical components will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path. Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low value resistors could load down nodes and will contribute to higher overall power dissipation and worse distortion. 22 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 11.2 Layout Examples 11.2.1 SOIC Layout Example Figure 41. LMH6622 Layout Example - SOIC Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 23 LMH6622 SNOS986E – DECEMBER 2001 – REVISED JULY 2014 www.ti.com Layout Examples (continued) 11.2.2 VSSOP Layout Example Figure 42. LMH6622 Layout Example - VSSOP 24 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 LMH6622 www.ti.com SNOS986E – DECEMBER 2001 – REVISED JULY 2014 12 Device and Documentation Support 12.1 Trademarks All trademarks are the property of their respective owners. 12.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMH6622 25 PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) LMH6622 MDC Package Type Package Pins Package Drawing Qty ACTIVE DIESALE Y 0 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) 374 Green (RoHS & no Sb/Br) Call TI Level-1-NA-UNLIM -40 to 85 Device Marking (4/5) LMH6622MA NRND SOIC D 8 TBD Call TI Call TI -40 to 85 LMH6622MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 22MA LMH6622MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66 22MA LMH6622MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 LMH6622MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A80A LMH6622MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A80A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Aug-2016 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Dec-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6622MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6622MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMH6622MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Dec-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6622MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6622MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LMH6622MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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