Cypress CY62148DV30 4-mbit (512k x 8) mobl static ram Datasheet


CY62148DV30
4-Mbit (512K x 8) MoBL Static RAM
Functional Description[1]
Features
■
Temperature Ranges
❐ Industrial: –40 °C to 85 °C
■
Very high speed: 55 ns
❐
Wide voltage range: 2.20 V – 3.60 V
■
Pin-compatible with CY62148CV25, CY62148CV30 and
CY62148CV33
■
Ultra low active power
❐
❐
Typical active current: 1.5 mA at f = 1 MHz
Typical active current: 8 mA at f = fmax(55-ns speed)
The CY62148DV30 is a high-performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can be put into standby mode reducing
power consumption when deselected (CE HIGH).The eight input
and output pins (I/O0 through I/O7) are placed in a
high-impedance state when:
■
Ultra low standby power
■
Deselected (CE HIGH)
■
Easy memory expansion with CE, and OE features
■
Outputs are disabled (OE HIGH)
■
Automatic power-down when deselected
■
When the write operation is active(CE LOW and WE LOW)
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■
Available in Pb-free 32-pin Small-outline integrated circuit
(SOIC package)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
Logic Block Diagram
I/O0
Data in Drivers
I/O1
512K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A13
A14
A15
A16
A17
A18
WE
OE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document Number : 38-05341 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Page 1 of 13
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CY62148DV30
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 6
Document Number : 38-05341 Rev. *F
Truth Table ........................................................................ 8
Ordering Information ........................................................ 9
Ordering Code Definition ............................................. 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
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CY62148DV30
Pin Configuration
32-pin SOIC Pinout
Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
4
32
31
30
29
5
6
28
27
7
8
9
10
11
12
26
25
1
2
3
13
14
15
16
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O 5
I/O4
I/O3
Product Portfolio
Power Dissipation
Product
Range
CY62148DV30LL Industrial
VCC Range (V)
Min
Typ[2]
Max
2.2
3.0
3.6
Speed
(ns)
55
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
1.5
3
8
10
2
8
Note
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number : 38-05341 Rev. *F
Page 3 of 13
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CY62148DV30
DC input voltage[3, 4].....................–0.3 V to VCC(max) + 0.3 V
Maximum Ratings
(Exceeding maximum ratings may impair the useful life of the
device. For user guidelines, not tested.)
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ............................................. 55 °C to +125 °C
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... > 2001V
(per MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
supply voltage to ground 
potential ........................................–0.3 V to VCC(max) + 0.3 V
Product
Range
VCC[5]
DC voltage applied to outputs
in High Z state[3, 4] ........................–0.3 V to VCC(max) + 0.3 V
Ambient
Temperature
CY62148DV30LL
Industrial
–40 °C to +85 °C
2.2 V to
3.6 V
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
voltage
Test Conditions
55 ns
Min
Typ[2]
Max
Unit
IOH = –0.1 mA
VCC = 2.20 V
2.0
–
–
V
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
Output LOW voltage IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
Input HIGH voltage VCC = 2.2 V to 2.7 V
1.8
–
VCC +
0.3V
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC +
0.3V
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
Input LOW voltage
IIX
Input leakage
current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage
current
GND < VO < VCC, output disabled
–1
–
+1
A
ICC
VCC operating
supply current
f = fmax = 1/tRC
8
10
mA
–
1.5
3
mA
ISB1
Automatic CE
Power-down 
current — CMOS
inputs
CE > VCC0.2 V,
VIN>VCC–0.2 V, VIN<0.2 V)
f = fmax (address and data only),
f = 0 (OE, and WE), VCC=3.60 V
–
2
8
A
ISB2
Automatic CE 
Power-down 
current — CMOS
inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
2
8
A
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA
CMOS levels
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max) = VCC+0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
Document Number : 38-05341 Rev. *F
Page 4 of 13
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CY62148DV30
Capacitance
Parameter[6]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
SOIC
Unit
55
C/W
22
C/W
Thermal Resistance
Parameter[6]
Description
Test Conditions
JA
Thermal resistance 
(Junction to ambient)
JC
Thermal resistance (Junction to
case)
Still air, soldered on a 3 x 4.5 inch,
four-layer printed circuit board
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
GND
R2
50 pF
90%
10%
90%
10%
Fall time: 1 V/ns
Rise Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V (2.2 V – 2.7 V)
3.0 V (2.7 V – 3.6 V)
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Min Typ[7] Max
Conditions
VDR
VCC for data retention
1.5
ICCDR
Data retention current
tCDR[6]
Chip deselect to data retention time
0
tR[8]
Operation recovery time
55
VCC = 1.5 V, CE > VCC 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
–
Unit
–
V
6
A
–
–
ns
–
–
ns
–
Data Retention Waveform
DATA RETENTION MODE
VCC
1.5 V
tCDR
VDR > 1.5 V
1.5 V
tR
CE
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C
8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min)  100 s.
Document Number : 38-05341 Rev. *F
Page 5 of 13
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CY62148DV30
Switching Characteristics (Over the Operating Range)
Parameter[9]
55 ns
Description
Min
Max
Unit
Read Cycle
tRC
Read cycle time
55
–
ns
tAA
Address to data valid
–
55
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
55
ns
tDOE
OE LOW to data valid
–
25
ns
tLZOE
OE LOW to Low Z[10]
5
–
ns
–
20
ns
10
–
ns
tHZOE
OE HIGH to High
tLZCE
CE LOW to Low
Z[10,11]
Z[10]
Z[10, 11]
tHZCE
CE HIGH to High
–
20
ns
tPU
CE LOW to power-up
0
–
ns
CE HIGH to power-up
–
55
ns
tWC
Write cycle time
55
–
ns
tSCE
CE LOW to write end
40
–
ns
tAW
Address set-up to write end
40
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address set-up to write start
0
–
ns
tPWE
WE pulse width
40
–
ns
tSD
Data set-up to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
–
20
ns
10
–
ns
tPD
Write
Cycle[12]
Z[10, 11]
tHZWE
WE LOW to High
tLZWE
WE HIGH to Low Z[10]
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes
9. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2,
input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
11. tHZOE, tHZCE, and tHZWE transitions are measured when the output enter a high impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
Document Number : 38-05341 Rev. *F
Page 6 of 13
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CY62148DV30
Switching Waveforms
(continued)
Figure 2. Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Figure 3. Write Cycle No. 1 (WE Controlled)[17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tSA
WE
tHA
tPWE
OE
tSD
DATA I/O
NOTE 19
tHD
DATAIN VALID
tHZOE
Notes
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE transition LOW.
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05341 Rev. *F
Page 7 of 13
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CY62148DV30
Switching Waveforms
(continued)
Figure 4. Write Cycle No. 2 (CE Controlled)[20, 21]
tWC
ADDRESS
tSCE
CE
tHA
tSA
tAW
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[21]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tSD
NOTE 22
DATA I/O
tHD
DATAIN VALID
tLZWE
tHZWE
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data out (I/O0-I/O7)
Read
Active (ICC)
L
H
H
High Z
Output disabled
Active (Icc)
L
L
X
Data in (I/O0-I/O7)
Write
Active (Icc)
Notes
20. Data I/O is high impedance if OE = VIH.
21. If CE goes HIGH simultaneously with WE HIGH, the output remains in high-impedance state.
22. During this period, the I/Os are in output state and input signals should not be applied.
Document Number : 38-05341 Rev. *F
Page 8 of 13
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CY62148DV30
Ordering Information
Speed
(ns)
55
Ordering Code
CY62148DV30LL-55SXI
Package
Diagram
Package Type
51-85081 32-pin SOIC (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts
Ordering Code Definition
CY 621 4
8
D V30 LL 55
SX
I
Temperature Grade: I = Industrial
Package Type: SX = 32 pin SOIC (Pb-free)
Speed Grade
LL = Low Power
Voltage Range = 3 V typical
D = Process Technology 130 nm
Buswidth = × 8
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number : 38-05341 Rev. *F
Page 9 of 13
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CY62148DV30
Package Diagrams
32-pin (450 MIL) Molded SOIC, 51-85081
51-85081 *C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective
holders.
Document Number : 38-05341 Rev. *F
Page 10 of 13
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CY62148DV30
Acronyms
Acronym
Description
CMOS
complementary metal oxide semiconductor
I/O
input/output
MoBL
more battery life
SOIC
small-outline integrated circuit
SRAM
static random access memory
Document Conventions
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
volts
µA
micro amperes
mA
milli amperes
pF
pico Farad
°C
degree Celsius
W
watts
Document Number : 38-05341 Rev. *F
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CY62148DV30
Document History Page
Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL Static RAM
Document Number: 38-05341
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
127480
06/17/03
HRT
Created new data sheet
*A
131041
01/23/04
CBD
Changed from Advance to Preliminary
*B
222180
See ECN
AJU
Changed from Preliminary to Final
Added 70 ns speed bin
Modified footnote #6 and #12
Removed MAX value for VDR on “Data Retention Characteristics” table
Modified input and output capacitance values
Added Pb-free ordering information
Removed 32-pin STSOP package
*C
498575
See ECN
NXR
Added Automotive-A Operating Range
Removed SOIC package from Product Offering
Updated Ordering Information Table
*D
729917
See ECN
VKN
Added SOIC package and its related information
Updated Ordering Information Table
*E
2896036
03/19/10
AJU
Removed inactive parts from Ordering Information.
Added Table of Contents.
Updated Packaging Information
Updated links in Sales, Solutions, and Legal Information.
*F
3166059
02/08/2011
RAME
Document Number : 38-05341 Rev. *F
Removed Automotive related info
Removed 70 ns speed bin related info
Remove TSOP and VFBGA package related info
Updated as per new template
Added Acronyms and Units of Measure table
Added Ordering Code Definitiondetails
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CY62148DV30
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 38-05341 Rev. *F
Revised February 8, 2011
Page 13 of 13
All products and company names mentioned in this document may be the trademarks of their respective holders.
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