Freescale MC9S08LH36CLH Advanced information Datasheet

Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MC9S08LH64
Rev. 4, 04/2010
An Energy Efficient Solution by Freescale
MC9S08LH64 Series
Covers: MC9S08LH64 and MC9S08LH36
• 8-Bit HCS08 Central Processor Unit (CPU)
– Up to 40 MHz CPU at 3.6 V to 2.1 V across temperature range
of –40 °C to 85 °C
– Up to 20 MHz at 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– HC08 instruction set with added BGND instruction
– Support for up to 32 interrupt/reset sources
• On-Chip Memory
– Dual array flash read/program/erase over full operating
voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and
flash contents
• Power-Saving Modes
– Two low-power stop modes
– Reduced-power wait mode
– Low-power run and wait modes allow peripherals to run while
voltage regulator is in standby
– Peripheral clock gating register can disable clocks to unused
modules, thereby reducing currents
– Very low-power external oscillator that can be used in stop2 or
stop3 modes to provide accurate clock source to time-of-day
(TOD) module
– 6 μs typical wakeup time from stop3 mode
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; crystal
or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz
to 16 MHz
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by
internal or external reference; precision trimming of internal
reference allows 0.2% resolution and 2% deviation over
temperature and voltage; supporting bus frequencies from
1 MHz to 20 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source or bus
clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode detection with reset; illegal address detection
with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
64-LQFP
Case 840F
80-LQFP
Case 917A
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus two more breakpoints in on-chip
debug module)
– On-chip in-circuit emulator (ICE) debug module containing
three comparators and nine trigger modes
• Peripherals
– LCD — Up to 8×36 or 4×40 LCD driver with internal charge
pump and option to provide an internally-regulated LCD
reference that can be trimmed for contrast control
– ADC —16-bit resolution; with a dedicated differential ADC
input, and 8 single-ended ADC inputs; up to 2.5 μs conversion
time; hardware averaging; calibration registers, automatic
compare function; temperature sensor; operation in stop3;
fully functional from 3.6 V to 1.8 V
– IIC — Inter-integrated circuit bus module to operate at up to
100 kbps with maximum bus loading; multi-master operation;
programmable slave address; interrupt-driven byte-by-byte
data transfer; broadcast mode; 10-bit addressing
– ACMP — Analog comparator with selectable interrupt on
rising, falling, or either edge of comparator output; compare
option to fixed internal reference voltage; outputs can be
optionally routed to TPM module; operation in stop3
– SCIx — Two full-duplex non-return to zero (NRZ) modules
(SCI1 and SCI2); LIN master extended break generation; LIN
slave extended break detection; wakeup on active edge
– SPI — Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave mode;
MSB-first or LSB-first shifting
– TPMx — Two 2-channel (TPM1 and TPM2); selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel
– TOD — (Time-of-day) 8-bit, quarter second counter with
match register; external clock source for precise time base,
time-of-day, calendar, or task scheduling functions
– VREFx — Trimmable via an 8-bit register in 0.5 mV steps;
automatically loaded with room temperature value upon reset;
can be enabled to operate in stop3 mode; trim register is not
available in stop modes
• Input/Output
– Dedicated accurate voltage reference output pin, 1.2 V output
(VREFOx); trimmable with 0.5 mV resolution
– Up to 39 GPIOs, two output-only pins
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins
• Package Options
– 14mm × 14mm 80-pin LQFP, 10 mm × 10 mm 64-pin LQFP
Contents
1
2
3
•
Devices in the MC9S08LH64 Series . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Parameter Classification. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . 11
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7 Supply Current Characteristics. . . . . . . . . . . . . . . . . . . 23
3.8 External Oscillator (XOSCVLP) Characteristics . . . . . . 25
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . . 26
3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4
3.10.2 TPM Module Timing. . . . . . . . . . . . . . . . . . . . . .29
3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . .33
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.13 VREF Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.14 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.15 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.16 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
3.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .42
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .42
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .43
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
1
10/2007
Intial Release of the electrical characteristics in the Reference Manual.
2
7/2008
Initial Release after product redefinition and restructuring of information into a separate Data
Sheet and Reference Manual.
3
1/2009
Refreshed the draft to include the new VREF module and the latest revisions.
4
4/8/2010
Completed RIDD in the Table 9; updated ERREFSTEN in the Table 10; changed all VDDAD to
VDDA, VSSAD to VSSA; updated the min. of VREFH;
Added 64-pin LQFP package information for LH36 MCU; Updated V Room Temp in the
Table 20. Updated S2IDD at VDD = 2 and Temp at –40 to 25 °C
Added 64-pin LQFP package for LH36.
Updated ADC data in the 3.12/33
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
—MC9S08LH64RM
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
1
Devices in the MC9S08LH64 Series
Table 1 summarizes the feature set available in the MC9S08LH64 Series of MCUs.
Table 1. MC9S08LH64 Series Features by MCU and Package
Feature
Package
1
2
MC9S08LH64
80-pin
LQFP
MC9S08LH36
64-pin
LQFP
80-pin
LQFP
64-pin
LQFP
FLASH
64 KB
(32,768 and 32,768 Arrays)
36 KB
(24,576 and 12,288 Arrays)
RAM
4000
4000
ACMP
yes
yes
ADC
Single-ended
Channels
8-ch
8-ch
8-ch
8-ch
ADC Differential
Channels1
1
0
1
0
IIC
yes
yes
IRQ
yes
yes
KBI
8
8
SCI1
yes
yes
SCI2
yes
yes
SPI
yes
yes
TPM1
2-ch
2-ch
TPM2
2-ch
2-ch
TOD
yes
yes
LCD
8×36
4×40
8×24
4×28
8×36
4×40
8×24
4×28
VREFO1
yes
no
yes
no
VREFO2
no
yes
no
yes
I/O pins2
39
37
39
37
Each differential channel consists of two pins (DADPx and DADMx).
The 39 I/O pins include two output-only pins and 18 LCD GPIO.
The block diagram in Figure 1 shows the structure of the MC9S08LH64 Series MCU.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
3
HCS08 CORE
ON-CHIP ICE
DEBUG MODULE (DBG)
INT
BKGD
BKP
PTA7/KBIP7/ADP11/ACMP–
PTA6/KBIP6/ADP10/ACMP+
PORT A
CPU
TIME OF DAY MODULE
(TOD)
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/MOSI/SCL/KBIP3/ADP7
PTA2/MISO/SDA/KBIP2/ADP6
HCS08 SYSTEM CONTROL
8-BIT KEYBOARD
INTERRUPT (KBI)
PTA0/SS/KBIP0/ADP4
BKGD/MS
RESET
COP
SERIAL PERIPHERAL
INTERFACE (SPI)
IRQ
IIC MODULE (IIC)
USER FLASH A
(LH64 = 32,768 BYTES)
(LH36 = 24,576 BYTES)
(TPM2)
USER RAM
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
4K BYTES
INTERNAL CLOCK
SOURCE (ICS)
VREFO1
VREFO2
LCD[43:0]
TPM1CH1
PTC7/IRQ/TCLK
PTC6/ACMPO//BKGD/MS ◊
PTC5/TPM2CH1
PTC4/TPM2CH0
TCLK
TxD1
RxD1
PTC3/TPM1CH1
PTC2/TPM1CH0
TxD2
RxD2
PTC1/TxD1
•
DADM0
•
PORT D
DADP0
VOLTAGE
REGULATOR
ANALOG COMPARATOR
(ACMP)
DADP0
•
DADM0
•
PTD[7:0]/LCD[7:0]
ACMP–
ACMP+
ACMPO
PTE[7:0]/LCD[13:20]
NOTES
• Pins not available on 64-pin packages. LCD[8:12] and LCD[31:37] are not
VLL2
VCAP2
PTB1/XTAL
PTB0/EXTAL
ADP[11:4]
VLL1
VLL3
TCLK
∞
PTC0/RxD1
VLCD
VCAP1
PTB2/RESET
TPM2CH1
EXTAL
16-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VREF1
VREF2
PTB5/MOSI/SCL
PTB4/MISO/SDA
PORT E
•
♦
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
XTAL
LOW-POWER OSCILLATOR
VSS
SDA
TPM1CH0
2-CHANNEL TIMER/PWM
(TPM1)
VDD
MOSI
TPM2CH0
2-CHANNEL TIMER/PWM
USER FLASH B
(LH64 = 32,768 BYTES)
(LH36 = 12,288 BYTES)
♦
♦
PTB7/TxD2/SS
PTB6/RxD2/SPSCK
SCL
LVD
VDDA
VSSA
VREFH
VREFL
SS
SPSCK
MISO
PORT C
IRQ
PTA1/SPSCK/KBIP1/ADP5
PORT B
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
KBI[7:0]
LIQUID CRYSTAL
DISPLAY
LCD
available on the 64-pin package.
♦ VREFH and VREFL are internally connected to VDDA and VSSA for the 64-pin
package. VREFO2 is only available on the 64-pin package.
∞ When PTB2 is configured as RESET, the pin becomes bi-directional with
output being an open-drain drive.
◊ When PTC6 is configured as BKGD, the pin becomes bi-directional.
Figure 1. MC9S08LH64 Series Block Diagram
MC9S08LH64 Series MCU Data Sheet, Rev. 4
4
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
2
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-Pin LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LCD38
LCD39
LCD40
LCD41
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
PTC3/TPM1CH1
PTC2/TPM1CH0
PTA6/KBIP6/ADP10/ACMP+
PTA7/KBIP7/ADP11/ACMP–
VSSA/VREFL
VDDA/VREFH
PTB0/EXTAL
PTB1/XTAL
VDD
VSS
PTB2/RESET
VREFO2
PTB4/MISO/SDA
PTB5/MOSI/SCL
PTB6/RxD2/SPSCK
PTB7/TxD2/SS
PTC0/RxD1
PTC1/TxD1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PTE1/LCD14
PTE0/LCD13
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
VCAP2
VLL1
VLL2
VLL3
VLCD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTE2/LCD15
PTE3/LCD16
PTE4/LCD17
PTE5/LCD18
PTE6/LCD19
PTE7/LCD20
LCD21
LCD22
LCD23
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
LCD30
This section shows the pin assignments for the This section shows the pin assignments for the
MC9S08LH64 Series devices.
Figure 2. 64-Pin LQFP
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
5
PTE1/LCD14
PTE2/LCD15
PTE3/LCD16
PTE4/LCD17
PTE5/LCD18
PTE6/LCD19
PTE7/LCD20
LCD21
LCD22
LCD23
LCD24
LCD25
LCD26
LCD27
LCD28
LCD29
LCD30
LCD31
LCD32
LCD33
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
LCD34
LCD35
LCD36
LCD37
LCD38
LCD39
LCD40
LCD41
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTC7/IRQ/TCLK
PTC6/ACMPO/BKGD/MS
PTC5/TPM2CH1
PTC4/TPM2CH0
PTC3/TPM1CH1
PTC2/TPM1CH0
PTB0/EXTAL
PTB1/XTAL
VDD
VSS
PTB2/RESET
PTB4/MISO/SDA
PTB5/MOSI/SCL
PTB6/RxD2/SPSCK
PTB7/TxD2/SS
PTC0/RxD1
PTC1/TxD1
DADP0
DADM0
VREFO1
VREFH
VDDA
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80-Pin
LQFP
PTA6/KBIP6/ADP10/ACMP+
PTA7/KBIP7/ADP11/ACMP–
VSSA
VREFL
PTE0/LCD13
LCD12
LCD11
LCD10
LCD9
LCD8
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTD1/LCD1
PTD0/LCD0
VCAP1
VCAP2
VLL1
VLL2
VLL3
VLCD
Figure 3. 80-Pin LQFP
Table 2. Pin Availability by Package Pin-Count
<-- Lowest
80
64
Port Pin
Alt 1
1
2
PTE0
LCD13
2
LCD12
3
LCD11
4
LCD10
5
LCD9
6
LCD8
7
3
PTD7
LCD7
8
4
PTD6
LCD6
Priority
--> Highest
Alt 2
Alt3
Alt4
MC9S08LH64 Series MCU Data Sheet, Rev. 4
6
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest
80
64
Port Pin
Alt 1
Priority
--> Highest
Alt 2
Alt3
9
5
PTD5
LCD5
10
6
PTD4
LCD4
11
7
PTD3
LCD3
12
8
PTD2
LCD2
13
9
PTD1
LCD1
14
10
PTD0
LCD0
15
11
VCAP1
16
12
VCAP2
17
13
VLL1
18
14
VLL2
19
15
VLL3
20
16
VLCD
21
17
PTA6
KBIP6
ADP10
ACMP+
22
18
PTA7
KBIP7
ADP11
ACMP–
23
24
19
Alt4
VSSA
VREFL
DADP0
25
26
DADM0
27
VREFO1
28
20
29
VREFH
VDDA
30
21
PTB0
EXTAL
31
22
PTB1
XTAL
32
23
VDD
33
24
VSS
34
25
PTB2
26
VREFO2
35
27
PTB4
MISO
SDA
36
28
PTB5
MOSI
SCL
37
29
PTB6
RxD2
SPSCK
38
30
PTB7
TxD2
SS
39
31
PTC0
RxD1
40
32
PTC1
TxD1
41
33
PTC2
TPM1CH0
42
34
PTC3
TPM1CH1
43
35
PTC4
TPM2CH0
44
36
PTC5
TPM2CH1
45
37
PTC6
ACMPO
RESET
BKGD
MS
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
7
Table 2. Pin Availability by Package Pin-Count (continued)
<-- Lowest
Priority
--> Highest
80
64
Port Pin
Alt 1
Alt 2
46
38
PTC7
IRQ
TCLK
47
39
PTA0
KBIP0
SS
ADP4
48
40
PTA1
KBIP1
SPSCK
ADP5
49
41
PTA2
KBIP2
SDA
MISO
ADP6
50
42
PTA3
KBIP3
SCL
MOSI
ADP7
51
43
PTA4
KBIP4
ADP8
LCD43
52
44
PTA5
KBIP5
ADP9
LCD42
53
45
LCD41
54
46
LCD40
55
47
LCD39
56
48
LCD38
57
LCD37
58
LCD36
59
LCD35
60
LCD34
61
LCD33
62
LCD32
Alt3
Alt4
LCD31
63
64
49
LCD30
65
50
LCD29
66
51
LCD28
67
52
LCD27
68
53
LCD26
69
54
LCD25
70
55
LCD24
71
56
LCD23
72
57
LCD22
73
58
LCD21
74
59
PTE7
LCD20
75
60
PTE6
LCD19
76
61
PTE5
LCD18
77
62
PTE4
LCD17
78
63
PTE3
LCD16
79
64
PTE2
LCD15
80
1
PTE1
LCD14
MC9S08LH64 Series MCU Data Sheet, Rev. 4
8
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Introduction
3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08LH64 Series of microcontrollers
available at the time of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding, the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
Table 3. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pullup resistor associated with the pin is enabled.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
9
Thermal Characteristics
Table 4. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +3.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the
MCU design. To take PI/O into account in power calculations, determine the difference between actual pin
voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high
pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 5. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range
(packaged)
TA
TL to TH
–40 to 85
°C
Maximum junction temperature
TJ
95
°C
Thermal resistance
Single-layer board
80-pin LQFP
64-pin LQFP
θJA
55
73
°C/W
Thermal resistance
Four-layer board
80-pin LQFP
64-pin LQFP
θJA
42
54
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
MC9S08LH64 Series MCU Data Sheet, Rev. 4
10
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ESD Protection and Latch-Up Immunity
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification, ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless instructed otherwise in the device
specification.
Table 6. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
R1
1500
W
C
100
pF
—
3
Series resistance
R1
0
W
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
Series resistance
Human
Storage capacitance
Body Model
Number of pulses per pin
Charge
Device
Model
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
11
DC Characteristics
Table 6. ESD and Latch-up Test Conditions (continued)
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
Latch-up
Table 7. ESD and Latch-Up Protection Characteristics
Rating1
No.
1
3.6
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Charge device model (CDM)
VCDM
±500
—
V
3
Latch-up current at TA = 85°C
ILAT
±100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 8. DC Characteristics
Num C
1
Characteristic
Output high
P voltage
Output high
P voltage
C
D
Output high
current
C
5
Output low
P voltage
C
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]2,
high-drive strength
VOH
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
C
4
Min
Typ1
1.8
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7]2,
low-drive strength
C
3
Condition
Operating Voltage
C
2
Symbol
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
Max total IOH for all ports
VOH
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
high-drive strength
VOL
Unit
3.6
V
VDD >1.8 V
ILoad = –0.6 mA
VDD – 0.5
—
—
VDD > 2.7 V
ILoad = –10 mA
VDD – 0.5
—
—
VDD > 1.8 V
ILoad = –3 mA
VDD – 0.5
—
—
VDD > 1.8 V
ILoad = –0.5 mA
VDD – 0.5
—
—
VDD > 2.7 V
ILoad = –2.5 mA
VDD – 0.5
—
—
VDD > 1.8 V
ILoad = –1 mA
VDD – 0.5
—
—
—
—
100
VDD >1.8 V
ILoad = 0.6 mA
—
—
0.5
VDD > 2.7 V
ILoad = 10 mA
—
—
0.5
VDD > 1.8 V
ILoad = 3 mA
—
—
0.5
IOHT
PTA[0:3], PTA[6:7],
PTB[0:7], PTC[0:7],
low-drive strength
Max
V
V
mA
V
MC9S08LH64 Series MCU Data Sheet, Rev. 4
12
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Table 8. DC Characteristics (continued)
Num C
Characteristic
PTA[4:5], PTD[0:7],
PTE[0:7],
low-drive strength
C
6
Symbol
Output low
P voltage
PTA[4:5], PTD[0:7],
PTE[0:7],
high-drive strength
C
Output low
current
7
D
8
P Input high
C voltage
9
P Input low
C voltage
10
C
11
Input
P leakage
current
12
Hi-Z
(off-state)
P
leakage
current
13
Total
P leakage
current3
14
Input
hysteresis
Max total IOL for all ports
all digital inputs
VOL
Condition
Min
Typ1
Max
VDD > 1.8 V
ILoad = 0.5 mA
—
—
0.5
VDD > 2.7 V
ILoad = 3 mA
—
—
0.5
VDD > 1.8 V
ILoad = 1 mA
—
—
0.5
—
—
100
VDD > 2.7 V
0.70 x VDD
—
—
IOLT
VIH
all digital inputs
VIL
all digital inputs
Vhys
Unit
V
mA
VDD > 1.8 V
0.85 x VDD
—
—
VDD > 2.7 V
—
—
0.35 x VDD
VDD > 1.8 V
—
—
0.30 x VDD
0.06 x VDD
—
—
mV
V
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
0.025
1
μA
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.025
1
μA
Total leakage current for all
pins
|IInT|
VIn = VDD or VSS
—
—
3
μA
Pullup,
P Pulldown
resistors
all non-LCD pins when
enabled
RPU,
RPD
17.5
—
52.5
kΩ
15
Pullup,
P Pulldown
resistors
LCD/GPIO pins when
enabled
RPU,
RPD
35
—
77
kΩ
–0.2
—
0.2
mA
16
DC injection Single pin limit
D current 4, 5, Total MCU limit, includes
6
sum of all stressed pins
–5
—
5
mA
17
C Input Capacitance, all pins
18
C RAM retention voltage
7
IIC
VIN < VSS, VIN > VDD
CIn
—
—
8
pF
VRAM
—
0.6
1.0
V
19
C POR re-arm voltage
VPOR
0.9
1.4
2.0
V
20
D POR re-arm time
tPOR
10
—
—
μs
21
P Low-voltage detection threshold
VLVD
VDD falling
VDD rising
1.80
1.88
1.84
1.92
1.88
1.96
V
22
P Low-voltage warning threshold
VLVW
VDD falling
VDD rising
2.08
2.14
2.2
V
23
P
Vhys
—
80
—
mV
24
P Bandgap Voltage Reference8
VBG
1.15
1.17
1.18
V
Low-voltage inhibit reset/recover
hysteresis
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
13
DC Characteristics
1
2
3
4
5
6
7
8
Typical values are measured at 25°C. Characterized, not tested
All I/O pins except for LCD pins in Open Drain mode.
Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but
characterization data shows that individual pin leakage current maximums are less than 250 nA.
All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
POR will occur below the minimum voltage.
Factory trimmed at VDD = 3.0 V, Temp = 25 °C
Figure 4. Non LCD pins I/O Pullup Typical Resistor Values
MC9S08LH64 Series MCU Data Sheet, Rev. 4
14
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 5. Typical Low-Side Driver (Sink) Characteristics (Non LCD Pins) — Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
15
DC Characteristics
Figure 6. Typical Low-Side Driver (Sink) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
16
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 7. Typical High-Side (Source) Characteristics (Non LCD Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
17
DC Characteristics
Figure 8. Typical High-Side (Source) Characteristics(Non LCD Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
18
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 9. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
19
DC Characteristics
Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
20
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
DC Characteristics
Figure 11. Typical High-Side (Source) Characteristics (LCD/GPIO Pins)— Low Drive (PTxDSn = 0)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
21
DC Characteristics
Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — High Drive (PTxDSn = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
22
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Supply Current Characteristics
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 9. Supply Current Characteristics
Num
C
Parameter
T
Typ1
Max
Run supply current
FEI mode, all modules on
13.75
17.9
7
—
1 MHz
2
—
20 MHz
8.9
—
5.5
—
—
RIDD
8 MHz
T
T
2
T
Run supply current
FEI mode, all modules off
RIDD
8 MHz
3
1 MHz
0.9
T
32 kHz
FBILP
185
T
T
Run supply current
LPS=0, all modules off
RIDD
Run supply current
LPS=1, all modules off, running from
Flash
4
T
T
T
Run supply current
LPS=1, all modules off, running from
RAM
Wait mode supply current
FEI mode, all modules off
16 kHz
FBELP
P
3
16 kHz
FBELP
RIDD
3
7.3
20 MHz
WIDD
8 MHz
Stop2 mode supply current
S2IDD
C
n/a
C
2
C
C
7
Stop3 mode supply current
No clocks active
P
C
3
S3IDD
C
mA
–40 to 85
mA
–40 to 85
μA
–-40 to 85
—
—
—
—
—
0 to 70
μA
—
–40 to 85
0 to 70
–40 to 85
2
—
0.73
—
0.4
1.3
–40 to 25
4
6
70
8.5
13
0.35
1.0
3.9
5
70
7.7
10
85
0.65
1.8
–40 to 25
5.7
8.0
70
12.2
20
0.6
1.5
5
6.8
70
11.5
14
85
2
C
1
n/a
Temp
(°C)
6
3
P
Unit
4.57
3
1 MHz
C
P
115
21.9
T
6
3
T
3
5
VDD
(V)
20 MHz
T
1
Bus
Freq
Symbol
mA
μA
μA
–40 to 85
85
–40 to 25
85
–40 to 25
Typical values are measured at 25 °C. Characterized, not tested
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
23
Supply Current Characteristics
Table 10. Stop Mode Adders
Temperature (°C)
Num
Parameter
1
T
LPO
2
T
ERREFSTEN
Condition
T
IREFSTEN
4
T
TOD
5
T
LVD1
25
70
85
100
100
150
175
nA
750
750
800
850
nA
63
70
77
81
μA
Does not include clock source current
50
50
75
100
nA
LVDSE = 1
110
110
112
115
μA
RANGE = HGO = 0
1
Units
–40
1
3
6
T
ACMP
Not using the bandgap (BGBE = 0)
12
12
20
23
μA
7
T
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap (BGBE = 0)
95
95
101
120
μA
LCD
VIREG enabled for Contrast control, 1/8
Duty cycle, 8x24 configuration for
driving 192 segments, 32 Hz frame rate,
No LCD glass connected.
1
1
6
13
μA
8
1
C
T
Not available in stop2 mode.
Figure 13. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ACMP and ADC off, All Other Modules Enabled)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
24
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
External Oscillator (XOSCVLP) Characteristics
3.8
External Oscillator (XOSCVLP) Characteristics
Reference Figure 14 and Figure 15 for crystal or resonator circuits.
Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85°C Ambient)
Num
1
2
C
Characteristic
Load capacitors
Low range (RANGE=0), low power (HGO=0)
D
Other oscillator settings
3
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
6
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
5
Symbol
Crystal start-up time 4
Low range, low power
Low range, high gain
C
High range, low power
High range, high gain
D
RF
RS
t
t
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
FBE or FBELP mode
See Note 2
See Note 3
C1,C2
CSTL
CSTH
fextal
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
ms
0.03125
0
—
—
20
20
MHz
MHz
MΩ
kΩ
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0.
3 See crystal or resonator manufacturer’s recommendation.
4 Proper PC board layout procedures must be followed to achieve specifications.
2
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
25
Internal Clock Source (ICS) Characteristics
XOSCVLP
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSCVLP
EXTAL
XTAL
Crystal or Resonator
Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power
3.9
Internal Clock Source (ICS) Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
1
C Average internal reference frequency — untrimmed
fint_ut
25
32.7
41.66
kHz
2
P
Average internal reference frequency — user-trimmed
fint_t
31.25
—
39.06
kHz
3
P
Average internal reference frequency — factory-trimmed
fint_t
—
32.7
—
kHz
4
T
Internal reference start-up time
tIRST
—
60
100
μs
12.8
16.8
21.33
25.6
33.6
42.67
16
—
20
32
—
40
P
5
6
Low range (DFR = 00)
DCO output frequency
C range — untrimmed
Mid range (DFR = 01)
P
Low range (DFR = 00)
P
DCO output frequency
range — trimmed
Mid range (DFR = 01)
fdco_ut
fdco_t
MHz
MHz
7
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δfdco_res_t
—
±0.1
±0.2
%fdco
8
C
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δfdco_res_t
—
±0.2
±0.4
%fdco
MC9S08LH64 Series MCU Data Sheet, Rev. 4
26
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
AC Characteristics
Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Symbol
Min
Typ1
Max
Unit
Total deviation of trimmed DCO output frequency over
voltage and temperature
Δfdco_t
—
+0.5
–1.0
±2
%fdco
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0 °C to 70 °C
Δfdco_t
—
±0.5
±1
%fdco
tAcquire
—
—
1
ms
CJitter
—
0.02
0.2
%fdco
Num
C
Characteristic
9
C
10
C
11
C FLL acquisition time2
12
C
Long term jitter of DCO output clock (averaged over 2-ms
interval)3
1
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
2
Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V)
3.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
27
AC Characteristics
3.10.1
Control Timing
Table 13. Control Timing
Num
C
1
D
2
D
1
3
4
5
6
Min
Typ1
Max
Unit
Bus frequency (tcyc = 1/fBus)
VDD ≤ 2.1V
VDD > 2.1V
fBus
dc
dc
—
—
10
20
MHz
Internal low power oscillator period
tLPO
700
—
1300
μs
textrst
100
—
—
ns
width2
3
D
External reset pulse
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 × tcyc
—
—
—
—
ns
—
—
16
23
—
—
—
—
5
9
—
—
9
2
Symbol
Rating
C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
ns
ns
Typical values are based on characterization data at VDD = 3.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 85 °C.
Except for LCD pins in Open Drain mode.
textrst
RESET PIN
Figure 17. Reset Timing
MC9S08LH64 Series MCU Data Sheet, Rev. 4
28
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
AC Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 18. IRQ/KBIPx Timing
3.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 14. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus/4
Hz
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
29
AC Characteristics
3.10.3
SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No.
C
Function
Symbol
Min
Max
Unit
—
D
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
1
D
SPSCK period
Master
Slave
tSPSCK
2
4
2048
—
tcyc
tcyc
2
D
Enable lead time
Master
Slave
tLead
1/2
1
—
—
tSPSCK
tcyc
3
D
Enable lag time
Master
Slave
tLag
1/2
1
—
—
tSPSCK
tcyc
4
D
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
5
D
Data setup time (inputs)
Master
Slave
tSU
15
15
—
—
ns
ns
6
D
Data hold time (inputs)
Master
Slave
tHI
0
25
—
—
ns
ns
7
D
Slave access time
ta
—
1
tcyc
8
D
Slave MISO disable time
tdis
—
1
tcyc
9
D
Data valid (after SPSCK edge)
Master
Slave
tv
—
—
25
25
ns
ns
10
D
Data hold time (outputs)
Master
Slave
tHO
0
0
—
—
ns
ns
11
D
Rise time
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
12
D
Fall time
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
MC9S08LH64 Series MCU Data Sheet, Rev. 4
30
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
AC Characteristics
SS1
(OUTPUT)
1
2
SPSCK
(CPOL = 0)
(OUTPUT)
11
3
4
4
12
SPSCK
(CPOL = 1)
(OUTPUT)
5
MISO
(INPUT)
6
MS BIN2
BIT 6 . . . 1
9
LSB IN
9
MOSI
(OUTPUT)
10
BIT 6 . . . 1
MSB OUT2
LSB OUT
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 21. SPI Master Timing (CPHA = 0)
SS1
(OUTPUT)
1
2
12
11
11
12
3
SPSCK
(CPOL = 0)
(OUTPUT)
4
SPSCK
(CPOL = 1)
(OUTPUT)
4
5
MISO
(INPUT)
6
MSB IN2
9
MOSI
(OUTPUT) PORT DATA
BIT 6 . . . 1
LSB IN
10
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 22. SPI Master Timing (CPHA =1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
31
AC Characteristics
SS
(INPUT)
1
12
11
11
12
3
SPSCK
(CPOL = 0)
(INPUT)
2
4
4
SPSCK
(CPOL = 1)
(INPUT)
8
7
MISO
(OUTPUT)
9
SLAVE LSB OUT
SEE
NOTE 1
6
5
MOSI
(INPUT)
BIT 6 . . . 1
MSB OUT
SLAVE
10
10
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received.
Figure 23. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SPSCK
(CPOL = 0)
(INPUT)
4
SPSCK
(CPOL = 1)
(INPUT)
4
9
MISO
(OUTPUT)
SEE
NOTE 1
7
MOSI
(INPUT)
12
11
11
12
10
SLAVE
MSB OUT
‘c
BIT 6 . . . 1
c
SLAVE LSB OUT
6
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 24. SPI Slave Timing (CPHA = 1)
MC9S08LH64 Series MCU Data Sheet, Rev. 4
32
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Analog Comparator (ACMP) Electricals
3.11
Analog Comparator (ACMP) Electricals
Table 16. Analog Comparator Electrical Specifications
C
Characteristic
Symbol
Min
Typical
Max
Unit
VDD
1.8
—
3.6
V
D
Supply voltage
P
Supply current (active)
IDDAC
—
20
35
μA
D
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
P
Analog input offset voltage
VAIO
20
40
mV
C
Analog comparator hysteresis
VH
3.0
9.0
15.0
mV
P
Analog input leakage current
IALKG
—
—
1.0
μA
C
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
3.12
ADC Characteristics
Table 17. 16-bit ADC Operating Conditions
Num
Charact
eristic
1
Conditions
Absolute
Symb
Min
Typ1
Max
Unit
VDDA
1.8
—
3.6
V
ΔVDDA
–100
0
100
mV
ΔVSSA
–100
0
100
mV
Supply
voltage
Delta to VDD (VDD–VDDA)2
3
Ground
voltage
Delta to VSS (VSS–VSSA)2
4
Ref
Voltage
High
VREFH
1.15
VDDA
VDDA
V
5
Ref
Voltage
Low
VREFL
VSSA
VSSA
VSSA
V
6
Input
Voltage
VADIN
VREFL
—
VREFH
V
7
Input
Capacit
ance
CADIN
—
8
4
10
5
pF
8
Input
Resista
nce
RADIN
—
2
5
kΩ
2
16-bit modes
8/10/12-bit modes
Comment
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
33
ADC Characteristics
Table 17. 16-bit ADC Operating Conditions
Charact
eristic
Min
Typ1
Max
9
16 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
0.5
1
2
10
13/12 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
1
2
5
Num
Analog
Source
Resista
nce
Conditions
Symb
RAS
11
11/10 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
2
5
10
12
9/8 bit modes
fADCK > 8MHz
fADCK < 8MHz
—
—
—
—
5
10
1.0
—
8
1.0
—
5
1.0
—
2.5
13
14
15
ADC
Convers
ion
Clock
Freq.
ADLPC = 0, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 1, ADHSC = 0
fADCK
Unit
Comment
External to MCU
kΩ
Assumes
ADLSMP=0
MHz
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
1
MC9S08LH64 Series MCU Data Sheet, Rev. 4
34
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ADC Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
For Differential Mode, this figure
applies to both inputs
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 25. ADC Input Impedance Equivalency Diagram
Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz)
Conditions1
Characteristic
Supply Current
C
Symb
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
T
IDDA
ADLPC=0, ADHSC=1
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
C
P
IDDA
fADACK
ADLPC = 0, ADHSC = 1
Sample Time
See reference manual for sample times
Conversion
Time
See reference manual for conversion times
Min
Typ2
Max
—
215
—
—
470
—
—
610
—
—
0.01
—
—
2.4
—
—
5.2
—
—
6.2
—
Unit
Comment
μA
ADLSMP = 0
ADCO = 1
μA
MHz
tADACK =
1/fADACK
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
35
ADC Characteristics
Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz)
Characteristic
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+48/-40
+56/-28
LSB3
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.5
±1.75
±3.0
±3.5
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.7
±0.8
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
16-bit differential mode
16-bit single-ended mode
T
—
—
±2.5
±2.5
+5/-3
+5/-3
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±6.0
±10.0
±16.0
±20.0
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±2.5
±2.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.3
±0.3
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±4.0
±4.0
+32/-24
+24/-16
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.5
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
DNL
INL
EZS
LSB2
LSB2
LSB2
VADIN = VSSA
MC9S08LH64 Series MCU Data Sheet, Rev. 4
36
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ADC Characteristics
Table 18. 16-bit ADC Characteristics full operating range(VREFH = VDDA > 1.8, VREFL = VSSA, FADCK < 8MHz)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+10/0
+14/0
+42/-2
+46/-2
LSB2
VADIN = VDDA
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±3.5
±3.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
Quantization
Error
16 bit modes
D
—
-1 to 0
—
—
—
±0.5
Effective
Number of Bits
16 bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
C
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
16 bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
D
—
—
—
—
—
13.2
12.8
12.6
12.3
11.5
—
—
—
—
—
Characteristic
Full-Scale
Error
EQ
<13 bit modes
ENOB
Signal to Noise
plus Distortion
See ENOB
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
Input Leakage
Error
all modes
D
EIL
Temp Sensor
Slope
-40°C– 25°C
C
m
Temp Sensor
Voltage
25°C
Spurious Free
Dynamic
Range
SINAD
Bits
SINAD = 6.02 ⋅ ENOB + 1.76
—
-91.5
-74.3
—
-85.5
—
75.0
92.2
—
—
86.2
—
SFDR
VTEMP25
IIn * RAS
—
1.646
—
—
1.769
—
—
701.2
—
Fin =
Fsample/100
dB
THD
25°C– 125°C
C
LSB2
dB
Fin =
Fsample/100
dB
Fin =
Fsample/100
mV
IIn = leakage
current
(refer to DC
characteristics)
mV/°C
mV
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
37
ADC Characteristics
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
Typical values assume VDDA = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
3
1 LSB = (VREFH - VREFL)/2N
2
Table 19. 16-bit ADC Characteristics(VREFH = VDDA > 2.7V, VREFL = VSSA, FADCK < 4MHz, ADHSC=1)
Characteristic
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+24/-24
+32/-20
LSB3
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.5
±1.75
±2.0
±2.5
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.7
±0.8
±1.0
±1.25
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
16-bit differential mode
16-bit single-ended mode
T
—
—
±2.5
±2.5
±3
±3
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±6.0
±10.0
±12.0
±16.0
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.3
±0.3
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±4.0
±4.0
+16/0
+16/-8
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
DNL
INL
EZS
LSB2
LSB2
LSB2
VADIN = VSSA
MC9S08LH64 Series MCU Data Sheet, Rev. 4
38
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
ADC Characteristics
Table 19. 16-bit ADC Characteristics(VREFH = VDDA > 2.7V, VREFL = VSSA, FADCK < 4MHz, ADHSC=1)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+8/0
+12/0
+24/0
+24/0
LSB2
VADIN = VDDA
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.0
±2.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16 bit modes
D
—
-1 to 0
—
—
—
±0.5
14.3
13.8
13.4
13.1
12.4
14.5
14.0
13.7
13.4
12.6
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
13.5
13.0
12.7
12.4
11.6
—
—
—
—
—
Characteristic
Full-Scale
Error
Quantization
Error
Effective
Number of Bits
EQ
<13 bit modes
16 bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
C
ENOB
16 bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
Signal to Noise
plus Distortion
See ENOB
Total Harmonic
Distortion
16 bit differential mode
Avg=32
C
16 bit single-ended mode
Avg=32
D
16 bit differential mode
Avg=32
C
16 bit single-ended mode
Avg=32
D
Input Leakage
Error
all modes
D
EIL
Temp Sensor
Slope
-40°C– 25°C
D
m
Temp Sensor
Voltage
25°C
Spurious Free
Dynamic
Range
SINAD
D
Bits
SINAD = 6.02 ⋅ ENOB + 1.76
THD
—
-95.8
-90.4
—
—
—
91.0
96.5
—
—
—
—
SFDR
25°C– 125°C
VTEMP25
LSB2
IIn * RAS
—
1.646
—
—
1.769
—
—
701.2
—
Fin =
Fsample/100
dB
dB
Fin =
Fsample/100
dB
Fin =
Fsample/100
mV
IIn = leakage
current
(refer to DC
characteristics)
mV/°C
mV
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
39
VREF Specifications
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDA
Typical values assume VDDA = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
3
1 LSB = (VREFH - VREFL)/2N
2
3.13
VREF Specifications
Table 20. VREF Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Unit
1
Supply voltage
VDD
1.80
3.60
V
2
Operating temperature range
Top
–40
105
C
3
Maximum Load
—
—
10
mA
1.135
1.165
V
Operation across Temperature
4
V Room Temp
5
Untrimmed –40 °C
6
V Room Temp
Untrimmed –40 °C
–2 to –6 from Room Temp
Voltage
mV
Trimmed –40 °C
Trimmed –40 °C
±1 from Room Temp Voltage
mV
Untrimmed 0 °C
Untrimmed 0 °C
+1 to –2 from Room Temp
Voltage
mV
Trimmed 0 °C
±0.5 from Room Temp Voltage
mV
Untrimmed 50 °C
+1 to –2 from Room Temp
Voltage
mV
Trimmed 50 °C
±0.5 from Room Temp Voltage
mV
7
Trimmed 0 °C
8
Untrimmed 50 °C
9
Trimmed 50 °C
10
Untrimmed 85 °C
11
Trimmed 85 °C
12
Untrimmed 125 °C
13
Untrimmed 85 °C 0 to –4 from Room Temp Voltage
mV
Trimmed 85 °C
±0.5 from Room Temp Voltage
mV
Untrimmed 125 °C
–2 to –6 from Room Temp
Voltage
mV
Trimmed 125 °C
Trimmed 125 °C
±1 from Room Temp Voltage
mV
14
Load Bandwidth
—
—
—
—
15
Load Regulation Mode = 10 at 1mA load
Mode = 10
20
100
μV/mA
16
Line Regulation (Power Supply
Rejection)
DC
±0.1 from Room Temp Voltage
mV
AC
–60
dB
Power Consumption
17
Powered down Current (Stop Mode,
VREFEN = 0, VRSTEN = 0)
I
—
.100
μA
18
Bandgap only (Mode[1:0] 00)
I
—
75
μA
19
Low-Power buffer (Mode[1:0] 01)
I
—
125
μA
20
Tight-Regulation buffer (Mode[1:0] 10)
I
—
1.1
mA
MC9S08LH64 Series MCU Data Sheet, Rev. 4
40
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
LCD Specifications
Table 20. VREF Electrical Specifications (continued)
Num
Characteristic
21
RESERVED (Mode[1:0] 11)
3.14
Symbol
Min
Max
Unit
—
—
—
—
LCD Specifications
Table 21. LCD Electricals, 3-V Glass
#
C
1
D
Min
Typ
Max
LCD Supply Voltage
VLCD
.9
1.5
1.8
Unit
V
2
D
LCD Frame Frequency
fFrame
28
30
58
Hz
D
LCD Charge Pump Capacitance
CLCD
—
100
100
nF
4
D
LCD Bypass Capacitance
CBYLCD
—
100
100
nF
5
D
LCD Glass Capacitance
Cglass
—
2000
8000
pF
D
VIREG
D
VIREG TRIM Resolution
D
VIREG Ripple
6
8
9
10
11
1
Symbol
3
7
2
Characteristic
D
HRefSel = 0
.89
1.00
1.15
1.49
1.67
1.851
ΔRTRIM
1.5
—
—
HRefSel = 0
—
—
—
.1
HRefSel = 1
—
—
—
.15
IBuff
—
1
HRefSel = 1
VLCD Buffered Adder2
VIREG
V
%
VIREG
V
μA
VIREG Max can not exceed VDD –.15 V
VSUPPLY = 10, BYPASS = 0
3.15
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Table 22. Flash Characteristics
#
C
1
D
2
D
Characteristic
Symbol
Min
Supply voltage for program/erase
–40 °C to 85 °C
Vprog/erase
1.8
Supply voltage for read operation
VRead
1.8
fFCLK
tFcyc
frequency1
3
D
Internal FCLK
4
D
Internal FCLK period (1/FCLK)
5
6
P
P
Byte program time (random
Byte program time (burst
location)2
mode)2
Typical
Max
Unit
3.6
V
—
3.6
V
150
—
200
kHz
5
—
6.67
μs
—
tprog
9
tFcyc
tBurst
4
tFcyc
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
41
EMC Performance
Table 22. Flash Characteristics (continued)
#
C
7
P
Page erase time2
P
2
8
9
Characteristic
Symbol
Mass erase time
D
3
Byte program current
Min
Typical
Max
Unit
tPage
4000
tFcyc
tMass
20,000
tFcyc
RIDDBP
—
4
—
mA
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with
VDD = 3.0 V, bus frequency = 4.0 MHz.
2
3.16
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
3.16.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East).
4
Ordering Information
This appendix contains ordering information for the device numbering system.
Table 23. Device Numbering System
Memory
Device Number1
MC9S08LH64
MC9S08LH36
1
2
4.1
Available Packages2
Flash
RAM
64 KB
4000
80-pin LQFP
64 KB
4000
64-pin LQFP
36 KB
4000
80-pin LQFP
36 KB
4000
64-pin LQFP
See Table 1 for a complete description of modules included on each device.
See Table 24 for package information.
Device Numbering System
Example of the device numbering system:
MC9S08LH64 Series MCU Data Sheet, Rev. 4
42
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
Freescale Semiconductor
Package Information
MC 9 S08 LH 64
C XX
Status
(MC = Fully Qualified)
Package designator (see Table 24)
Temperature range
(C = –40 °C to 85 °C)
Memory
(9 = Flash-based)
Core
Approximate flash size in KB
Family
4.2
Package Information
Table 24. Package Descriptions
Pin Count
4.3
Package Type
Abbreviation
Designator
Case No.
Document No.
80
Low Quad Flat Package
LQFP
LK
917A
98ASS23237W
64
Low Quad Flat Package
LQFP
LH
840F
98ASS23234W
Mechanical Drawings
Table 24 provides the available package types and their document numbers. The latest package
outline/mechanical drawings are available on the MC9S08LH64 Series Product Summary pages at
http://www.freescale.com.
To view the latest drawing, either:
• Click on the appropriate link in Table 24, or
• Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate
document number (from Table 24) in the “Enter Keyword” search box at the top of the page.
MC9S08LH64 Series MCU Data Sheet, Rev. 4
Freescale Semiconductor
PRELIMINARY-SUBJECT TO CHANGE WITHOUT NOTICE
43
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MC9S08LH64
Rev. 4, 04/2010
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